Table of Contents
Advertisement
4 iniTial ReSeT
4.3
Simultaneous high input to P0x Ports (P00–P03)
Another way of executing initial reset externally is to input high level signals simultaneously to the P0x ports (P00–
P03) selected by a mask option. Since this initial reset passes through the noise reject circuit, maintain the specified
input port terminals at high level for at least 1.5 msec (when the oscillation frequency f
normal operation. The noise reject circuit does not operate immediately after turning the power on until the oscilla-
tion circuit starts oscillating. Therefore, maintain the specified input port terminals at high level for at least 1.5 msec
(when the oscillation frequency f
P0x ports (P00–P03) that can be selected by a mask option.
When, for instance, mask option 4 (P00 * P01 * P02 * P03) is selected, initial reset is executed when the signals
input to the four ports P00–P03 are all high at the same time. When 2 or 3 is selected, the initial reset is done when
a key entry including a combination of selected input ports is made. Further, the time authorize circuit mask option
is selected when this reset function is selected. The time authorize circuit checks the input time of the simultaneous
high input and performs initial reset if that time is the defined time (1 to 2 sec) or more. If using this function, make
sure that the specified ports do not go high at the same time during ordinary operation.
4.4
internal Register at initial Resetting
Initial reset initializes the CPU as shown in Table 4.4.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including NMI are masked
after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in the extend-
ed addressing mode. If an instruction which does not permit extended operation is used as the following instruction,
the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
Name
Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
4-2
is 32.768 kHz) after oscillation starts. Table 4.3.1 shows the combinations of
OSC1
Table 4.
3.1 Combinations of P0x ports
No.
1
2
3
4
Table 4.
4.1 Initial values
CPU core
Symbol Bit length Set value
A
4
Undefined
B
4
Undefined
EXT
8
Undefined
X
16
Undefined
Y
16
Undefined
PC
16
0110H
SP1
8
Undefined
SP2
8
Undefined
Z
1
Undefined
C
1
Undefined
I
1
E
1
Q
16
Undefined
Seiko epson Corporation
Combination
Not used
P00 * P01
P00 * P01 * P02
P00 * P01 * P02 * P03
Peripheral circuit
Name
RAM
Display memory
Other peripheral circuits
0
0
S1C63003/004/008/016 TeChniCal Manual
is 32.768 kHz) during
OSC1
Bit length Set value
4
Undefined
4
Undefined
*
–
* See "I/O Memory Map."
(Rev. 1.1)
Advertisement
Table of Contents
