Sharp DV-500D Technical Manual page 97

DV-560H
Pin No. Terminal name
45 EQIN
46 EQOUT
47 DVDsel
48 RFGain
49 VCC3
50 MDIN
51 LDC
52 LDOUT
53 LDPsel
54 RFPIN
55 RFNIN
56 VCC1
57 AIN
58 BIN
59 CIN
60 DIN
61 VrefIN
62 EIN
63 FIN
64 S/Dsel
12-4. IC707 IX1473GE
SERVO PROCCESSOR
Pin No. Terminal name
1 VSS
2 BCK
3 AOUT
4 DOUT
5 MBOV
6 IPF
7 SBOK
8 CLCK
9 VDD
10 VSS
11 DATA
12 SFSY
13 SBSY
14 SPCK
15 SPDA
16 COFS
17 MONIT
18 VDD
I/O
I DVD/CD-EQ input.
O Output after passing of RFNIN and RFPIN VCA.
I DVD/CD selection control input. H:CD L: DVD (PNP open space)
I RF signal VCA control input.
– RF system VCC.
I Laser diode APC monitor input.
I LD ON/OFF control input. H:ON, L:OFF
O LD external current driver control output.
I APC control polarity selection input. H: Positive polarity L: Negative polarity.
I RF signal nonreverse input from PU.
I RF signal reverse input from PU.
– Servo system VCC.
I Main beam 4-division detector A input for focus error (FE) generation.
I Main beam 4-division detector B input for focus error (FE) generation.
I Main beam 4-division detector C input for focus error (FE) generation.
I Main beam 4-division detector D input for focus error (FE) generation.
I 2.1V reference voltage potential input.
I Sub-bean E input.
I Sub-bean F input.
I Single/double layer system selection input. H: Double layer, L: Single layer
I/O
– Digital ground terminal.
O Bit clock (1.4122MHz) output terminal.
O Audio data output terminal.
O Digital out output terminal.
O Buffer memory over signal output terminal. Over: "H"
O Correction flag output terminal. When correction disable symbol
is given if AOUT output is C2 correction: "H".
O Sub-code Q data CRCC judgment result output terminal.
Judgment result OK: "H".
I/O Sub-code P to W data read clock output/input terminal.
Selectable with command bit.
– Digital + power terminal
– Digital ground terminal
O Sub code P-W data output terminal.
O Playback system frame sync signal output terminal.
O Subcode block sync output terminal.
When subcode sync is detected, S1 position: "H".
O Processor status signal read clock (176.4 kHz) output terminal.
O Processor status signal output terminal.
O Correction system frame clock (7.35 kHz) output terminal.
O LSI internal signal monitor terminal.
DSP internal flag and PLL system clock can be monitored with
microcomputer command.
– Digital + power terminal.
Operation function
Operation function
12-4
Remarks