Table 179. Core Debug Registers - ST STM32L0x3 Reference Manual

RM0367
33.6 Core debug
Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the debug access port. It consists of four registers:
Register
DHCSR
DCRSR
DCRDR
DEMCR
These registers are not reset by a system reset. They are only reset by a power-on reset.
Refer to the Cortex
To Halt on reset, it is necessary to:
• enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control
Register
•
enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register
33.7 BPU (Break Point Unit)
The Cortex
subset of the Flash Patch and Breakpoint (FPB) block available in Armv7-M (Cortex
and Cortex
33.7.1 BPU functionality
The processor breakpoints implement PC based breakpoint functionality.
Refer the Armv6-M Arm
Manual for more information about the BPU CoreSight identification registers, and their
addresses and access types.

Table 179. Core debug registers

The 32-bit Debug Halting Control and Status Register
This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core Register Selector Register:
This selects the processor register to transfer data to or from.
The 32-bit Debug Core Register Data Register:
This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control Register:
This provides Vector Catching and Debug Monitor Control.
®
-M0+ TRM for further details.
®
-M0+ BPU implementation provides four breakpoint registers. The BPU is a
®
-M4).
®
and the Arm
Description
®
CoreSight Components Technical Reference
RM0367 Rev 7
Debug support (DBG)
®
-M3
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