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Getting started with STM32H723/733, STM32H725/735 and STM32H730 Value
Introduction
This application note is intended for system designers who develop applications based on STM32H723/33, STM32H725/35 and
STM32H730 microcontroller lines, and need an implementation overview of the following hardware features:
•
Power supply
•
Package selection
•
Clock management
•
Reset control
•
Boot mode settings
•
Debug management.
This document describes the minimum hardware resources required to develop an application based on STM32H723/33,
STM32H725/35 and STM32H730 microcontrollers.
Reference documents
•
STM32H72x and STM32H73x datasheets
•
STM32H723/733, STM32H725/735 and STM32H730 advanced Arm
•
STM32H723/733, STM32H725/735 and STM32H730 errata sheet (ES0491)
The following documents are available on
•
Oscillator design guide for STM8S, STM8A and STM32 microcontrollers application note (AN2867)
•
STM32 microcontroller system memory boot mode application note (AN2606).
AN5419 - Rev 2 - May 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
website.
Line hardware development
®
-based 32-bit MCUs (RM0468)
AN5419
www.st.com
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Table of Contents
Related Manuals for ST STM32H723
Summary of Contents for ST STM32H723
- Page 1 Getting started with STM32H723/733, STM32H725/735 and STM32H730 Value Line hardware development Introduction This application note is intended for system designers who develop applications based on STM32H723/33, STM32H725/35 and STM32H730 microcontroller lines, and need an implementation overview of the following hardware features: •...
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Page 2: General Information
AN5419 General information General information ® This document applies to STM32H723/33, STM32H725/35 and STM32H730Arm -based microcontroller lines. Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. AN5419 - Rev 2 page 2/50... -
Page 3: Power Supplies
AN5419 Power supplies Power supplies Introduction The STM32H723/33, STM32H725/35 and STM32H730 are highly integrated microcontrollers that are based on ® ® the Arm Cortex -M7 32-bit core (refer to the datasheets/databriefs for details). The STM32H723/33, STM32H725/35 and STM32H730 microcontrollers require at least one single power supply to be fully operational. - Page 4 AN5419 Introduction Figure 1. Power supplies VDDSMPS VLXSMPS Step Down VFBSMPS Converter regulator VSSSMPS VCAP Core domain (V CORE Voltage VDDLDO regulator D3 domain (System D1 domain logic, (CPU, peripherals, D2 domain EXTI, RAM) Peripherals, (peripherals, logic RAM) RAM) Flash VDD domain HSI, CSI, Power...
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Page 5: Table 1. Pwr Input/Output Signals Connected To Package Pins/Balls
VDDSMPS, VLXSMPS, VFBSMPS and VSSSMPS are available only on STM32H725/735 and STM32H730 devices. Note: On STM32H723/733, VDDLDO is not available on a pin/ball. It is internally connected to VDD. Table 1. PWR input/output signals connected to package pins/balls Pin name... - Page 6 AN5419 Introduction Figure 2. System supply configuration DDSMPS DDSMPS LXSMPS LXSMPS SMPS SMPS FBSMPS (off) (on) FBSMPS <= V DDLDO SSSMPS SSSMPS DDLDO CORE DDLDO CORE V reg V reg (on) (off) 1. LDO Supply 2. Direct SMPS Supply DDSMPS DDSMPS LXSMPS LXSMPS...
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Page 7: External Power Supplies And Components
The external battery can be charged through the internal 5 kΩ or 1.5 kΩ resistor (see the reference manual STM32H723/733, STM32H725/735 and STM32H730 VBAT 1.2 to 3.6 V 1 μF ceramic and 100 nF close to the VBAT pin ®... - Page 8 AN5419 Introduction Package pin/ Voltage range External components Comments ball LDO enabled and SMPS enabled or disabled: 2.2 μF ESR < 100 mΩ for VCAP1 If the VCAP3 pin is available (depending on the VOS0/VOS1/ package), it must be connected to the other VCAP pins 2.2 μF ESR <...
- Page 9 AN5419 Introduction Figure 3. Power supply component layout STM32H723/733/ DDSMPS 725/735/730 SMPS 2.2 μH 4.7 μ F 10 μF LXSMPS Switched Mode 220 pF Power Supply 10 μF 10 μF step down FBSMPS converter SSSMPS SMPS enabled SMPS disabled CAP1/2 Core domain 2.2 μF...
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Page 10: Digital Circuit Core Supply (Vcore)
In system Stop mode, the digital core voltage can be reduced to improve the power consumption (voltage scaling SVOS3 to SVOS5). For a detailed definition on the available power modes please read the power control (PWR) chapter of the ® reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced Arm -based 32-bit MCUs (RM0468). 2.1.3... -
Page 11: Figure 4. Vdd33Usb Connected To
AN5419 Introduction Figure 4. VDD33USB connected to V power supply DD33USB_MAX DD_MAX DD33USB DDUSB_MIN functional DD_MIN time Power- Operating mode Power-on down Figure 5. VDD33USB connected to external power supply DD33USB_MAX functional DD33USB DD33USB_MIN DD33USB VDD33USB forbidden forbidden area area DD_MIN time Power-... -
Page 12: Battery Backup Domain
AN5419 Introduction Figure 6. VDD50USB power supply DD50USB DD50USB = 5.5 V DD50USB_MAX = 4.0 V DD50USB_MIN time Power- Operating mode Power-on down 2.1.5 Battery Backup domain Backup domain description To retain the content of the RTC Backup registers, Backup SRAM, and supply the RTC when V is turned off, the VBAT pin can be connected to an optional 1.2-3.6 V standby voltage supplied by a battery. - Page 13 The LDO regulator supplies the core and the backup domains; – The LDO regulator output voltage can be dynamically scaled by programming the voltage scaling (VOS0 to VOS3) depending on the required performance (see the reference manual STM32H723/733, ® STM32H725/735 and STM32H730 advanced Arm -based 32-bit MCUs (RM0468)).
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Page 14: Smps Step-Down Converter
In this configuration, the SMPS will run in one of the following modes: – Run mode: ◦ The converter can be dynamically scaled by programming the voltage scaling (VOS0 to VOS3) to the required performance (see the reference manual STM32H723/733, STM32H725/735 and ® STM32H730 advanced Arm -based 32-bit MCUs (RM0468)). –... -
Page 15: Reset And Power Supply Supervisor
AN5419 Reset and power supply supervisor Reset and power supply supervisor 2.2.1 Power-on reset (POR)/power-down reset (PDR) The devices have an integrated POR/PDR circuitry which ensures correct operational start-up from 1.71 V. The device remains in reset mode while V is below a specified threshold, V , without the need for an POR/PDR... -
Page 16: Brownout Reset (Bor)
PLS[2:0] bits in the PWR power control register (PWR_CR1). The PVD is enabled by setting the PVDE bit. The selectable threshold is between 1.95 V and 2.85 V (see the reference manual STM32H723/733, ® STM32H725/735 and STM32H730 advanced Arm -based 32-bit MCUs (RM0468)). -
Page 17: Analog Voltage Detector (Avd)
AN5419 Reset and power supply supervisor 2.2.4 Analog voltage detector (AVD) The AVD can be used to monitor V power supply by comparing it to a threshold selected through the ALS[1:0] bits of the PWR power control register (PWR_CR1). The threshold value can be configured to 1.7, 2.1, 2.5 or 2.8 V (refer to the STM32H72x and STM32H73x datasheets for the actual values). -
Page 18: Clocks
OSC32_IN pins (HSE bypass and LSE bypass modes) Figure 10. Clock generation and clock tree schematic shows the clock generation and clock tree architecture. For detail explanation refer to reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced ® -based 32-bit MCUs (RM0468). - Page 19 AN5419 Introduction Figure 10. Clock generation and clock tree VDD Domain LSION or IWDG1 activated lsi_ck tempo IWDG1 RTCSRC VSW (Backup) RTCEN LSEON lse_ck lse_ck rcc_rtc_ck OSC32_IN tempo lsi_ck RTC/AWU OSC32_OUT hse_1M_ck MCO1SEL RTCPRE MCO1PRE hsi_ck ÷ 2 to 63 lse_ck MCO1 ÷...
- Page 20 Synchronization source for the HSI48MHz embedded oscillator Clock Recovery System (CRS) One of the three possible sync signal, see the reference SYNC External sync signal manual STM32H723/733, STM32H725/735 and ® STM32H730 advanced Arm -based 32-bit MCUs (RM0468). 1. Oscillator design guide for STM8S, STM8A and STM32 microcontrollers application note (AN2867)
- Page 21 To optimize power consumption, each clock source can be switched on or off independently when it is not used. ® Refer to the reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced Arm -based 32-bit MCUs (RM0468) for a detailed description of the clock tree. This document provides a complete view of clock usage by peripheral is provided in the Kernel clock distribution overview.
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Page 22: Hse And Lse Bypass (External User Clock)
AN5419 Introduction 3.1.1 HSE and LSE bypass (external user clock) In this mode, an external clock source must be provided to OSC_IN/OSC32_IN pins. For LSE bypass, the external source has to be "low swing".The signal (square, sinus or triangle) with ~50% duty cycle drives the OSC_IN/OSC32_IN pin. -
Page 23: Lse Oscillator Clock
• SYNC external signal provided through pin; • LSE oscillator output; • USB SOF packet reception. For more details refer to the reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced ® -based 32-bit MCUs (RM0468). AN5419 - Rev 2 page 23/50... -
Page 24: Alternate Function Mapping To Pins
Analog inputs for ADC1, ADC2 and ADC3 The STM32H723/33, STM32H725/35 and STM32H730 microcontrollers embed four pads with a direct connection to the ADC (PA0_C; PA1_C; PC2_C; PC3_C). It avoids the parasitic impedances of a conventional pad and thereby enhancing the performance of the ADC. -
Page 25: Packages Having Pxy_C But Not The Peer Pxy
Closing the switch in the pad (GPIOx_MODER bit) connects an ADC slow input to the Pxy pad (See Figure ADC ® connectivity in the reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced Arm -based 32-bit MCUs (RM0468)). Also refer to the ADC STM32H72x and STM32H73x datasheets characteristic table “Sampling rate for Slow channels”. -
Page 26: Boot Configuration
Boot configuration Boot configuration Boot mode selection In STM32H723/33, STM32H725/35 and STM32H730 microcontrollers, two different boot spaces can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 or BOOT_ADD1 option bytes as shown in the Table 5. -
Page 27: Boot Pin Connection
Resistor values are given only as a typical example. System bootloader mode The embedded bootloader code is located in the system memory. It is programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces. -
Page 28: Debug Management
The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port. In the SWJ-DP, the two SW-DP JTAG pins the are multiplexed with some of the JTAG-DP five JTAG pins. For more details on the SWJ debug port refer to the reference manual STM32H723/733, STM32H725/735 and ®... -
Page 29: Pinout And Debug Port Pins
JTAG-DP disabled and SW-DP enabled JTAG-DP disabled and SW-DP disabled Released For more details on how to disable SWJ-DP port pins, refer to the STM32H723/733, STM32H725/735 and ® STM32H730 advanced Arm -based 32-bit MCUs (RM0468) I/O pin alternate function multiplexer and mapping section. -
Page 30: Internal Pull-Up And Pull-Down On Jtag Pins
JTAG I/O is released by the user software. 6.3.4 SWJ debug port connection with standard JTAG connector Figure 15. JTAG connector implementation shows the connection between STM32H723/33, STM32H725/35 and STM32H730 microcontrollers and a standard JTAG connector. Figure 15. JTAG connector implementation JTAG connector CN9... -
Page 31: Recommendations
AN5419 Recommendations Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to the ground (V ) and another dedicated to the V supply. This provides both good decoupling and good shielding effect. -
Page 32: Other Signals
AN5419 Other signals Other signals When designing an application, the EMC performance can be improved by closely studying: • Signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LED commands). For these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve the EMC performance. -
Page 33: Reference Design
The STM32H725G-DK Discovery board and the NUCLEO-H723ZG and NUCLEO-H725ZG Nucleo boards are good references that can be used as a basis for a specific application development. Details of these boards are available on www.st.com website. AN5419 - Rev 2 page 33/50... -
Page 34: Recommended Pcb Routing Guidelines For Stm32H723/733, Stm32H725/735 And Stm32H730 Microcontrollers
AN5419 Recommended PCB routing guidelines for STM32H723/733, STM32H725/735 and STM32H730 microcontrollers Recommended PCB routing guidelines for STM32H723/733, STM32H725/735 and STM32H730 microcontrollers PCB stack-up In order to reduce the reflections on high speed signals, the impedance between the source, sink and transmission lines have to be matched. -
Page 35: Crystal Oscillator
Figure 20. Example of decoupling capacitor placed underneath shows an example of decoupling capacitor placement underneath STM32H723/33, STM32H725/35 and STM32H730 microcontroller, closer to the pins and with less vias. Figure 19. -
Page 36: High Speed Signal Layout
The total bus CARD capacitance is C + N*C where the host is an STM32H723/33, STM32H725/35 and Host Card STM32H730 microcontroller, the bus is all the signals and Card is SD card. Figure 21. microSD card interconnection example Figure 22. -
Page 37: Flexible Memory Controller (Fmc) Interface
AN5419 High speed signal layout Figure 21. microSD card interconnection example VDD_ SD STM32H7 microSD Card SUPPLY Socket SD_REF SDMMC1_CK PC12 VDD is not CLK_IN CLK_SD switched between 1.8V SDMMC1_CKIN CLK_FB and 3.3V Stays always SDMMC1_CMD CMD_H CMD_SD at 3.3V even in fast mode SDMMC1_CDIR DIR_CMD... -
Page 38: Octo-Spi Interface
Interface connectivity The Octo-SPI is a specialized communication interface targeting single, dual, quad and octal communication. ® (Refer to the reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced Arm -based 32- bit MCUs (RM0468)) for details) Refer to the STM32H72x and STM32H73x datasheets for the full electrical characteristic. - Page 39 AN5419 High speed signal layout Figure 23. Octo-SPI interconnection example STM32H7 Octo-SPI memory OCSPI1_NCS PC11 OCSPI1_DQS RWDS (=DQSM) OCSPI1_CLK OCSPI1_NCLK PB12 PD11/PC10/PE2/PA1 8 bits OCSPI1_IO0….IO7 PC1/PE8/PE9/PE10 DQ[0:7] GPIO RSTO GPIO OCTOSPI1 NRST RESET# OCTOSPI2 Octo-SPI memory OCSPI2_NCS PG12 OCSPI2_DQS PG15 RWDS (=DQSM) OCSPI2_CLK OCSPI2_NCLK...
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Page 40: Dfsdm Interface
32-bit MCUs (RM0468) for details). It can, for instance, handle data stream issued from sensors or pulse density modulation (PDM) microphones. The DFSDM embedded in STM32H723/33, STM32H725/35 and STM32H730 devices is composed of eight filters ® (see reference manual STM32H723/733, STM32H725/735 advanced and STM32H730 Arm... -
Page 41: Embedded Trace Macrocell (Etm)
AN5419 High speed signal layout Figure 25. Stereo microphone interconnection STM32H7 Digital PDM Stereo Microphones CKOUT DATIN0 Filter 0 Transceiver 0 DATIN1 Filter 1 Transceiver 1 Filter 2 Transceiver 2 Filter 3 Transceiver 3 Filter 4 Transceiver 4 Filter 5 Transceiver 5 DATIN6 Filter 6... -
Page 42: Use Case Examples
AN5419 Use case examples Use case examples STM32CubeMX must be used to determine the most appropriate package for a given use case. Table 11. Use case examples gives some typical use case examples. It defines the package which supports a specific use case and identifies the peripherals that are available. -
Page 43: Conclusion
AN5419 Conclusion Conclusion This application note must be used as reference when starting a new design with an STM32H723/33, STM32H725/35 and STM32H730 microcontroller. AN5419 - Rev 2 page 43/50... -
Page 44: Revision History
AN5419 Revision history Table 12. Document revision history Date Version Changes 13-Nov-2019 Initial release. Changed document classification to public. Added STM32H730 Value Line. Updated external components for VLXSMPS and VDDLDO in Table 2. Power supply connection and updated values of external capacitors connected to VLXSMPS in Figure 3. -
Page 45: Table Of Contents
AN5419 Contents Contents General information ............. . . 2 Power supplies . - Page 46 Description ..............33 Recommended PCB routing guidelines for STM32H723/733, STM32H725/735 and STM32H730 microcontrollers .
- Page 47 AN5419 Contents 9.4.4 DFSDM interface ............40 9.4.5 Embedded trace macrocell (ETM).
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Page 48: List Of Tables
Boot modes............... 26 Table 6. STM32H723/733, STM32H725/735 and STM32H730 microcontroller bootloader communication peripherals . . . 27 Table 7. -
Page 49: List Of Figures
AN5419 List of figures List of figures Figure 1. Power supplies ..............4 Figure 2. - Page 50 ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’...
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