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ST STM32L4 5 Series Reference Manual

Advanced arm-based 32-bit mcus

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STM32L4x5 and STM32L4x6 advanced ARM

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32L4x5/STM32L4x6 microcontroller memory and peripherals.

The STM32L4x5/STM32L4x6 is a family of microcontrollers with different memory sizes,

packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

corresponding datasheets.

For information on the ARM

Reference Manual.

Related documents

• Cortex

• STM32L475xx, STM32L476xx, STM32L486xx, STM32L496xx and STM32L4A6xx

datasheets

• STM32F3, STM32F4 and STM32L4 Series Cortex

March 2017

®

Cortex

®

-M4 Technical Reference Manual, available from: http://infocenter.arm.com

DocID024597 Rev 5

Reference manual

®

-M4 core, please refer to the Cortex

®

-M4 programming manual (PM0214)

RM0351

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-based 32-bit MCUs

®

-M4 Technical

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Summary of Contents for ST STM32L4 5 Series

Page 1 Reference Manual. Related documents ® • Cortex -M4 Technical Reference Manual, available from: http://infocenter.arm.com • STM32L475xx, STM32L476xx, STM32L486xx, STM32L496xx and STM32L4A6xx datasheets ® • STM32F3, STM32F4 and STM32L4 Series Cortex -M4 programming manual (PM0214) March 2017 DocID024597 Rev 5 1/1830 www.st.com...
Page 2: Table Of Contents
Contents RM0351 Contents Documentation conventions ....... . . 67 List of abbreviations for registers ....... 67 Glossary .
Page 3 RM0351 Contents 3.3.3 Read access latency ........97 3.3.4 Adaptive real-time memory accelerator (ART Accelerator™) .
Page 4 Contents RM0351 Firewall functional description ....... . 138 4.3.1 Firewall AMBA bus snoop ........138 4.3.2 Functional requirements .
Page 5 RM0351 Contents 5.3.5 Low-power sleep mode (LP sleep) ......169 5.3.6 Stop 0 mode ..........170 5.3.7 Stop 1 mode .
Page 6 Contents RM0351 6.1.1 Power reset ..........199 6.1.2 System reset .
Page 7 RM0351 Contents 6.4.12 AHB3 peripheral reset register (RCC_AHB3RSTR) ....240 6.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1) ... . 240 6.4.14 APB1 peripheral reset register 2 (RCC_APB1RSTR2) .
Page 8 Contents RM0351 CRS low-power modes ........283 CRS interrupts .
Page 9 RM0351 Contents 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I) ..302 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..I) ..........303 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..I) .
Page 10 Contents RM0351 10.3.3 From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8) ... . 327 10.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC (DAC1/DAC2) ......... . . 328 10.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16) and EXTI to DFSDM1 .
Page 11 RM0351 Contents 11.5.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) ....... . 348 11.5.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) .
Page 12 Contents RM0351 12.5.7 DMA2D background offset register (DMA2D_BGOR) ... . . 375 12.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) ..376 12.5.9 DMA2D foreground color register (DMA2D_FGCOLR) ... . 378 12.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) .
Page 13 RM0351 Contents 14.5 EXTI registers ..........402 14.5.1 Interrupt mask register 1 (EXTI_IMR1) .
Page 14 Contents RM0351 16.4.1 NOR/PSRAM address mapping ......420 16.4.2 NAND Flash memory address mapping ..... . . 421 16.5 NOR Flash/PSRAM controller .
Page 15 RM0351 Contents 17.4.13 QUADSPI error management ....... 485 17.4.14 QUADSPI busy bit and abort functionality ..... . 485 17.4.15 nCS behavior .
Page 16 Contents RM0351 18.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) ..518 18.4.13 Single conversion mode (CONT=0) ......519 18.4.14 Continuous conversion mode (CONT=1) .
Page 17 RM0351 Contents 18.6.11 ADC regular sequence register 1 (ADC_SQR1) ....597 18.6.12 ADC regular sequence register 2 (ADC_SQR2) ....598 18.6.13 ADC regular sequence register 3 (ADC_SQR3) .
Page 18 Contents RM0351 19.5.1 DAC control register (DAC_CR) ......633 19.5.2 DAC software trigger register (DAC_SWTRGR) ....636 19.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) .
Page 19 RM0351 Contents 20.4.4 Synchronization ......... . 652 20.4.5 Capture modes .
Page 20 Contents RM0351 22.1 Introduction ..........675 22.2 COMP main features .
Page 21 RM0351 Contents 23.5.6 OPAMP2 offset trimming register in low-power mode (OPAMP2_LPOTR) ........698 23.5.7 OPAMP register map .
Page 22 Contents RM0351 24.7.5 DFSDM channel data input register (DFSDM_CHyDATINR) (y=0..7) ..........733 24.8 DFSDM filter x module registers (x=0..3) .
Page 23 RM0351 Contents 25.4 LCD low-power modes ........778 25.5 LCD interrupts .
Page 24 Contents RM0351 26.6.11 TSC register map ......... 805 True Random Number Generator (RNG) .
Page 25 RM0351 Contents 28.7 AES cipher message authentication code mode (CMAC) ... 829 28.8 Data type ..........831 28.9 Operating modes .
Page 26 Contents RM0351 29.3.2 HASH internal signals ........854 29.3.3 About secure hash algorithms .
Page 27 RM0351 Contents 30.3.12 Asymmetric PWM mode ........908 30.3.13 Combined PWM mode .
Page 28 Contents RM0351 30.4.19 TIM1/TIM8 DMA control register (TIMx_DCR) ....963 30.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) ... 964 30.4.21 TIM1 option register 1 (TIM1_OR1) .
Page 29 RM0351 Contents 31.3.20 DMA burst mode ........1025 31.3.21 Debug mode .
Page 30 Contents RM0351 32.4.6 Input capture mode ........1069 32.4.7 PWM input mode (only for TIM15) .
Page 31 RM0351 Contents 32.6 TIM16/TIM17 registers ........1113 32.6.1 TIM16/TIM17 control register 1 (TIMx_CR1) .
Page 32 Contents RM0351 33.4.6 TIM6/TIM7 counter (TIMx_CNT) ......1144 33.4.7 TIM6/TIM7 prescaler (TIMx_PSC) ......1145 33.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR) .
Page 33 RM0351 Contents Infrared interface (IRTIM) ........1170 Independent watchdog (IWDG) .
Page 34 Contents RM0351 Real-time clock (RTC) ........1186 38.1 Introduction .
Page 35 RM0351 Contents 38.6.14 RTC time-stamp sub second register (RTC_TSSSR) ... . 1221 38.6.15 RTC calibration register (RTC_CALR) ......1222 38.6.16 RTC tamper configuration register (RTC_TAMPCR) .
Page 36 Contents RM0351 39.7.3 Own address 1 register (I2C_OAR1) ......1291 39.7.4 Own address 2 register (I2C_OAR2) ......1292 39.7.5 Timing register (I2C_TIMINGR) .
Page 37 RM0351 Contents 40.7 USART interrupts ......... 1344 40.8 USART registers .
Page 38 Contents RM0351 41.7.2 Control register 2 (LPUART_CR2) ......1400 41.7.3 Control register 3 (LPUART_CR3) ......1402 41.7.4 Baud rate register (LPUART_BRR) .
Page 39 RM0351 Contents 42.6.6 SPI Rx CRC register (SPIx_RXCRCR) ..... . . 1445 42.6.7 SPI Tx CRC register (SPIx_TXCRCR) ..... . . 1445 42.6.8 SPI register map .
Page 40 Contents RM0351 44.1 Introduction ..........1491 44.2 SWPMI main features .
Page 41 RM0351 Contents 45.4.3 Operating voltage range validation ......1535 45.4.4 Card identification process ....... . 1535 45.4.5 Block write .
Page 42 Contents RM0351 45.8.9 SDMMC data control register (SDMMC_DCTRL) ....1565 45.8.10 SDMMC data counter register (SDMMC_DCOUNT) ... . . 1567 45.8.11 SDMMC status register (SDMMC_STA) .
Page 43 RM0351 Contents 46.9.1 Register access protection ....... . 1595 46.9.2 CAN control and status registers .
Page 44 Contents RM0351 47.11.1 Peripheral FIFO architecture ....... 1640 47.11.2 Host FIFO architecture ........1641 47.11.3 FIFO RAM allocation .
Page 45 RM0351 Contents 47.15.23 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) ........1682 47.15.24 OTG Host all channels interrupt register (OTG_HAINT) .
Page 46 Contents RM0351 47.15.47 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..5, where x = Endpoint_number) ..... . . 1709 47.15.48 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) .
Page 47 RM0351 Contents ® 48.6.3 Cortex -M4 TAP ........1782 ®...
Page 48 Contents RM0351 48.17.5 Transmission of the synchronization frame packet ....1803 48.17.6 Synchronous mode ........1803 48.17.7 Asynchronous mode .
Page 49 RM0351 List of tables List of tables Table 1. STM32L475xx/476xx/486xx devices memory map and peripheral register boundary addresses ............. . 75 Table 2.
Page 50 List of tables RM0351 Table 47. DMA register map and reset values ......... 354 Table 48.
Page 51 RM0351 List of tables Table 99. QUADSPI pins ............473 Table 100.
Page 52 List of tables RM0351 Table 149. Effect of low-power modes on the OPAMP ........694 Table 150.
Page 53 RM0351 List of tables Table 198. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) ............1122 Table 199.
Page 54 List of tables RM0351 Table 246. LPUART interrupt requests..........1395 Table 247.
Page 55 RM0351 List of tables Table 298. Receive mailbox mapping..........1590 Table 299.
Page 56 List of figures RM0351 List of figures Figure 1. System architecture for STM32L475xx/476xx/486xx devices ..... . 69 Figure 2. System architecture for STM32L496xx/4A6xx devices......70 Figure 3.
Page 57 RM0351 List of figures Figure 49. Muxed read access waveforms ..........440 Figure 50.
Page 58 List of figures RM0351 Figure 97. Right alignment (offset enabled, signed value)....... . . 541 Figure 98.
Page 59 RM0351 List of figures Figure 145. DAC sample and hold mode phase diagram ........625 Figure 146.
Page 60 List of figures RM0351 Figure 196. CTR mode encryption ........... . 825 Figure 197.
Page 61 RM0351 List of figures Figure 248. Center-aligned PWM waveforms (ARR=8) ........907 Figure 249.
Page 62 List of figures RM0351 Figure 299. Output stage of capture/compare channel (channel 1)......1002 Figure 300. PWM input mode timing ..........1004 Figure 301.
Page 63 RM0351 List of figures Figure 349. Measuring time interval between edges on 2 signals ......1083 Figure 350.
Page 64 List of figures RM0351 Figure 398. Timeout intervals for t ........1269 LOW:SEXT LOW:MEXT Figure 399.
Page 65 RM0351 List of figures Figure 449. Hardware/software slave select management ....... . 1419 Figure 450.
Page 66 List of figures RM0351 Figure 500. Data path state machine (DPSM) ......... . 1529 Figure 501.
Page 67: Documentation Conventions
RM0351 Documentation conventions Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit. Reading this bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1.
Page 68: System And Memory Overview
System and memory overview RM0351 System and memory overview System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Up to six masters: ® – Cortex -M4 with FPU core I-bus ® – Cortex -M4 with FPU core D-bus ®...
Page 69: Figure 1. System Architecture For Stm32L475Xx/476Xx/486Xx Devices
RM0351 System and memory overview Figure 1. System architecture for STM32L475xx/476xx/486xx devices DocID024597 Rev 5 69/1830...
Page 70: S0: I-Bus
System and memory overview RM0351 Figure 2. System architecture for STM32L496xx/4A6xx devices 2.1.1 S0: I-bus ® This bus connects the instruction bus of the Cortex -M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory, SRAM1, SRAM2 and external memories through QUADSPI or the FMC.
Page 71: S3, S4: Dma-Bus
RM0351 System and memory overview bus are the SRAM1, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the QUADSPI or the FMC. On STM32L496xx/4A6xx devices, the SRAM2 is also accessible on this bus to allow continuous mapping with SRAM1.
Page 72: Memory Organization
RM0351 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 73: Figure 3. Memory Map For Stm32L475Xx/476Xx/486Xx Devices
RM0351 Figure 3. Memory map for STM32L475xx/476xx/486xx devices DocID024597 Rev 5 73/1830...
Page 74: Figure 4. Memory Map For Stm32L496Xx/4A6Xx Devices
RM0351 Figure 4. Memory map for STM32L496xx/4A6xx devices It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. 74/1830 DocID024597 Rev 5...
Page 75: Memory Map And Register Boundary Addresses
RM0351 All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to Memory map and register boundary addresses and peripheral sections. 2.2.2 Memory map and register boundary addresses See the datasheet corresponding to your device for a comprehensive diagram of the memory map.
Page 76 RM0351 Table 1. STM32L475xx/476xx/486xx devices memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map Section 26.6.11: TSC register 0x4002 4000 - 0x4002 43FF 1 KB 0x4002 3400 - 0x4002 3FFF 1 KB Reserved Section 15.4.6: CRC register 0x4002 3000 - 0x4002 33FF 1 KB...
Page 77 RM0351 Table 1. STM32L475xx/476xx/486xx devices memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map Section 32.6.20: TIM16/TIM17 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 register map Section 32.6.20: TIM16/TIM17 0x4001 4400 - 0x4001 47FF 1 KB TIM16 register map...
Page 78 RM0351 Table 1. STM32L475xx/476xx/486xx devices memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map 0x4000 9800 - 0x4000 FFFF 26 KB Reserved Section 34.7.11: LPTIM register 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8C00 - 0x4000 93FF 2 KB...
Page 79 RM0351 Table 1. STM32L475xx/476xx/486xx devices memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map Section 40.8.12: USART 0x4000 5000 - 0x4000 53FF 1 KB UART5 register map Section 40.8.12: USART 0x4000 4C00 - 0x4000 4FFF 1 KB UART4 register map...
Page 80: Table 2. Stm32L496Xx/4A6Xx Devices Memory Map And Peripheral Register Boundary
RM0351 Table 2. STM32L496xx/4A6xx devices memory map and peripheral register boundary addresses Size Boundary address Peripheral Peripheral register map (bytes) Section 17.6.14: QUADSPI register AHB4 0xA000 1000 - 0xA000 13FF 1 KB QUADSPI 0xA000 0400 - 0xA000 0FFF 3 KB Reserved AHB3 0xA000 0000 - 0xA000 03FF...
Page 81 RM0351 Table 2. STM32L496xx/4A6xx devices memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4002 B000 - 0x4002 BBFF 3 KB DMA2D Section 12.5.24: DMA2D register map 0x4002 4400 - 0x4002 AFFF 26 KB Reserved 0x4002 4000 - 0x4002 43FF 1 KB...
Page 82 RM0351 Table 2. STM32L496xx/4A6xx devices memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4001 0200 - 0x4001 03FF COMP Section 22.6.3: COMP register map Section 21.3.3: VREFBUF register APB2 0x4001 0030 - 0x4001 01FF 1 KB VREFBUF 0x4001 0000 - 0x4001 002F...
Page 83: Bit Banding
RM0351 Table 2. STM32L496xx/4A6xx devices memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 40.8.12: USART register map 0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 40.8.12: USART register map 0x4000 4000 - 0x4000 43FF...
Page 84: Embedded Sram
RM0351 A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit –...
Page 85: Sram2 Write Protection
RM0351 The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms. The parity bits are computed and stored when writing into the SRAM2. Then, they are automatically checked when reading.
Page 86 RM0351 Table 3. SRAM2 organization (continued) Page number Start address End address Page 23 0x1000 5C00 0x1000 5FFF Page 24 0x1000 6000 0x1000 63FF Page 25 0x1000 6400 0x1000 67FF Page 26 0x1000 6800 0x1000 6BFF Page 27 0x1000 6C00 0x1000 6FFF Page 28 0x1000 7000...
Page 87: Sram2 Read Protection
RM0351 Table 3. SRAM2 organization (continued) Page number Start address End address Page 57 0x1000 E400 0x1000 E7FF Page 58 0x1000 E800 0x1000 EBFF Page 59 0x1000 EC00 0x1000 EFFF Page 60 0x1000 F000 0x1000 F3FF Page 61 0x1000 F400 0x1000 F7FF Page 62 0x1000 F800...
Page 88: Boot Configuration
RM0351 Boot configuration 2.6.1 Boot configuration for STM32L475xx/476xx/486xx devices In the STM32L475xx/476xx/486xx devices, three different boot modes can be selected through the BOOT0 pin and nBOOT1 bit in the User option byte, as shown in the following table. Table 4. Boot modes Boot mode selection Boot mode Aliasing...
Page 89: Table 5. Memory Mapping Versus Boot Mode/Physical Remap
RM0351 Physical remap Once the boot pins are selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in place of the System bus). This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.
Page 90: Boot Configuration For Stm32L496Xx/4A6Xx Devices
RM0351 Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode. 2.6.2 Boot configuration for STM32L496xx/4A6xx devices In the STM32L496xx/4A6xx devices, three different boot modes can be selected through...
Page 91: Table 7. Memory Mapping Versus Boot Mode/Physical Remap
RM0351 PH3/BOOT0 GPIO is configured in: • Input mode during the complete reset phase if the option bit nSWBOOT0 is set into the FLASH_OPTR register and then switches automatically in analog mode after reset is released (BOOT0 pin). • Input mode from the reset phase to the completion of the option byte loading if the bit nSWBOOT0 is cleared into the FLASH_OPTR register (BOOT0 value coming from the option bit).
Page 92 2. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space. Embedded boot loader The embedded boot loader is located in the system memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode. 92/1830...
Page 93: Embedded Flash Memory (Flash)
RM0351 Embedded Flash memory (FLASH) Embedded Flash memory (FLASH) Introduction The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 94: Table 8. Flash Module - 1 Mb Dual Bank Organization
STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from www.st.com. – 1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The OTP area is available in Bank 1 only.
Page 95: Table 9. Flash Module - 512 Kb Dual Bank Organization
RM0351 Embedded Flash memory (FLASH) Table 8. Flash module - 1 MB dual bank organization (continued) Size Flash area Flash memory addresses Name (bytes) Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K System memory Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K Information block Bank 1...
Page 96: Error Code Correction (Ecc)
Embedded Flash memory (FLASH) RM0351 Table 10. Flash module - 256 KB dual bank organization Size Flash area Flash memory addresses Name (bytes) 0x0800 0000 - 0x0800 07FF Page 0 0x0800 0800 - 0x0800 0FFF Page 1 0x0800 1000 - 0x0800 17FF Page 2 0x0800 1800 - 0x0800 1FFF Page 3...
Page 97: Read Access Latency
RM0351 Embedded Flash memory (FLASH) When ECCC or ECCD is set, ADDR_ECC and BK_ECC are not updated if a new ECC error occurs. FLASH_ECCR is updated only when ECC flags are cleared. Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two errors detection is not supported.
Page 98: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
Embedded Flash memory (FLASH) RM0351 Decreasing the CPU frequency: Modify the CPU clock source by writing the SW bits in the RCC_CFGR register. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Page 99: Figure 5. Sequential 16-Bit Instructions Execution
RM0351 Embedded Flash memory (FLASH) Figure 5. Sequential 16-bit instructions execution When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states.
Page 100: Flash Program And Erase Operations
Embedded Flash memory (FLASH) RM0351 If a loop is present in the current buffer, no new flash access is performed. Instruction cache memory (I-Cache) To limit the time lost due to jumps, it is possible to retain 32 lines of 4*64 bits in an instruction cache memory.This feature can be enabled by setting the instruction cache enable (ICEN) bit in the Flash access control register...
Page 101: Flash Main Memory Erase Sequences
RM0351 Embedded Flash memory (FLASH) write (RWW)). On the contrary, during a program/erase operation to the Flash memory, any attempt to read the same Flash memory bank will stall the bus. The read operation will proceed correctly once the program/erase operation has completed. Unlocking the Flash memory After reset, write is not allowed in the Flash control register (FLASH_CR)
Page 102: Flash Main Memory Programming Sequences
Embedded Flash memory (FLASH) RM0351 Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. Set the MER1 bit or/and MER2 (depending on the bank) in the Flash control register (FLASH_CR).
Page 103 RM0351 Embedded Flash memory (FLASH) automatically when PG bit is set, and disabled automatically when PG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the user needs to program only one word, double word must be completed with the erase value 0xFFFF FFFF to launch automatically the programming.
Page 104 Embedded Flash memory (FLASH) RM0351 Programming errors Several kind of errors can be detected. In case of error, the Flash operation (programming or erasing) is aborted. • PROGERR: Programming Error In standard programming: PROGERR is set if the word to write is not previously erased (except if the value to program is full zero).
Page 105: Read-While-Write (Rww)
RM0351 Embedded Flash memory (FLASH) In fast programming: FASTERR is set if one of the following conditions occurs: – When FSTPG bit is set for more than 7ms which generates a time-out detection. – When the row fast programming has been interrupted by a MISSERR, PGAERR, WRPERR or SIZERR.
Page 106 Embedded Flash memory (FLASH) RM0351 Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR) (BSY is active when erase/program operation is on going in bank 1 or bank 2). Set MER1 or MER2 to in the Flash control register (FLASH_CR).
Page 107: Flash Option Bytes
RM0351 Embedded Flash memory (FLASH) FLASH option bytes 3.4.1 Option bytes description The option bytes are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode (refer to Section 3.4.2: Option bytes programming).
Page 108 WRP2B WRP2B 1FFFF820 Unused Unused Unused Unused _END _STRT _END _STRT User and read protection option bytes Flash memory address: 0x1FFF 7800 ST production value: 0xFFEF F8AA SRAM2 SRAM2 DUAL WWDG IWGD_ IWDG_ IWDG_ Res. Res. Res. Res. Res. BFB2...
Page 109 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active Bank 1 PCROP Start address option bytes Flash memory address: 0x1FFF 7808 ST production value: 0xFFFF FFFF DocID024597 Rev 5 109/1830...
Page 110 Bits 15:0 PCROP1_STRT: Bank 1 PCROP area start offset PCROP1_STRT contains the first double-word of the bank 1 PCROP area. Bank 1 PCROP End address option bytes Flash memory address: 0x1FFF 7810 ST production value: 0x0000 0000 PCROP Res. Res.
Page 111 Bits 7:0 WRP1A_STRT: Bank 1 WRP first area “A” start offset WRPA1_STRT contains the first page of the Bank 1 WRP first area. Bank 1 WRP Area B address option bytes Flash memory address: 0x1FFF 7820 ST production value: 0x0000 00FF Res. Res. Res.
Page 112 Bits 15:0 PCROP2_END: Bank 2 PCROP area end offset PCROP2_END contains the last double-word of the bank 2 PCROP area. Bank 2 WRP Area A address option bytes Flash memory address: 0x1FFF F818 ST production value: 0x0000 00FF Res. Res. Res.
Page 113: Option Bytes Programming
RM0351 Embedded Flash memory (FLASH) Bits 23:16 WRP2B_END: Bank 2 WRP first area “B” end offset WRP2B_END contains the last page of the Bank 2 WRP second area. Bits 15:8 Not used Bits 7:0 WRP2B_STRT: Bank 2 WRP first area “B” start offset WRP2B_STRT contains the first page of the Bank 2 WRP second area.
Page 114 Embedded Flash memory (FLASH) RM0351 Option byte loading After the BSY bit is cleared, all new options are updated into the flash but they are not applied to the system. They will have effect on the system when they are loaded. Option bytes loading (OBL) is performed in two cases: –...
Page 115: Flash Memory Protection
RM0351 Embedded Flash memory (FLASH) FLASH memory protection The Flash main memory can be protected against external accesses with the Read protection (RDP). The pages of the Flash memory can also be protected against unwanted write due to loss of program counter contexts. The write-protection (WRP) granularity is one page (2 KByte).
Page 116 Embedded Flash memory (FLASH) RM0351 Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct.
Page 117: Table 15. Access Status Versus Protection Level And Execution Modes
RM0351 Embedded Flash memory (FLASH) Note: Full Mass Erase or Partial Mass Erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase. To validate the protection level change, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash control register.
Page 118: Proprietary Code Readout Protection (Pcrop)
Embedded Flash memory (FLASH) RM0351 Table 15. Access status versus protection level and execution modes (continued) Debug/ BootFromRam/ User execution (BootFromFlash) Protection BootFromLoader Area level Read Write Erase Read Write Erase Backup registers SRAM2 1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled. 2.
Page 119: Write Protection (Wrp)
RM0351 Embedded Flash memory (FLASH) For example, to protect by PCROP from the address 0x0806 2F80 (included) to the address 0x0807 0004 (included): • if boot in flash is done in Bank 1, FLASH_PCROP1SR and FLASH_PCROP1ER registers must be programmed with: –...
Page 120: Flash Interrupts
Embedded Flash memory (FLASH) RM0351 For example, to protect by WRP from the address 0x0806 2800 (included) to the address 0x0807 07FF (included): • if boot in flash is done in Bank 1, FLASH_WRP1AR register must be programmed with: – WRP1A_STRT = 0xC5.
Page 121: Flash Registers
RM0351 Embedded Flash memory (FLASH) FLASH registers 3.7.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0600 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 122: Flash Power-Down Key Register (Flash_Pdkeyr)
Embedded Flash memory (FLASH) RM0351 Bit 9 ICEN: Instruction cache enable 0: Instruction cache is disabled 1: Instruction cache is enabled Bit 8 PRFTEN: Prefetch enable 0: Prefetch disabled 1: Prefetch enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LATENCY[2:0]: Latency These bits represent the number of HCLK (AHB clock) period to the Flash access time.
Page 123: Flash Key Register (Flash_Keyr)
RM0351 Embedded Flash memory (FLASH) 3.7.3 Flash key register (FLASH_KEYR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word access KEYR[31:16] KEYR[15:0] Bits 31:0 KEYR: Flash key The following values must be written consecutively to unlock the FLACH_CR register allowing flash programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB...
Page 124: Flash Status Register (Flash_Sr)
Embedded Flash memory (FLASH) RM0351 3.7.5 Flash status register (FLASH_SR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 125: Flash Control Register (Flash_Cr)
RM0351 Embedded Flash memory (FLASH) Bit 6 SIZERR: Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1.
Page 126 Embedded Flash memory (FLASH) RM0351 Bit 31 LOCK: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
Page 127: Flash Ecc Register (Flash_Eccr)
RM0351 Embedded Flash memory (FLASH) Bit 15 MER2: Bank 2 Mass erase This bit triggers the bank 2 mass erase (all bank 2 user pages) when set. Bits 14:12 Reserved, must be kept at reset value. Bit 11 BKER: Page number MSB (Bank selection) 0: Bank 1 is selected for page erase 1: Bank 2 is selected for page erase Bits 10:3 PNB[7:0]: Page number selection...
Page 128: Flash Option Register (Flash_Optr)
Embedded Flash memory (FLASH) RM0351 Bit 31 ECCD: ECC detection Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated Cleared by writing 1. Bit 30 ECCC: ECC correction Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set.
Page 129 RM0351 Embedded Flash memory (FLASH) Bits 31:28 Reserved, must be kept at reset value. Bit 27 nBOOT0: nBOOT0 option bit (This bit is reserved for STM32L475xx/476xx/486xx devices) 0: nBOOT0 = 0 1: nBOOT0 = 1 Bit 26 nSWBOOT0: Software BOOT0 (This bit is reserved for STM32L475xx/476xx/486xx devices) 0: BOOT0 taken from the option bit nBOOT0 1: BOOT0 taken from PH3/BOOT0 pin...
Page 130: Flash Bank 1 Pcrop Start Address Register (Flash_Pcrop1Sr)
Embedded Flash memory (FLASH) RM0351 Bit 12 nRST_STOP 0: Reset generated when entering the Stop mode 1: No reset generated when entering the Stop mode Bit 11 Reserved, must be kept cleared Bits10:8 BOR_LEV: BOR reset Level These bits contain the VDD supply level threshold that activates/releases the reset.
Page 131: Flash Bank 1 Pcrop End Address Register (Flash_Pcrop1Er)
RM0351 Embedded Flash memory (FLASH) 3.7.10 Flash Bank 1 PCROP End address register (FLASH_PCROP1ER) Address offset: 0x28 Reset value: 0xX000 XXXX. Register bits are loaded with values from Flash memory at OBL. Access: no wait state when no Flash memory operation is on going, word, half-word access. PCROP_RDP bit can be accessed with byte access.
Page 132: Flash Bank 1 Wrp Area B Address Register (Flash_Wrp1Br)
Embedded Flash memory (FLASH) RM0351 Bits 23:16 WRP1A_END: Bank 1 WRP first area “A” end offset WRP1A_END contains the last page of the Bank 1 WRP first area. Bits 15:8 Reserved, must be kept cleared Bits 7:0 WRP1A_STRT: Bank 1 WRP first area “A” start offset WRP1A_STRT contains the first page of the Bank 1 WRP first area.
Page 133: Flash Bank 2 Pcrop End Address Register (Flash_Pcrop2Er)
RM0351 Embedded Flash memory (FLASH) 3.7.14 Flash Bank 2 PCROP End address register (FLASH_PCROP2ER) Address offset: 0x48 Reset value: 0x0000 XXXX Access: no wait state when no Flash memory operation is on going, word, half-word access Res. Res. Res. Res. Res.
Page 134: Flash Bank 2 Wrp Area B Address Register (Flash_Wrp2Br)
Embedded Flash memory (FLASH) RM0351 3.7.16 Flash Bank 2 WRP area B address register (FLASH_WRP2BR) Address offset: 0x50 Reset value: 0x00XX 00XX Access: no wait state when no Flash memory operation is on going, word, half-word and byte access Res. Res.
Page 135: Flash Register Map
RM0351 Embedded Flash memory (FLASH) 3.7.17 FLASH register map Table 17. Flash interface - register map and reset values Offset Register LATENCY FLASH_ACR [2:0] 0x00 Reset value FLASH_ PDKEYR[31:0] PDKEYR 0x04 Reset value FLASH_KEYR KEYR[31:0] 0x08 Reset value FLASH_OPT OPTKEYR[31:0] KEYR 0x0C Reset value...
Page 136 Embedded Flash memory (FLASH) RM0351 Table 17. Flash interface - register map and reset values (continued) Offset Register FLASH_ WRP1B_END[7:0] WRP1B_STRT[7:0] WRP1BR 0x30 Reset value X X X X X X X X X X X X X X X X FLASH_ PCROP2_STRT[15:0] PCROP2SR...
Page 137: Firewall (Fw)
RM0351 Firewall (FW) Firewall (FW) Introduction The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM 1 from the rest of the code executed outside the protected area.
Page 138: Firewall Functional Description
Firewall (FW) RM0351 Firewall functional description 4.3.1 Firewall AMBA bus snoop The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in Figure Figure 7. STM32L4x5/STM32L4x6 firewall connection schematics 4.3.2 Functional requirements There are several requirements to guaranty the highest security level by the application...
Page 139: Firewall Segments
RM0351 Firewall (FW) end code needs to embed an IAP located in a write protected segment in order to allow future code updates when the production parts will be Level 2 ROP. Write protection In order to offer a maximum security level, the following points need to be respected: •...
Page 140: Segment Accesses And Properties
Firewall (FW) RM0351 Volatile data segment Volatile data used by the protected code located into the code segment must be defined into the SRAM 1 memory. The access to this segment is defined into the Section 4.3.4: Segment accesses and properties.
Page 141: Firewall Initialization
RM0351 Firewall (FW) The Volatile data segment is a bit different from the two others. The segment can be: • Shared (VDS bit in the register) It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area.
Page 142: Firewall States
Firewall (FW) RM0351 Below is the initialization procedure to follow: Configure the RCC to enable the clock to the Firewall module Configure the RCC to enable the clock of the system configuration registers Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL, VDSSA, VDSL registers) Set the configuration register of the Firewall (FW_CR register) Enable the Firewall clearing the FWDIS bit in the system configuration register.
Page 143 RM0351 Firewall (FW) Opening the Firewall As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to Section 4.3.4: Segment accesses and properties). In order to open the Firewall to interact with the protected segments, it is mandatory to apply the “call gate”...
Page 144: Firewall Registers
Firewall (FW) RM0351 Firewall registers 4.4.1 Code segment start address (FW_CSSA) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 Reserved, must be kept at reset value. Bits 23:8 ADD[23:8]: code segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 145: Non-Volatile Data Segment Start Address (Fw_Nvdssa)
RM0351 Firewall (FW) 4.4.3 Non-volatile data segment start address (FW_NVDSSA) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 Reserved, must be kept at the reset value. Bits 23:8 ADD[23:8]: Non-volatile data segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 146: Volatile Data Segment Start Address (Fw_Vdssa)
Firewall (FW) RM0351 4.4.5 Volatile data segment start address (FW_VDSSA) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. [17:16] ADD[15:6] Res. Res. Res. Res. Res. Res. Bits 31:18 Reserved, must be kept at the reset value. Bit 17 ADD[17]: Volatile data segment start address (only for STM32L496xx/4A6xx devices) Bits 16:6 ADD[16:6]: Volatile data segment start address The LSB bits of the start address (bit 5:0) are reserved and forced to 0 in order to allow a...
Page 147: Configuration Register (Fw_Cr)
RM0351 Firewall (FW) Bits 31:18 Reserved, must be kept at the reset value. Bit 17 LENG[17]: volatile data segment length (only for STM32L496xx/4A6xx devices) Bits 16:6 LENG[16:6]: volatile data segment length LENG[16:6] selects the size of the volatile data segment expressed in bytes but is a multiple of 64 bytes.
Page 148 Firewall (FW) RM0351 Bit 2 VDE: Volatile data execution 0: Volatile data segment cannot be executed if VDS = 0 1: Volatile data segment is declared executable whatever VDS bit value When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever the VDE bit value.
Page 149: Firewall Register Map
RM0351 Firewall (FW) 4.4.8 Firewall register map The table below provides the Firewall register map and reset values. Table 20. Firewall register map and reset values Offset Register FW_CSSA Reset Value FW_CSL LENG Reset Value FW_NVDSSA Reset Value FW_NVDSL LENG Reset Value FW_VDSSA 0x10...
Page 150: Power Control (Pwr)
Power control (PWR) RM0351 Power control (PWR) Power supplies The STM32L4x5/STM32L4x6 devices require a 1.71 V to 3.6 V operating supply voltage ). Several peripherals are supplied through independent power domains: V . Those supplies must not be provided without a valid operating DDIO2 DDUSB supply on the V...
Page 151: Independent Analog Peripherals Supply
RM0351 Power control (PWR) – around 2.5 V. This requires V equal to or higher than 2.8 V. REF+ VREF- and VREF+ pins are not available on all packages. When not available on the package, they are bonded to VSSA and VDDA, respectively. When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disable (refer to related device datasheet for packages pinout description).
Page 152: Independent I/O Supply Rail
Power control (PWR) RM0351 The V supply voltage can be different from V . The presence of V must be checked before enabling any of the analog peripherals supplied by V (A/D converter, D/A converter, comparators, operational amplifiers, voltage reference buffer). The V supply can be monitored by the Peripheral Voltage Monitoring, and compared with two thresholds (1.65 V for PVM3 or 2.2 V for PVM4), refer to...
Page 153: Independent Lcd Supply
RM0351 Power control (PWR) 5.1.4 Independent LCD supply The VLCD pin is provided to control the contrast of the glass LCD. This pin can be used in two ways: • It can receive from an external circuitry the desired maximum voltage that is provided on segment and common lines to the glass LCD by the microcontroller.
Page 154: Voltage Regulator
Power control (PWR) RM0351 Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g.
Page 155: Vdd12 Domain
RM0351 Power control (PWR) contents of the registers, SRAM1 and SRAM2. • In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator (LPR) supplies low power to the V domain, preserving the contents of the CORE registers, SRAM1 and SRAM2.
Page 156: Dynamic Voltage Scaling Management
Power control (PWR) RM0351 Proper software management through GPIOs to enable/disable SMPS and connect/disconnect SMPS through the switch, is required to conform with the rules described below. (See also Section 5.1.8: Dynamic voltage scaling management) It is mandatory to respect the following rules to avoid any damage or instability on either digital parts or internal regulators: •...
Page 157 RM0351 Power control (PWR) The sequence to go from Range 1 to Range 2 is: 1. Reduce the system frequency to a value lower than 26 MHz 2. Adjust number of wait states according new frequency target in Range 2 (LATENCY bits in the FLASH_ACR).
Page 158: Power Supply Supervisor
Power control (PWR) RM0351 If in Range 1, then the following step can be applied: 5. Increase the system frequency if needed. Power supply supervisor 5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry.
Page 159: Peripheral Voltage Monitoring (Pvm)
RM0351 Power control (PWR) Figure 12. PVD thresholds 5.2.3 Peripheral Voltage Monitoring (PVM) Only V is monitored by default, as it is the only supply required for all system-related functions. The other supplies (V and V ) can be independent from V DDIO2 DDUSB and can be monitored with four Peripheral Voltage Monitoring (PVM).
Page 160: Low-Power Modes
Power control (PWR) RM0351 can be enabled to confirm whether the supply is present or not. The following sequence must be done before using the USB OTG peripheral: If V is independent from V DDUSB Enable the PVM1 by setting PVME1 bit in the Power control register 2 (PWR_CR2).
Page 161 RM0351 Power control (PWR) regulator is in low-power mode to minimize the regulator's operating current. Refer to Section 5.3.2: Low-power run mode (LP run). ® • Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex M4 is off. Refer to Section 5.3.5: Low-power sleep mode (LP sleep).
Page 162: Figure 13. Low-Power Modes Possible Transitions
Power control (PWR) RM0351 Figure 13. Low-power modes possible transitions 162/1830 DocID024597 Rev 5...
Page 163: Table 22. Low-Power Mode Summary
RM0351 Power control (PWR) Table 22. Low-power mode summary Voltage Wakeup Wakeup regulators Mode name Entry Effect on clocks source system clock WFI or Return Sleep CPU clock OFF Same as before Any interrupt from ISR entering Sleep (Sleep-now or no effect on other clocks mode Sleep-on-exit)
Page 164: Table 23. Functionalities Depending On The Working Mode
Power control (PWR) RM0351 Table 23. Functionalities depending on the working mode Stop 0/1 Stop 2 Standby Shutdown Peripheral Sleep VBAT Flash memory (up to 1 MB) SRAM1 (up to 256 KB) SRAM2 (up to 64 KB) FSMC QUADSPI Backup Registers Brown-out reset (BOR) Programmable Voltage Detector (PVD)
Page 165 RM0351 Power control (PWR) Table 23. Functionalities depending on the working mode (continued) Stop 0/1 Stop 2 Standby Shutdown Peripheral Sleep VBAT USB OTG FS USARTx (x=1,2,3,4,5) Low-power UART (LPUART1) I2Cx (x=1,2,4) I2C3 SPIx (x=1,2,3) CANx (x=1,2) SDMMC1 SWPMI1 SAIx (x=1,2) DFSDM1 ADCx (x=1,2,3) DACx (x=1,2)
Page 166: Run Mode
Power control (PWR) RM0351 Table 23. Functionalities depending on the working mode (continued) Stop 0/1 Stop 2 Standby Shutdown Peripheral Sleep VBAT AES hardware accelerator HASH hardware accelerator CRC calculation unit (11) GPIOs pins pins (10) (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2.
Page 167: Low-Power Run Mode (Lp Run)
RM0351 Power control (PWR) Peripheral clock gating In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption. To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Page 168: Low Power Modes
Power control (PWR) RM0351 Table 24. Low-power run Low-power run mode Description LPR = 0 Mode exit Wait until REGLPF = 0 Increase the system clock frequency Wakeup latency Regulator wakeup time from low-power mode 5.3.3 Low power modes Entering low power mode Low power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or ®...
Page 169: Sleep Mode
RM0351 Power control (PWR) or a RTC event occurs (see Figure 374: RTC block diagrams). After waking up from Standby or Shutdown mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.). 5.3.4 Sleep mode I/O states in Sleep mode...
Page 170: Stop 0 Mode
Power control (PWR) RM0351 I/O states in Low-power sleep mode In Low-power sleep mode, all I/O pins keep the same state as in Run mode. Entering the Low-power sleep mode The Low-power sleep mode is entered from low-power run mode according Section : ®...
Page 171 RM0351 Power control (PWR) HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3), U(S)ARTx(x=1,2...5) and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it.
Page 172: Stop 1 Mode
Power control (PWR) RM0351 (RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The MSI selection allows wakeup at higher frequency, up to 48 MHz. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop 0 mode with HSI16.
Page 173: Stop 2 Mode
RM0351 Power control (PWR) Refer to Table 28: Stop 1 mode for details on how to enter and exit Stop 1 mode. Table 28. Stop 1 mode Stop 1 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ®...
Page 174 Power control (PWR) RM0351 I/O states in Stop 2 mode In the Stop 2 mode, all I/O pins keep the same state as in the Run mode. Entering Stop 2 mode The Stop 2 mode is entered according Section : Entering low power mode, when the ®...
Page 175: Standby Mode
RM0351 Power control (PWR) When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared.
Page 176 Power control (PWR) RM0351 SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 9). SRAM2 content can be preserved if the bit RRS is set in the PWR_CR3 register. In this case the Low-power regulator is ON and provides the supply to SRAM2 only.
Page 177: Table 30. Standby Mode
RM0351 Power control (PWR) Table 30. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 178: Shutdown Mode
Power control (PWR) RM0351 5.3.10 Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The V domain is consequently CORE powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
Page 179: Auto-Wakeup From Low-Power Mode
RM0351 Power control (PWR) Table 31. Shutdown mode Shutdown mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 180: Pwr Registers
Power control (PWR) RM0351 PWR registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 5.4.1 Power control register 1 (PWR_CR1) Address offset: 0x00 Reset value: 0x0000 0200. This register is reset after wakeup from Standby mode. Res.
Page 181: Power Control Register 2 (Pwr_Cr2)
RM0351 Power control (PWR) 5.4.2 Power control register 2 (PWR_CR2) Address offset: 0x04 Reset value: 0x0000 0000. This register is reset when exiting the Standby mode. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 182: Power Control Register 3 (Pwr_Cr3)
Power control (PWR) RM0351 Bit 4 PVME1: Peripheral voltage monitoring 1 enable: vs. 1.2V DDUSB 0: PVM1 ( monitoring vs. 1.2V threshold) disable. DDUSB 1: PVM1 ( monitoring vs. 1.2V threshold) enable. DDUSB Bits 3:1 PLS[2:0]: Power voltage detector level selection. These bits select the voltage threshold detected by the power voltage detector: 000: V around 2.0 V...
Page 183: Power Control Register 4 (Pwr_Cr4)
RM0351 Power control (PWR) Bit 10 APC: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os.
Page 184: Power Status Register 1 (Pwr_Sr1)
Power control (PWR) RM0351 Bits 31:10 Reserved, must be kept at reset value. Bit 9 VBRS: V battery charging resistor selection 0: Charge V through a 5 kOhms resistor 1: Charge V through a 1.5 kOhms resistor Bit 8 VBE: V battery charging enable 0: V battery charging disable...
Page 185: Power Status Register 2 (Pwr_Sr2)
RM0351 Power control (PWR) Bits 31:16 Reserved, must be kept at reset value. Bit 15 WUFI: Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. Bits 14:9 Reserved, must be kept at reset value.
Page 186: Power Status Clear Register (Pwr_Scr)
Power control (PWR) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bit 15 PVMO4: Peripheral voltage monitoring output: V vs. 2.2 V 0: V voltage is above PVM4 threshold (around 2.2 V). 1: V voltage is below PVM4 threshold (around 2.2 V). Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0).
Page 187: Power Port A Pull-Up Control Register (Pwr_Pucra)
RM0351 Power control (PWR) Reset value: 0x0000 0000. Access: 3 additional APB cycles are needed to write this register vs. a standard APB write. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CWUF CWUF CWUF...
Page 188: Power Port A Pull-Down Control Register (Pwr_Pdcra)
Power control (PWR) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bit 15 PU15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set. Bit 14 Reserved, must be kept at reset value.
Page 189: Power Port B Pull-Down Control Register (Pwr_Pdcrb)
RM0351 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
Page 190: Power Port C Pull-Down Control Register (Pwr_Pdcrc)
Power control (PWR) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register.
Page 191: Power Port D Pull-Down Control Register (Pwr_Pdcrd)
RM0351 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register.
Page 192: Power Port E Pull-Down Control Register (Pwr_Pdcre)
Power control (PWR) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register.
Page 193: Power Port F Pull-Down Control Register (Pwr_Pdcrf)
RM0351 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register.
Page 194: Power Port G Pull-Down Control Register (Pwr_Pdcrg)
Power control (PWR) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register.
Page 195: Power Port H Pull-Down Control Register (Pwr_Pdcrh)
RM0351 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register.
Page 196: Power Port I Pull-Down Control Register (Pwr_Pdcri)
Power control (PWR) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 11:0 PUy: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register.
Page 197: Pwr Register Map And Reset Value Table
RM0351 Power control (PWR) 5.4.26 PWR register map and reset value table Table 32. PWR register map and reset values Offset Register LPMS PWR_CR1 [1:0] [2:0] 0x000 Reset value PWR_CR2 PLS [2:0] 0x004 Reset value PWR_CR3 0x008 Reset value PWR_CR4 0x00C Reset value PWR_SR1...
Page 198 Power control (PWR) RM0351 Table 32. PWR register map and reset values (continued) Offset Register PWR_PDCRE 0x044 Reset value PWR_PUCRF 0x048 Reset value PWR_PDCRF 0x04C Reset value PWR_PUCRG 0x050 Reset value PWR_PDCRG 0x054 Reset value PWR_PUCRH 0x058 Reset value PWR_PDCRH 0x05C Reset value PWR_PUCRI...
Page 199: Reset And Clock Control (Rcc)
RM0351 Reset and clock control (RCC) Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and backup domain reset. 6.1.1 Power reset A power reset is generated when one of the following events occurs: a Brown-out reset (BOR).
Page 200: Figure 14. Simplified Diagram Of The Reset Circuit
Reset and clock control (RCC) RM0351 Figure 14. Simplified diagram of the reset circuit Software reset ® The SYSRESETREQ bit in Cortex -M4 Application Interrupt and Reset Control Register must be set to force a software reset on the device (refer to the STM32F3xx/F4xx/L4xx ®...
Page 201 RM0351 Reset and clock control (RCC) Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). or V power on, if both supplies have previously been powered off. A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register.
Page 202 Reset and clock control (RCC) RM0351 All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except: • The 48 MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived (selected by software) from one of the four following sources: –...
Page 203 RM0351 Reset and clock control (RCC) – LSI clock – LSE clock – HSI16 clock – APB1 clock (PCLK1) – External clock mapped on LPTIMx_IN1 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE, or in external clock mode. •...
Page 204: Figure 15. Clock Tree (For Stm32L475Xx/476Xx/486Xx Devices)
Reset and clock control (RCC) RM0351 Figure 15. Clock tree (for STM32L475xx/476xx/486xx devices) 204/1830 DocID024597 Rev 5...
Page 205 RM0351 Reset and clock control (RCC) 1. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4).
Page 206: Figure 16. Clock Tree (For Stm32L496Xx/4A6Xx Devices)
Reset and clock control (RCC) RM0351 Figure 16. Clock tree (for STM32L496xx/4A6xx devices) 206/1830 DocID024597 Rev 5...
Page 207: Figure 17. Hse/ Lse Clock Sources
RM0351 Reset and clock control (RCC) 6.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
Page 208 Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 209 The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the...
Page 210 Reset and clock control (RCC) RM0351 can use the USB SOF signal, the LSE or an external signal to automatically and quickly adjust the oscillator frequency on-fly. It is disabled as soon as the system enters Stop or Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default frequency which is subject to manufacturing process variations.
Page 211 RM0351 Reset and clock control (RCC) The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN, PLLSAI1QEN, PLLSAI1REN, PLLSAI2PEN and PLLSAI2REN) can be modified at any time without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is used as system clock.
Page 212: Table 33. Clock Source Frequency
Reset and clock control (RCC) RM0351 The system clock maximum frequency is 80 MHz. After a system reset, the MSI oscillator, at 4 MHz, is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it.
Page 213 RM0351 Reset and clock control (RCC) 6.2.11 Clock security system on LSE A Clock Security System on LSE can be activated by software writing the LSECSSON bit in Control/status register (RCC_CSR). This bit can be disabled only by a hardware reset or RTC software reset, or after a failure detection on LSE.
Page 214 Reset and clock control (RCC) RM0351 The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – The RTC continues to work even if the V supply is switched off, provided the supply is maintained.
Page 215: Figure 18. Frequency Measurement With Tim15 In Capture Mode
RM0351 Reset and clock control (RCC) configuration register (RCC_CFGR). • LSCO Another output (LSCO) allows a low speed clock to be output onto the external LSCO pin: – – This output remains available in Stop (Stop 0, Stop 1 and Stop 2) and Standby modes. The selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the Backup domain control register (RCC_BDCR).
Page 216: Figure 19. Frequency Measurement With Tim16 In Capture Mode
Reset and clock control (RCC) RM0351 Figure 19. Frequency measurement with TIM16 in capture mode The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM16_OR register. The possibilities are the following ones: •...
Page 217 RM0351 Reset and clock control (RCC) Calibration of the HSI16 and the MSI For TIM15 and TIM16, the primary purpose of connecting the LSE to the channel 1 input capture is to be able to precisely measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI should be used as the system clock source).
Page 218 Reset and clock control (RCC) RM0351 Low-power modes • AHB and APB peripheral clocks, including DMA clock, can be disabled by software. • Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks (Flash and SRAM1 and SRAM2 interfaces) can be stopped by software during sleep mode.
Page 219 RM0351 Reset and clock control (RCC) RCC registers 6.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 0063. HSEBYP is not affected by reset. Access: no wait state, word, half-word and byte access Res. Res. SAI2 SAI2 SAI1 SAI1 PLLON Res.
Page 220 Reset and clock control (RCC) RM0351 Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected.
Page 221 RM0351 Reset and clock control (RCC) Bit 8 HSION: HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.
Page 222 Reset and clock control (RCC) RM0351 Bit 0 MSION: MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock.
Page 223 RM0351 Reset and clock control (RCC) 6.4.3 Clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers values update is on going.
Page 224 Reset and clock control (RCC) RM0351 STOPWUCK: Wakeup from Stop and CSS backup clock selection Bit 15 Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=”10”) or a switch on HSE is requested (SW=”10”).
Page 225 RM0351 Reset and clock control (RCC) Bits 1:0 SW[1:0]: System clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by HW to force MSI oscillator selection when exiting Standby or Shutdown mode. Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in case of failure of the HSE oscillator, depending on STOPWUCK value.
Page 226 Reset and clock control (RCC) RM0351 Bits 26:25 PLLR[1:0]: Main PLL division factor for PLLCLK (system clock) Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled.
Page 227 RM0351 Reset and clock control (RCC) Bit 16 PLLPEN: Main PLL PLLSAI3CLK output enable Set and reset by software to enable the PLLSAI3CLK output of the main PLL. In order to save power, when the PLLSAI3CLK output of the PLL is not used, the value of PLLPEN should be 0.
Page 228 Reset and clock control (RCC) RM0351 Bits 1:0 PLLSRC: Main PLL, PLLSAI1 and PLLSAI2 entry clock source Set and cleared by software to select PLL, PLLSAI1 and PLLSAI2 clock source. These bits can be written only when PLL, PLLSAI1 and PLLSAI2 are disabled. In order to save power, when no PLL is used, the value of PLLSRC should be 00.
Page 229 RM0351 Reset and clock control (RCC) Bits 31:27 PLLSAI1PDIV[4:0]: PLLSAI1 division factor for PLLSAI1CLK (only on STM32L496xx/4A6xx devices) Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI1CLK output clock frequency = VCOSAI1 frequency / PLLPDIV. 00000: PLLSAI1CLK is controlled by the bit PLLP 00001: Reserved.
Page 230 Reset and clock control (RCC) RM0351 Bit 17 PLLSAI1P: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock). Set and cleared by software to control the frequency of the SAI1PLL output clock PLLSAI1CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if SAI1PLL is disabled.
Page 231 RM0351 Reset and clock control (RCC) 6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR) Address offset: 0x14 Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLLSAI2 clock outputs according to the formulas: •...
Page 232 Reset and clock control (RCC) RM0351 Bit 17 PLLSAI2P: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock). Set and cleared by software to control the frequency of the SAI2PLL output clock PLLSAI2CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if SAI2PLL is disabled.
Page 233 RM0351 Reset and clock control (RCC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSI48 Res. Res. Res. Res. Res. Res. SAI2 SAI1 RDYIE CSSIE RDYIE RDYIE RDYIE RDYIE RDYIE RDYIE RDYIE RDYIE Bits 31:11 Reserved, must be kept at reset value.
Page 234 Reset and clock control (RCC) RM0351 Bit 2 MSIRDYIE: MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
Page 235 RM0351 Reset and clock control (RCC) Bit 7 PLLSAI2RDYF: PLLSAI2 ready interrupt flag Set by hardware when the PLLSAI2 locks and PLLSAI2RDYDIE is set. Cleared by software setting the PLLSAI2RDYC bit. 0: No clock ready interrupt caused by PLLSAI2 lock 1: Clock ready interrupt caused by PLLSAI2 lock Bit 6 PLLSAI1RDYF: PLLSAI1 ready interrupt flag Set by hardware when the PLLSAI1 locks and PLLSAI1RDYDIE is set.
Page 236 Reset and clock control (RCC) RM0351 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSI48 PLLSAI Res. Res. Res. Res. Res. CSSC SAI1 RDYC CSSC 2RDYC...
Page 237 RM0351 Reset and clock control (RCC) Bit 2 MSIRDYC: MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. 0: No effect 1: MSIRDYF cleared Bit 1 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 0 LSIRDYC: LSI ready interrupt clear...
Page 238 Reset and clock control (RCC) RM0351 Bit 8 FLASHRST: Flash memory interface reset Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. 0: No effect 1: Reset Flash memory interface Bits 7:2 Reserved, must be kept at reset value.
Page 239 RM0351 Reset and clock control (RCC) Bit 14 DCMIRST: Digital Camera Interface reset (This bit is reserved for STM32L475xx/476xx/486xx devices) Set and cleared by software 0: No effect 1: Reset DCMI interface Bit 13 ADCRST: ADC reset Set and cleared by software. 0: No effect 1: Reset ADC interface Bit 12 OTGFSRST: USB OTG FS reset...
Page 240 Reset and clock control (RCC) RM0351 Bit 2 GPIOCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset IO port C Bit 1 GPIOBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset IO port B Bit 0 GPIOARST: IO port A reset Set and cleared by software.
Page 241 RM0351 Reset and clock control (RCC) DAC1 CAN1 I2C2 I2C1 UART5 UART4 USART3 USART2 LPTIM1 OPAMP CAN2R CRSRS I2C3R Res. Res. SPI3 SPI2 TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 Res. Res. Res. Res. Res. Res. Res. Bit 31 LPTIM1RST: Low Power Timer 1 reset Set and cleared by software.
Page 242 Reset and clock control (RCC) RM0351 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 Bit 20 UART5RST: UART5 reset Set and cleared by software. 0: No effect 1: Reset UART5 Bit 19 UART4RST: UART4 reset Set and cleared by software.
Page 243 RM0351 Reset and clock control (RCC) Bit 3 TIM5RST: TIM5 timer reset Set and cleared by software. 0: No effect 1: Reset TIM5 Bit 2 TIM4RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 1 TIM3RST: TIM3 timer reset Set and cleared by software.
Page 244 Reset and clock control (RCC) RM0351 Bit 2 SWPMI1RST: Single wire protocol reset Set and cleared by software. 0: No effect 1: Reset SWPMI1 Bit 1 I2C4RST: I2C4 reset (This bit is reserved for STM32L475xx/476xx/486xx devices) Set and cleared by software 0: No effect 1: Reset I2C4 Bit 0 LPUART1RST: Low-power UART 1 reset...
Page 245 RM0351 Reset and clock control (RCC) Bit 18 TIM17RST: TIM17 timer reset Set and cleared by software. 0: No effect 1: Reset TIM17 timer Bit 17 TIM16RST: TIM16 timer reset Set and cleared by software. 0: No effect 1: Reset TIM16 timer Bit 16 TIM15RST: TIM15 timer reset Set and cleared by software.
Page 246 Reset and clock control (RCC) RM0351 DMA2D Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH DMA2 DMA1 Res. Res. Res. CRCEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:18 Reserved, must be kept at reset value. Bit 17 DMA2DEN: DMA2D clock enable (This bit is reserved for STM32L475xx/476xx/486xx devices) Set and cleared by software 0: DMA2D clock disabled...
Page 247 RM0351 Reset and clock control (RCC) 6.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR) Address offset: 0x4C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 248 Reset and clock control (RCC) RM0351 Bit 8 GPIOIEN: IO port I clock enable (This bit is reserved for STM32L475xx/476xx/486xx devices) Set and cleared by software 0: IO port I clock disabled 1: IO port I clock enabled Bit 7 GPIOHEN: IO port H clock enable Set and cleared by software.
Page 249 RM0351 Reset and clock control (RCC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QSPI Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:9 Reserved, must be kept at reset value. Bit 8 QSPIEN: Quad SPI memory interface clock enable Set and cleared by software.
Page 250 Reset and clock control (RCC) RM0351 Bit 31 LPTIM1EN: Low power timer 1 clock enable Set and cleared by software. 0: LPTIM1 clock disabled 1: LPTIM1 clock enabled Bit 30 OPAMPEN: OPAMP interface clock enable Set and cleared by software. 0: OPAMP interface clock disabled 1: OPAMP interface clock enabled Bit 29 DAC1EN: DAC1 interface clock enable...
Page 251 RM0351 Reset and clock control (RCC) Bit 19 UART4EN: UART4 clock enable Set and cleared by software. 0: UART4 clock disabled 1: UART4 clock enabled Bit 18 USART3EN: USART3 clock enable Set and cleared by software. 0: USART3 clock disabled 1: USART3 clock enabled Bit 17 USART2EN: USART2 clock enable Set and cleared by software.
Page 252 Reset and clock control (RCC) RM0351 Bit 3 TIM5EN: TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled Bit 2 TIM4EN: TIM4 timer clock enable Set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software.
Page 253 RM0351 Reset and clock control (RCC) Bit 2 SWPMI1EN: Single wire protocol clock enable Set and cleared by software. 0: SWPMI1 clock disable 1: SWPMI1 clock enable Bit 1 I2C4EN: I2C4 clock enable (This bit is reserved for STM32L475xx/476xx/486xx devices) Set and cleared by software 0: I2C4 clock disabled 1: I2C4 clock enabled...
Page 254 Reset and clock control (RCC) RM0351 6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x60 Reset value: 0x0000 0000 Access: word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 255 RM0351 Reset and clock control (RCC) Bit 14 USART1EN: USART1clock enable Set and cleared by software. 0: USART1clock disabled 1: USART1clock enabled Bit 13 TIM8EN: TIM8 timer clock enable Set and cleared by software. 0: TIM8 timer clock disabled 1: TIM8 timer clock enabled Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software.
Page 256 Reset and clock control (RCC) RM0351 DMA2D Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMEN SMEN FLASH DMA2 SRAM1 DMA1 Res. Res. Res. CRCSMEN Res. Res. Res. Res. Res. Res. Res. Res. SMEN SMEN SMEN SMEN...
Page 257 RM0351 Reset and clock control (RCC) 6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) Address offset: 0x6C Reset value: 0x0007 73FF (for STM32L496xx/4A6xx devices) 0x0005 32FF (for STM32L475xx/476xx/486xx devices) Access: no wait state, word, half-word and byte access HASHS Res.
Page 258 Reset and clock control (RCC) RM0351 Bit 12 OTGFSSMEN: OTG full speed clocks enable during Sleep and Stop modes Set and cleared by software. 0: USB OTG full speed clocks disabled by the clock gating during Sleep and Stop modes 1: USB OTG full speed clocks enabled by the clock gating during Sleep and Stop modes Bits 11:10 Reserved, must be kept at reset value.
Page 259 RM0351 Reset and clock control (RCC) 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 6.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR)
Page 260 Reset and clock control (RCC) RM0351 Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes 1: LPTIM1 clocks enabled by the clock gating during Sleep and Stop modes Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes Set and cleared by software.
Page 261 RM0351 Reset and clock control (RCC) Bit 20 UART5SMEN: UART5 clocks enable during Sleep and Stop modes Set and cleared by software. 0: UART5 clocks disabled by the clock gating during Sleep and Stop modes 1: UART5 clocks enabled by the clock gating during Sleep and Stop modes Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes Set and cleared by software.
Page 262 Reset and clock control (RCC) RM0351 Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM6 clocks disabled by the clock gating during Sleep and Stop modes 1: TIM6 clocks enabled by the clock gating during Sleep and Stop modes Bit 3 TIM5SMEN: TIM5 timer clocks enable during Sleep and Stop modes Set and cleared by software.
Page 263 RM0351 Reset and clock control (RCC) Bit 2 SWPMI1SMEN: Single wire protocol clocks enable during Sleep and Stop modes Set and cleared by software. 0: SWPMI1 clocks disabled by the clock gating during Sleep and Stop modes 1: SWPMI1 clocks enabled by the clock gating during Sleep and Stop modes Bit 1 I2C4SMEN: I2C4 clocks enable during Sleep and Stop modes (This bit is reserved for STM32L475xx/476xx/486xx devices)
Page 264 Reset and clock control (RCC) RM0351 6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) Address: 0x80 Reset value: 0x0167 7C01 Access: word, half-word and byte access DFSD SAI2 SAI1 TIM17 TIM16 TIM15 Res. Res. Res. Res. Res.
Page 265 RM0351 Reset and clock control (RCC) Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART1clocks disabled by the clock gating during Sleep and Stop modes 1: USART1clocks enabled by the clock gating during Sleep and Stop modes Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software.
Page 266 Reset and clock control (RCC) RM0351 Bit 31 DFSDM1SEL: DFSDM1 clock source selection This bit is set and cleared by software to select the DFSDM1 clock source. 0: APB2 (PCLK2) selected as DFSDM1 clock 1: System clock (SYSCLK) used as DFSDM1 clock Bit 30 SWPMI1SEL: SWPMI1 clock source selection This bit is set and cleared by software to select the SWPMI1 clock source.
Page 267 RM0351 Reset and clock control (RCC) Bits 19:18 LPTIM1SEL[1:0]: Low power timer 1 clock source selection These bits are set and cleared by software to select the LPTIM1 clock source. 00: PCLK selected as LPTIM1 clock 01: LSI clock selected as LPTIM1 clock 10: HSI16 clock selected as LPTIM1 clock 11: LSE clock selected as LPTIM1 clock Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection...
Page 268 Reset and clock control (RCC) RM0351 Bits 5:4 USART3SEL[1:0]: USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 00: PCLK selected as USART3 clock 01: System clock (SYSCLK) selected as USART3 clock 10: HSI16 clock selected as USART3 clock 11: LSE clock selected as USART3 clock Bits 3:2 USART2SEL[1:0]: USART2 clock source selection...
Page 269 RM0351 Reset and clock control (RCC) Bits 31:26 Reserved, must be kept at reset value. Bit 25 LSCOSEL: Low speed clock output selection Set and cleared by software. 0: LSI clock selected 1: LSE clock selected Bit 24 LSCOEN: Low speed clock output enable Set and cleared by software.
Page 270 Reset and clock control (RCC) RM0351 Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability Set by software to modulate the LSE oscillator’s drive capability. 00: ‘Xtal mode’ lower driving capability 01: ‘Xtal mode’ medium low driving capability 10: ‘Xtal mode’ medium high driving capability 11: ‘Xtal mode’...
Page 271 RM0351 Reset and clock control (RCC) Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. Cleared by writing to the RMVF bit. 0: No illegal mode reset occurred 1: Illegal mode reset occurred Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs.
Page 272 Reset and clock control (RCC) RM0351 Bits 11:8 MSISRANGE[3:1] MSI range after Standby mode Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 4 MHz.
Page 273 RM0351 Reset and clock control (RCC) Bits 6:2 Reserved, must be kept at reset value Bit 1 HSI48RDY: HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.
Page 274: Table 34. Rcc Register Map And Reset Values
Reset and clock control (RCC) RM0351 Table 34. RCC register map and reset values Off- Register MSIRANG RCC_CR 0x00 [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 Reset value HSITRIM[6:0] HSICAL[7:0]...
Page 275 RM0351 Reset and clock control (RCC) Table 34. RCC register map and reset values (continued) Off- Register RCC_CICR 0x20 0 0 0 0 0 0 0 0 0 0 0 Reset value RCC_ AHB1RSTR 0x28 Reset value RCC_ AHB2RSTR 0x2C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 276 Reset and clock control (RCC) RM0351 Table 34. RCC register map and reset values (continued) Off- Register RCC_AHB2 0x4C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value RCC_AHB3 0x50 Reset value RCC_ APB1ENR1 0x58...
Page 277 RM0351 Reset and clock control (RCC) Table 34. RCC register map and reset values (continued) Off- Register RCC_ APB1SM 0x78 ENR1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset value RCC_ APB1SM...
Page 278 Reset and clock control (RCC) RM0351 Table 34. RCC register map and reset values (continued) Off- Register I2C4 RCC_CCIPR2 0x9C [1:0] Reset value 1. Only for STM32L475xx/476xx/486xx devices 2. Only for STM32L496xx/4A6xx devices 278/1830 DocID024597 Rev 5...
Page 279 RM0351 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) Introduction The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable RC oscillator HSI48. The CRS provides a powerful means for oscillator output frequency evaluation, based on comparison with a selectable synchronization signal.
Page 280: Figure 21. Crs Block Diagram
Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) RM0351 CRS functional description 7.3.1 CRS block diagram Figure 21. CRS block diagram 7.3.2 Synchronization input The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can be the signal from the LSE clock or the USB SOF signal. For a better robustness of the SYNC input, a simple digital filter (2 out of 3 majority votes, sampled by the RC48 clock) is implemented to filter out any glitches.
Page 281: Figure 22. Crs Counter Behavior
RM0351 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) 7.3.3 Frequency error measurement The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each SYNC event. It starts counting down till it reaches the zero value, where the ESYNC (expected synchronization) event is generated.
Page 282 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) RM0351 7.3.4 Frequency error evaluation and automatic trimming The measured frequency error is evaluated by comparing its value with a set of limits: – TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register –...
Page 283: Table 35. Effect Of Low-Power Modes On Crs
RM0351 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) FELIM value The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number of HSI48 oscillator clock ticks.
Page 284 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) RM0351 CRS registers Refer to Section 1.1 on page 67 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 7.6.1 CRS control register (CRS_CR) Address offset: 0x00...
Page 285 RM0351 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) Bit 3 ESYNCIE: Expected SYNC interrupt enable 0: Expected SYNC (ESYNCF) interrupt disabled 1: Expected SYNC (ESYNCF) interrupt enabled Bit 2 ERRIE: Synchronization or trimming error interrupt enable 0: Synchronization or trimming error (ERRF) interrupt disabled 1: Synchronization or trimming error (ERRF) interrupt enabled Bit 1 SYNCWARNIE: SYNC warning interrupt enable 0: SYNC warning (SYNCWARNF) interrupt disabled...
Page 286 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) RM0351 Bits 26:24 SYNCDIV[2:0]: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 000: SYNC not divided (default) 001: SYNC divided by 2 010: SYNC divided by 4 011: SYNC divided by 8 100: SYNC divided by 16...
Page 287 RM0351 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) Bit 9 SYNCMISS: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken.
Page 288 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) RM0351 7.6.4 CRS interrupt flag clear register (CRS_ICR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 289: Table 37. Crs Register Map And Reset Values
RM0351 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx devices) 7.6.5 CRS register map Table 37. CRS register map and reset values Offset Register TRIM[5:0] CRS_CR 0x00 Reset value SYNC SYNC CRS_CFGR FELIM[7:0] RELOAD[15:0] 0x04 [1:0] [2:0] Reset value CRS_ISR FECAP[15:0] 0x08 Reset value...
Page 290 General-purpose I/Os (GPIO) RM0351 General-purpose I/Os (GPIO) Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 291: Figure 23. Basic Structure Of An I/O Port Bit
RM0351 General-purpose I/Os (GPIO) Figure 23 Figure 24 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively. Table 38 gives the possible port bit configurations. Figure 23. Basic structure of an I/O port bit Figure 24.
Page 292: Table 38. Port Bit Configuration Table
General-purpose I/Os (GPIO) RM0351 Table 38. Port bit configuration table MODE(i) OSPEED(i) PUPD(i) OTYPER(i) I/O configuration [1:0] [1:0] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [1:0] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 293 RM0351 General-purpose I/Os (GPIO) 8.3.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode. The debug pins are in AF pull-up/pull-down after reset: • PA15: JTDI in pull-up •...
Page 294 General-purpose I/Os (GPIO) RM0351 – Configure the desired I/O as an alternate function in the GPIOx_MODER register. • Additional functions: – For the ADC, DAC, OPAMP, and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC, OPAMP, and COMP registers.
Page 295 RM0351 General-purpose I/Os (GPIO) 8.3.6 GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same).
Page 296: Figure 25. Input Floating/Pull Up/Pull Down Configurations
General-purpose I/Os (GPIO) RM0351 Figure 25. Input floating/pull up/pull down configurations 8.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 297: Figure 26. Output Configuration
RM0351 General-purpose I/Os (GPIO) Figure 26. Output configuration 8.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured in open-drain or push-pull mode • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data) •...
Page 298: Figure 27. Alternate Function Configuration
General-purpose I/Os (GPIO) RM0351 Figure 27. Alternate function configuration 8.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin.
Page 299 RM0351 General-purpose I/Os (GPIO) 8.3.13 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.
Page 300 General-purpose I/Os (GPIO) RM0351 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A..I) Address offset:0x00...
Page 301 RM0351 General-purpose I/Os (GPIO) 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I) Address offset: 0x08 Reset value: • 0x0C00 0000 for port A • 0x0000 0000 for the other ports OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8 [1:0] [1:0] [1:0]...
Page 302 General-purpose I/Os (GPIO) RM0351 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 303 RM0351 General-purpose I/Os (GPIO) Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority.
Page 304 General-purpose I/Os (GPIO) RM0351 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 305 RM0351 General-purpose I/Os (GPIO) 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..I) Address offset: 0x24 Reset value: 0x0000 0000 AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0] Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: 1000: AF8...
Page 306 General-purpose I/Os (GPIO) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ASC15 ASC14 ASC13 ASC12 ASC11 ASC10 ASC9 ASC8 ASC7 ASC6 ASC5 ASC4 ASC3 ASC2 ASC1 ASC0 Bits 31:16 Reserved Bits 15:0 ASCy: Port x analog switch control y (y= 0..15) These bits are written by software to configure the analog connection of the IOs 0: Disconnect analog switch to the ADC input (reset state) 1: Connect analog switch to the ADC input...
Page 307: Table 39. Gpio Register Map And Reset Values
RM0351 General-purpose I/Os (GPIO) 8.4.13 GPIO register map The following table gives the GPIO register map and reset values. Table 39. GPIO register map and reset values Offset Register GPIOA_MODER 0x00 Reset value GPIOB_MODER 0x00 Reset value GPIOx_MODER (where x = C..I) 0x00 Reset value GPIOx_OTYPER...
Page 308 General-purpose I/Os (GPIO) RM0351 Table 39. GPIO register map and reset values (continued) Offset Register GPIOx_ODR (where x = A..I) 0x14 Reset value GPIOx_BSRR (where x = A..I) 0x18 Reset value GPIOx_LCKR (where x = A..I) 0x1C Reset value GPIOx_AFRL AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] (where x = A..I) 0x20...
Page 309 RM0351 System configuration controller (SYSCFG) System configuration controller (SYSCFG) SYSCFG main features The STM32L4x5/STM32L4x6 devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs •...
Page 310 System configuration controller (SYSCFG) RM0351 Bit 8 FB_MODE: Flash Bank mode selection 0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 2 mapped at 0x0808 0000 (and aliased at 0x0008 0000) 1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 1 mapped at 0x0808 0000 (and aliased at 0x0008 0000) Bits 7:3 Reserved, must be kept at reset value.
Page 311 RM0351 System configuration controller (SYSCFG) Bits 31:26 FPU_IE[5..0]: Floating Point Unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable FPU_IE[4]: Input denormal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation interrupt enable Bits 25:24 Reserved, must be kept at reset value.
Page 312 System configuration controller (SYSCFG) RM0351 Bit 8 BOOSTEN: I/O analog switch voltage booster enable 0: I/O analog switches are supplied by V voltage. This is the recommended configuration when using the ADC in high V voltage operation. 1: I/O analog switches are supplied by a dedicated voltage booster (supplied by V ).
Page 313 RM0351 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI3[3:0]: EXTI 3 configuration bits These bits are written by software to select the source input for the EXTI3 external interrupt. 0000: PA[3] pin 0001: PB[3] pin 0010: PC[3] pin 0011: PD[3] pin...
Page 314 System configuration controller (SYSCFG) RM0351 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 0000 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI7[3:0]: EXTI 7 configuration bits These bits are written by software to select the source input for the EXTI7 external interrupt.
Page 315 RM0351 System configuration controller (SYSCFG) Bits 11:8 EXTI6[3:0]: EXTI 6 configuration bits These bits are written by software to select the source input for the EXTI6 external interrupt. 0000: PA[6] pin 0001: PB[6] pin 0010: PC[6] pin 0011: PD[6] pin 0100: PE[6] pin 0101: PF[6] pin 0110: PG[6] pin...
Page 316 System configuration controller (SYSCFG) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI11[3:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt. 0000: PA[11] pin 0001: PB[11] pin 0010: PC[11] pin 0011: PD[11] pin...
Page 317 RM0351 System configuration controller (SYSCFG) 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI15[3:0]: EXTI 15 configuration bits These bits are written by software to select the source input for the EXTI15 external interrupt.
Page 318 System configuration controller (SYSCFG) RM0351 Bits 11:8 EXTI14[3:0]: EXTI 14 configuration bits These bits are written by software to select the source input for the EXTI14 external interrupt. 0000: PA[14] pin 0001: PB[14] pin 0010: PC[14] pin 0011: PD[14] pin 0100: PE[14] pin 0101: PF[14] pin 0110: PG[14] pin...
Page 319 RM0351 System configuration controller (SYSCFG) Bits 31:2 Reserved, must be kept at reset value Bit 1 SRAM2BSY: SRAM2 busy by erase operation 0: No SRAM2 erase operation is on going. 1: SRAM2 erase operation is on going. Bit 0 SRAM2ER: SRAM2 Erase Setting this bit starts a hardware SRAM2 erase operation.
Page 320 System configuration controller (SYSCFG) RM0351 Bit 2 PVDL: PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
Page 321 RM0351 System configuration controller (SYSCFG) KEY[7:0] Bits 31:8 Reserved, must be kept at reset value Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register. 1.
Page 322: Table 40. Syscfg Register Map And Reset Values
System configuration controller (SYSCFG) RM0351 9.2.12 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 40. SYSCFG register map and reset values Offset Register SYSCFG_ MEM_ MODE MEMRMP 0x00 Reset value SYSCFG_CFGR1 FPU_IE[5..0] 0x04 Reset value EXTI3...
Page 323 RM0351 System configuration controller (SYSCFG) Refer to Section 2.2.2 on page 75 for the register boundary addresses. DocID024597 Rev 5 323/1830...
Page 324 Peripherals interconnect matrix RM0351 Peripherals interconnect matrix 10.1 Introduction Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections remove software latency and allow design of predictable system.
Page 325: Table 41. Stm32L4X5/Stm32L4X6 Peripherals Interconnect Matrix
RM0351 Peripherals interconnect matrix 10.2 Connection summary 10.3 Interconnection details (1) (2) Table 41. STM32L4x5/STM32L4x6 peripherals interconnect matrix Destination Source TIM1 TIM8 TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM15 TIM16 TIM17 LPTIM1 LPTIM2 ADC1 ADC2 ADC3 DFSDM1 T. Sensor VBAT VREFINT OPAMP1 12 12...
Page 326 Peripherals interconnect matrix RM0351 (1) (2) Table 41. STM32L4x5/STM32L4x6 peripherals interconnect matrix (continued) Destination Source EXTI COMP1 13 13 13 13 13 13 13 COMP2 13 13 13 13 13 13 13 SYST ERR 14 14 14 14 14 1. Numbers in table are links to corresponding detailed sub-section in Section 10.3: Interconnection details.
Page 327 RM0351 Peripherals interconnect matrix Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC (ADC1/ADC2/ADC3) Purpose General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers (TIM1/TIM8), general-purpose timer (TIM15) and EXTI can be used to generate an ADC triggering event.
Page 328 Peripherals interconnect matrix RM0351 10.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC (DAC1/DAC2) Purpose General-purpose timers (TIM2/TIM4/TIM5), basic timers (TIM6, TIM7), advanced-control timers (TIM8) and EXTI can be used as triggering event to start a DAC conversion. Triggering signals The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC inputs.
Page 329 RM0351 Peripherals interconnect matrix Timer break is described in: • Section 30.3.16: Using the break function (TIM1/TIM8) • Section 32.4.13: Using the break function (TIM15/TIM16/TIM17) Triggering signals The output (from DFSDM1) is on signals dfsdm1_break[0:3] directly connected to timer and ‘Ored’...
Page 330 Peripherals interconnect matrix RM0351 10.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators (COMP1/COMP2) Purpose Advanced-control timers (TIM1/TIM8), general-purpose timers (TIM2/TIM3) and general- purpose timer (TIM15) can be used as blanking window input to COMP1/COMP2 The blanking function is described in Section 22.3.7: Comparator output blanking function.
Page 331 RM0351 Peripherals interconnect matrix 10.3.12 From internal analog source to ADC (ADC1/ADC2/ADC3) and OPAMP (OPAMP1/OPAM2) Purpose Internal temperature sensor (V ) and V monitoring channel are connected to ADC1/ADC3 input channels. Internal reference voltage (V ) is connected to ADC1 input channels. REFINT OPAMP1 and OPAMP2 outputs can be connected to ADC1 or ADC2 input channels through the GPIO.
Page 332 Peripherals interconnect matrix RM0351 The possible connections are given in: • Section 30.4.21: TIM1 option register 1 (TIM1_OR1) • Section 30.4.22: TIM8 option register 1 (TIM8_OR1) • Section 30.4.26: TIM1 option register 2 (TIM1_OR2) • Section 30.4.28: TIM8 option register 2 (TIM8_OR2) •...
Page 333 RM0351 Peripherals interconnect matrix 10.3.16 From ADC (ADC1/ADC2/ADC3) to DFSDM (only for STM32L496xx/4A6xx devices) Purpose Up to 3 internal ADC results can be directly connected through a parallel bus to DFSDM input in order to use DFSDM filtering capabilities. The feature is described as part of DFSDM peripheral description in Section 24.4.6: Parallel data inputs - Input from internal ADC...
Page 334: Table 42. Dma Implementation
Direct memory access controller (DMA) RM0351 Direct memory access controller (DMA) 11.1 Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions.
Page 335: Figure 29. Dma Block Diagram
RM0351 Direct memory access controller (DMA) 11.4 DMA functional description The block diagram is shown in the following figure. Figure 29. DMA block diagram The DMA controller performs direct memory transfer by sharing the system bus with the ® Cortex -M4 core.
Page 336 Direct memory access controller (DMA) RM0351 Controller. The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller. Once the request is de-asserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction.
Page 337 RM0351 Direct memory access controller (DMA) transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero).
Page 338: Table 43. Programmable Data Width & Endian Behavior (When Bits Pinc = Minc = 1)
Direct memory access controller (DMA) RM0351 If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode.
Page 339: Table 44. Dma Interrupt Requests
RM0351 Direct memory access controller (DMA) Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below:...
Page 340 Direct memory access controller (DMA) RM0351 11.4.7 DMA request mapping DMA controller The hardware requests from the peripherals (TIM1/2/3/4/5/6/7/8/15/16/17, ADC1/2/3, DAC1/2, SPI1/2/3, I2C1/2/3/4, SDMMC1, QUADSPI, SWPMI1, DFSDM1, SAI1/2, AES, HASH, DCMI, USART1/2/3, UART4/5 and LPUART1) are mapped to the DMA1 or DMA2 channels (1 to 7) through the DMA1/2 channel selection register.
Page 341: Figure 30. Dma1 Request Mapping
RM0351 Direct memory access controller (DMA) Figure 30. DMA1 request mapping DocID024597 Rev 5 341/1830...
Page 342: Table 45. Summary Of The Dma1 Requests For Each Channel
Direct memory access controller (DMA) RM0351 Figure 31. DMA2 request mapping Table 45. Summary of the DMA1 requests for each channel Request. Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 number DFSDM1_ DFSDM1_ DFSDM1_ DFSDM1_ ADC1 ADC2...
Page 343: Table 46. Summary Of The Dma2 Requests For Each Channel
RM0351 Direct memory access controller (DMA) Table 45. Summary of the DMA1 requests for each channel (continued) Request. Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 number USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I2C3_TX I2C3_RX I2C2_TX I2C2_RX...
Page 344 Direct memory access controller (DMA) RM0351 11.5 DMA registers Refer to Section 1.1 on page 67 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32- bit). 11.5.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00...
Page 345 RM0351 Direct memory access controller (DMA) 11.5.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Bits 31:28 Reserved, must be kept at reset value.
Page 346 Direct memory access controller (DMA) RM0351 11.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 347 RM0351 Direct memory access controller (DMA) Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable...
Page 348 Direct memory access controller (DMA) RM0351 11.5.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Res. Res. Res. Res.
Page 349 RM0351 Direct memory access controller (DMA) 11.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. MA [31:16] MA [15:0] Bits 31:0 MA[31:0]: Memory address...
Page 350 Direct memory access controller (DMA) RM0351 11.5.7 DMA1 channel selection register (DMA1_CSELR) Address offset: 0xA8 (with respect to DMA1 base address) Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels (see Figure 30). Res. Res.
Page 351 RM0351 Direct memory access controller (DMA) Bits 15:12 C4S[3:0]: DMA channel 4 selection 0000: Channel 4 mapped on DFSDM1_FLT0 0001: Channel 4 mapped on SPI2_RX 0010: Channel 4 mapped on USART1_TX 0011: Channel 4 mapped on I2C2_TX 0100: Reserved 0101: Channel 4 mapped on TIM7_UP/DAC2 0110: Channel 4 mapped on TIM4_CH2 0111: Channel 4 mapped on TIM1_CH4/TIM1_TRIG/TIM1_COM others: Reserved...
Page 352 Direct memory access controller (DMA) RM0351 11.5.8 DMA2 channel selection register (DMA2_CSELR) Address offset: 0xA8 (with respect to DMA2 base address) Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels (see Figure 31). Res. Res.
Page 353 RM0351 Direct memory access controller (DMA) Bits 15:12 C4S[3:0]: DMA channel 4 selection 0000: Channel 4 mapped on ADC2 0001: Channel 4 mapped on SAI2_B 0010: Reserved 0011: Channel 4 mapped on TIM6_UP/DAC1 0100: Channel 4 mapped on SPI1_TX 0101: Channel 4 mapped on TIM5_CH2 0110: Reserved 0111: Channel 4 mapped on SDMMC1 others: Reserved...
Page 354: Table 47. Dma Register Map And Reset Values
Direct memory access controller (DMA) RM0351 11.5.9 DMA register map The following table gives the DMA register map and the reset values. Table 47. DMA register map and reset values Offset Register DMA_ISR 0x00 Reset value DMA_IFCR 0x04 Reset value DMA_CCR1 [1:0] 0x08...
Page 355 RM0351 Direct memory access controller (DMA) Table 47. DMA register map and reset values (continued) Offset Register 0x40 Reserved DMA_CCR4 [1:0] 0x44 Reset value DMA_CNDTR4 NDT[15:0] 0x48 Reset value DMA_CPAR4 PA[31:0] 0x4C Reset value DMA_CMAR4 MA[31:0] 0x50 Reset value 0x54 Reserved DMA_CCR5 [1:0]...
Page 356 Direct memory access controller (DMA) RM0351 Table 47. DMA register map and reset values (continued) Offset Register DMA_CPAR7 PA[31:0] 0x88 Reset value DMA_CMAR7 MA[31:0] 0x8C Reset value 0x90 - Reserved 0xA7 DMA_CSELR C7S[3:0] C6S[3:0] C5S[3:0] C4S[3:0] C3S[3:0] C2S[3:0] C1S[3:0] 0xA8 Reset value Refer to Section 2.2.2 on page 75...
Page 357 RM0351 Chrom-Art Accelerator™ controller (DMA2D) Chrom-Art Accelerator™ controller (DMA2D) The DMA2D is present on L496/L4A6 devices only. 12.1 DMA2D introduction The Chrom-Art Accelerator™ (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations: • Filling a part or the whole of a destination image with a specific color •...
Page 358 Chrom-Art Accelerator™ controller (DMA2D) RM0351 • Area filling with a fixed color • Copy from an area to another • Copy with pixel format conversion between source and destination images • Copy from two sources with independent color format and blending •...
Page 359 RM0351 Chrom-Art Accelerator™ controller (DMA2D) Figure 32. DMA2D block diagram 12.3.2 DMA2D control The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR) which allows selecting: The user application can perform the following operations: • Select the operating mode •...
Page 360: Table 48. Supported Color Mode In Input
Chrom-Art Accelerator™ controller (DMA2D) RM0351 They are programmed through a set of control registers: • DMA2D foreground memory address register (DMA2D_FGMAR) • DMA2D foreground offset register (DMA2D_FGOR) • DMA2D background memory address register (DMA2D_BGMAR) • DMA2D background offset register (DMA2D_BGBOR) •...
Page 361: Table 49. Data Order In Memory
RM0351 Chrom-Art Accelerator™ controller (DMA2D) The color format are coded as follows: • Alpha value field: transparency 0xFF value corresponds to an opaque pixel and 0x00 to a transparent one. • R field for Red • G field for Green •...
Page 362 Chrom-Art Accelerator™ controller (DMA2D) RM0351 The alpha channel can be: • kept as it is (no modification), • replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR, • or replaced by the original alpha value multiplied by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255. Table 50.
Page 363: Table 51. Supported Clut Color Mode
RM0351 Chrom-Art Accelerator™ controller (DMA2D) occurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in DMA2D_CR. • Manual loading The application has to program the CLUT manually through the DMA2D AHB slave port to which the local CLUT memory is mapped.The foreground CLUT is located at address offset 0x0400 and the background CLUT at address offset 0x0800.
Page 364: Table 53. Supported Color Mode In Output
Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.3.7 DMA2D output PFC The output PFC performs the pixel format conversion from 32 bits to the output format defined in the CM[2:0] field of the DMA2D output pixel format converter configuration register (DMA2D_OPFCCR). The supported output formats are given in Table 53: Supported color mode in output Table 53.
Page 365 RM0351 Chrom-Art Accelerator™ controller (DMA2D) Table 54. Data order in memory (continued) Color Mode @ + 3 @ + 2 @ + 1 @ + 0 ARGB1555 [0]R [4:0]G [4:3] [2:0]B [4:0] [0]R [4:0]G [4:3] [2:0]B [4:0] ARGB4444 [3:0]R [3:0] [3:0]B [3:0] [3:0]R...
Page 366 Chrom-Art Accelerator™ controller (DMA2D) RM0351 The color format is set in the DMA2D_OPFCCR. The DMA2D does not perform any data fetching from any source. It just writes the color defined in the DMA2D_OCOLR register to the area located at the address pointed by the DMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.
Page 367 RM0351 Chrom-Art Accelerator™ controller (DMA2D) to obtain a fully opaque pixel. The alpha value can be modified according to the AM[1:0] bits of the DMA2D_FGPFCCR register: • It can be unchanged. • It can be replaced by the value defined in the ALPHA[7:0] value of the DMA2D_FGPFCCR register.
Page 368 Chrom-Art Accelerator™ controller (DMA2D) RM0351 The wrong configurations that can be detected are listed below: • Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR are not aligned with CCM of DMA2D_FGPFCCR. • Background CLUT automatic loading: MA bits of DMA2D_BGCMAR are not aligned with CCM of DMA2D_BGPFCCR •...
Page 369: Table 55. Dma2D Interrupt Requests
RM0351 Chrom-Art Accelerator™ controller (DMA2D) When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set. 12.3.14 Error management Two kind of errors can be triggered: •...
Page 370 Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.5 DMA2D registers 12.5.1 DMA2D control register (DMA2D_CR) Address offset: 0x0000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE[1:0] Res. Res. CEIE CTCIE CAEIE TWIE TCIE TEIE...
Page 371 RM0351 Chrom-Art Accelerator™ controller (DMA2D) Bit 8 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disable 1: TE interrupt enable Bits 7:3 Reserved, must be kept at reset value Bit 2 ABORT: Abort This bit can be used to abort the current transfer.
Page 372 Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.5.2 DMA2D Interrupt Status Register (DMA2D_ISR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 373 RM0351 Chrom-Art Accelerator™ controller (DMA2D) 12.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 374 Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.5.4 DMA2D foreground memory address register (DMA2D_FGMAR) Address offset: 0x000C Reset value: 0x0000 0000 MA[31:16] MA[15:0] Bits 31:0 MA[31: 0]: Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled.
Page 375 RM0351 Chrom-Art Accelerator™ controller (DMA2D) MA[31:16] MA[15:0] Bits 31: 0 MA[31: 0]: Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read- only.
Page 376 Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) Address offset: 0x001C Reset value: 0x0000 0000 ALPHA[7:0] Res. Res. Res. Res. AM[1:0] CS[7:0] Res. Res. START CM[3:0] Bits 31:24 ALPHA[7: 0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits.
Page 377 RM0351 Chrom-Art Accelerator™ controller (DMA2D) Bit 5 START: Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR –...
Page 378 Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.5.9 DMA2D foreground color register (DMA2D_FGCOLR) Address offset: 0x0020 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0] GREEN[7:0] BLUE[7:0] Bits 31:24 Reserved, must be kept at reset value Bits 23:16 RED[7: 0]: Red Value These bits defines the red value for the A4 or A8 mode of the foreground image.
Page 379 RM0351 Chrom-Art Accelerator™ controller (DMA2D) 12.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) Address offset: 0x0024 Reset value: 0x0000 0000 ALPHA[7:0] Res. Res. Res. Res. AM[1:0] CS[7:0] Res. Res. START CM[3:0] Bits 31:24 ALPHA[7: 0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0].
Page 380 Chrom-Art Accelerator™ controller (DMA2D) RM0351 Bit 5 START: Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR –...
Page 381 RM0351 Chrom-Art Accelerator™ controller (DMA2D) 12.5.11 DMA2D background color register (DMA2D_BGCOLR) Address offset: 0x0028 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0] GREEN[7:0] BLUE[7:0] Bits 31:24 Reserved, must be kept at reset value Bits 23:16 RED[7: 0]: Red Value These bits define the red value for the A4 or A8 mode of the background.
Page 382 Chrom-Art Accelerator™ controller (DMA2D) RM0351 Bits 31: 0 MA[31: 0]: Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only.
Page 383 RM0351 Chrom-Art Accelerator™ controller (DMA2D) Bits 31:22 Reserved, must be kept at reset value Bit 21 RBS: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 0: Regular mode (RGB or ARGB) 1: Swap mode (BGR or ABGR) Bit 20 AI: Alpha Inverted...
Page 384 Chrom-Art Accelerator™ controller (DMA2D) RM0351 Bits 23:16 RED[7: 0]: Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 15:8 GREEN[7: 0]: Green Value These bits define the green value of the output image.
Page 385 RM0351 Chrom-Art Accelerator™ controller (DMA2D) 12.5.16 DMA2D output memory address register (DMA2D_OMAR) Address offset: 0x003C Reset value: 0x0000 0000 MA[31:16] MA[15:0] Bits 31: 0 MA[31: 0]: Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled.
Page 386 Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.5.17 DMA2D output offset register (DMA2D_OOR) Address offset: 0x0040 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LO[13:0] Bits 31:14 Reserved, must be kept at reset value Bits 13:0 LO[13: 0]: Line Offset Line offset used for the output (expressed in pixels).
Page 387 RM0351 Chrom-Art Accelerator™ controller (DMA2D) 12.5.19 DMA2D line watermark register (DMA2D_LWR) Address offset: 0x0048 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LW[15:0] Bits 31:16 Reserved, must be kept at reset value Bits 15:0 LW[15:0]: Line watermark These bits allow to configure the line watermark for interrupt generation.
Page 388 Chrom-Art Accelerator™ controller (DMA2D) RM0351 MAJREV[3:0] MINREV[3:0] Bits 31:8 Reserved, can be used for some special purpose. Bits 7:4 MAJREV[3:0]: Major revision This field returns the major revision of the DMA2D IP. Bits 3:0 MINREV[3:0]: Minor revision This field returns the minor revision of the DMA2D IP. 12.5.22 DMA2D IP identification register (DMA2D_IPIDR) Address offset: 0x03F8...
Page 389 RM0351 Chrom-Art Accelerator™ controller (DMA2D) 12.5.23 DMA2D IP size identification register (DMA2D_SIDR) Address offset: 0x03FC Reset value: 0xA3C5 DD01 SID[31:16] SID[15:0] Bits 31:0 SID[31:0]: Size identification This field returns the size and identification of the DMA2D IP. DocID024597 Rev 5 389/1830...
Page 390: Table 56. Dma2D Register Map And Reset Values
Chrom-Art Accelerator™ controller (DMA2D) RM0351 12.5.24 DMA2D register map The following table summarizes the DMA2D registers. Refer to Section 2.2.2 on page 75 the DMA2D register base address. Table 56. DMA2D register map and reset values Offset Register DMA2D_CR 0x0000 Reset value DMA2D_ISR 0x0004...
Page 391 RM0351 Chrom-Art Accelerator™ controller (DMA2D) Table 56. DMA2D register map and reset values (continued) Offset Register ALPHA[7:0] RED[7:0] GREEN[7:0] BLUE[7:0] RED[4:0] GREEN[5:0] BLUE[4:0] DMA2D_OCOLR 0x0038 RED[4:0] GREEN[4:0] BLUE[4:0] ALPHA[3:0] RED[3:0] GREEN[3:0] BLUE[3:0] Reset value DMA2D_OMAR MA[31:0] 0x003C Reset value DMA2D_OOR LO[13:0] 0x0040 Reset value...
Page 392 Nested vectored interrupt controller (NVIC) RM0351 Nested vectored interrupt controller (NVIC) 13.1 NVIC main features • 82 (for STM32L475xx/476xx/486xx devices), 91 (for STM32L496xx/4A6xx devices) ® maskable interrupt channels (not including the sixteen Cortex -M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) •...
Page 393: Table 57. Stm32L4X5/Stm32L4X6 Vector Table
RM0351 Nested vectored interrupt controller (NVIC) 13.3 Interrupt and exception vectors The grey rows in Table 57 describe the vectors without specific position. Table 57. STM32L4x5/STM32L4x6 vector table Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 Non maskable interrupt.
Page 394 Nested vectored interrupt controller (NVIC) RM0351 Table 57. STM32L4x5/STM32L4x6 vector table (continued) Type of Acronym Description Address priority settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078 settable DMA1_CH5...
Page 395 RM0351 Nested vectored interrupt controller (NVIC) Table 57. STM32L4x5/STM32L4x6 vector table (continued) Type of Acronym Description Address priority settable TIM8_UP TIM8 Update interrupt 0x0000 00F0 settable TIM8_TRG_COM TIM8 trigger and commutation interrupt 0x0000 00F4 settable TIM8_CC TIM8 capture compare interrupt 0x0000 00F8 settable ADC3...
Page 396 Nested vectored interrupt controller (NVIC) RM0351 Table 57. STM32L4x5/STM32L4x6 vector table (continued) Type of Acronym Description Address priority settable SAI2 SAI2 global interrupt 0x0000 016C settable SWPMI1 SWPMI1 global interrupt 0x0000 0170 settable TSC global interrupt 0x0000 0174 settable LCD global interrupt 0x0000 0178 settable AES global interrupt...
Page 397 RM0351 Extended interrupts and events controller (EXTI) Extended interrupts and events controller (EXTI) 14.1 Introduction The EXTI main features are as follows: • Generation of up to 40 (STM32L475xx/476xx/486xx devices), up to 41 (STM32L496xx/4A6xx devices) event/interrupt requests – 26 configurable lines –...
Page 398: Figure 33. Configurable Interrupt/Event Block Diagram
Extended interrupts and events controller (EXTI) RM0351 To generate an event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated.
Page 399 RM0351 Extended interrupts and events controller (EXTI) 14.3.3 Peripherals asynchronous Interrupts Some peripherals are able to generate events when the system is in run mode and also when the system is in Stop mode, allowing to wake up the system from Stop mode. To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g.
Page 400: Table 58. Exti Lines Connections
Extended interrupts and events controller (EXTI) RM0351 Figure 34. External interrupt/event GPIO mapping 1. Only on STM32L496xx/4A6xx devices The EXTI lines are connected as shown in Table 58: EXTI lines connections. Table 58. EXTI lines connections EXTI line Line source Line type 0-15 GPIO...
Page 401 RM0351 Extended interrupts and events controller (EXTI) Table 58. EXTI lines connections (continued) EXTI line Line source Line type RTC tamper or timestamp or configurable CSS_LSE RTC wakeup timer configurable COMP1 output configurable COMP2 output configurable I2C1 wakeup direct I2C2 wakeup direct I2C3 wakeup direct...
Page 402 Extended interrupts and events controller (EXTI) RM0351 14.5 registers EXTI Refer to Section 1.1 on page 67 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 14.5.1 Interrupt mask register 1 (EXTI_IMR1) Address offset: 0x00 Reset value: 0xFF82 0000 IM31...
Page 403 RM0351 Extended interrupts and events controller (EXTI) Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 RT18 Res. RT16 RT15 RT14 RT13 RT12 RT11 RT10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:18 RTx: Rising trigger event configuration bit of line x (x = 22 to 18) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bit 17 Reserved, must be kept at reset value.
Page 404 Extended interrupts and events controller (EXTI) RM0351 Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line.
Page 405 RM0351 Extended interrupts and events controller (EXTI) 14.5.6 Pending register 1 (EXTI_PR1) Address offset: 0x14 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 PIF18 Res. PIF16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PIF15 PIF14 PIF13...
Page 406 Extended interrupts and events controller (EXTI) RM0351 14.5.8 Event mask register 2 (EXTI_EMR2) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 407 RM0351 Extended interrupts and events controller (EXTI) 14.5.10 Falling trigger selection register 2 (EXTI_FTSR2) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 408 Extended interrupts and events controller (EXTI) RM0351 14.5.12 Pending register 2 (EXTI_PR2) Address offset: 0x34 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 409: Table 59. Extended Interrupt/Event Controller Register Map And Reset Values
RM0351 Extended interrupts and events controller (EXTI) 14.5.13 EXTI register map Table 59 gives the EXTI register map and the reset values. Table 59. Extended interrupt/event controller register map and reset values Offset Register EXTI_IMR1 0x00 Reset value EXTI_EMR1 0x04 Reset value EXTI_RTSR1 0x08...
Page 410 Cyclic redundancy check calculation unit (CRC) RM0351 Cyclic redundancy check calculation unit (CRC) 15.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 411: Table 60. Crc Internal Input/Output Signals
RM0351 Cyclic redundancy check calculation unit (CRC) 15.3 CRC functional description 15.3.1 CRC block diagram Figure 35. CRC calculation unit block diagram 15.3.2 CRC internal signals Table 60. CRC internal input/output signals Signal name Signal type Description crc_hclk Digital input AHB clock 15.3.3 CRC operation...
Page 412 Cyclic redundancy check calculation unit (CRC) RM0351 The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: 0x58D43CB2 with bit-reversal done by byte 0xD458B23C with bit-reversal done by half-word...
Page 413 RM0351 Cyclic redundancy check calculation unit (CRC) 15.4 CRC registers 15.4.1 Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0] Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read.
Page 414 Cyclic redundancy check calculation unit (CRC) RM0351 15.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res. Res.
Page 415: Table 61. Crc Register Map And Reset Values
RM0351 Cyclic redundancy check calculation unit (CRC) Bits 31:0 CRC_INIT: Programmable initial CRC value This register is used to write the CRC initial value. 15.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C11DB7 POL[31:16] POL[15:0] Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation.
Page 416 Flexible static memory controller (FSMC) RM0351 Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND memory controller This memory controller is also named Flexible memory controller (FMC). 16.1 FMC main features The FMC functional block makes the interface with: synchronous and asynchronous static...
Page 417: Figure 36. Fmc Block Diagram
RM0351 Flexible static memory controller (FSMC) At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes. The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up.
Page 418 Flexible static memory controller (FSMC) RM0351 16.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 419 RM0351 Flexible static memory controller (FSMC) can be read/written from/to the Flash memory), Write transactions and Read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte). Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported. The memories must be configured in linear burst mode of undefined length.
Page 420: Table 62. Nor/Psram Bank Selection
Flexible static memory controller (FSMC) RM0351 Figure 37. FMC memory banks 16.4.1 NOR/PSRAM address mapping HADDR[27:26] bits are used to select one of the four memory banks as shown in Table Table 62. NOR/PSRAM bank selection HADDR[27:26] Selected bank Bank 1 - NOR/PSRAM 1 Bank 1 - NOR/PSRAM 2 Bank 1 - NOR/PSRAM 3 Bank 1 - NOR/PSRAM 4...
Page 421: Table 64. Nand Memory Mapping And Timing Registers
RM0351 Flexible static memory controller (FSMC) 1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the address for external memory FMC_A[24:0]. Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0]. 16.4.2 NAND Flash memory address mapping The NAND bank is divided into memory areas as indicated in...
Page 422 Flexible static memory controller (FSMC) RM0351 16.5 NOR Flash/PSRAM controller The FMC generates the appropriate signal timings to drive the following types of memories: • Asynchronous SRAM and ROM – 8 bits – 16 bits • PSRAM (Cellular RAM) – Asynchronous mode –...
Page 423: Table 66. Programmable Nor/Psram Access Parameters
RM0351 Flexible static memory controller (FSMC) Table 66. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min. Max. Address Duration of the address AHB clock cycle Asynchronous setup setup phase (HCLK) Duration of the address hold Asynchronous, AHB clock cycle Address hold phase muxed I/Os...
Page 424: Table 68. 16-Bit Multiplexed I/O Nor Flash Memory
Flexible static memory controller (FSMC) RM0351 NOR Flash memory, 16-bit multiplexed I/Os Table 68. 16-bit multiplexed I/O NOR Flash memory FMC signal name Function Clock (for synchronous access) A[25:16] Address bus 16-bit multiplexed, bidirectional address/data bus (the 16-bit address AD[15:0] A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] Chip Select, x = 1..4...
Page 425: Table 71. Nor Flash/Psram: Example Of Supported Memories And Transactions
RM0351 Flexible static memory controller (FSMC) Table 70. 16-Bit multiplexed I/O PSRAM (continued) FMC signal name I/O Function NE[x] Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) Output enable Write enable NL(= NADV) Address valid PSRAM input (memory signal name: NADV) NWAIT PSRAM wait input signal to the FMC NBL[1:0]...
Page 426 Flexible static memory controller (FSMC) RM0351 Table 71. NOR Flash/PSRAM: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Use of byte lanes NBL[1:0] Asynchronous Asynchronous Asynchronous Split into 2 FMC accesses PSRAM Asynchronous Split into 2 FMC accesses...
Page 427: Figure 38. Mode1 Read Access Waveforms
RM0351 Flexible static memory controller (FSMC) 16.5.4 NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, PSRAM, SRAM) • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory • The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns) •...
Page 428: Table 72. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Figure 39. Mode1 write access waveforms The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST >...
Page 429: Table 73. Fmc_Btrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 72. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MWID As needed MTYP As needed, exclude 0x2 (NOR Flash memory) MUXE MBKEN Table 73. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved...
Page 430: Figure 40. Modea Read Access Waveforms
Flexible static memory controller (FSMC) RM0351 Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 40. ModeA read access waveforms 1. NBL[1:0] are driven low during the read access Figure 41. ModeA write access waveforms 430/1830 DocID024597 Rev 5...
Page 431: Table 74. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 74. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 As needed (this bit is reserved for STM32L475xx/476xx/486xx WFDIS devices) CCLKEN...
Page 432: Table 76. Fmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 76. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST HCLK cycles) for write 15:8 DATAST...
Page 433: Figure 43. Mode2 Write Access Waveforms
RM0351 Flexible static memory controller (FSMC) Figure 43. Mode2 write access waveforms Figure 44. ModeB write access waveforms The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). DocID024597 Rev 5 433/1830...
Page 434: Table 77. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 77. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 As needed (this bit is reserved for STM32L475xx/476xx/486xx WFDIS devices) CCLKEN As needed CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode)
Page 435: Table 79. Fmc_Bwtrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 79. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 0x1 if extended mode is set 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the access second phase (DATAST HCLK cycles) for 15:8 DATAST...
Page 436: Table 80. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Figure 46. ModeC write access waveforms The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 80. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 437: Table 81. Fmc_Btrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 80. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x02 (NOR Flash memory) MUXEN MBKEN Table 81. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24...
Page 438: Figure 47. Moded Read Access Waveforms
Flexible static memory controller (FSMC) RM0351 Mode D - asynchronous access with extended address Figure 47. ModeD read access waveforms Figure 48. ModeD write access waveforms 438/1830 DocID024597 Rev 5...
Page 439: Table 83. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 83. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 440: Table 85. Fmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 85. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST + 1 HCLK cycles) for 15:8 DATAST...
Page 441: Table 86. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Figure 50. Muxed write access waveforms The difference with ModeD is the drive of the lower address byte(s) on the data bus. Table 86. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 442: Table 87. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 86. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM) MUXEN MBKEN Table 87. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28...
Page 443: Figure 51. Asynchronous Wait During A Read Access Waveforms
RM0351 Flexible static memory controller (FSMC) The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: ≥...
Page 444: Figure 52. Asynchronous Wait During A Write Access Waveforms
Flexible static memory controller (FSMC) RM0351 Figure 52. Asynchronous wait during a write access waveforms 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. 16.5.5 Synchronous transactions The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below: FMC_CLK divider ratio max CLKDIV...
Page 445 RM0351 Flexible static memory controller (FSMC) Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles •...
Page 446: Figure 53. Wait Configuration Waveforms
Flexible static memory controller (FSMC) RM0351 Figure 53. Wait configuration waveforms 446/1830 DocID024597 Rev 5...
Page 447: Table 88. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Figure 54. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 88.
Page 448: Table 89. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 88. FMC_BCRx bit fields (continued) Bit number Bit name Value to set Reserved WAITPOL To be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN...
Page 449: Table 90. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Figure 55. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 90.
Page 450: Table 91. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 90. FMC_BCRx bit fields (continued) Bit number Bit name Value to set To be set to 1 if the memory supports this feature, to be kept at 0 WAITEN otherwise. WREN WAITCFG Reserved WAITPOL to be set according to memory BURSTEN...
Page 451 RM0351 Flexible static memory controller (FSMC) 16.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4) Address offset: 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
Page 452 Flexible static memory controller (FSMC) RM0351 Bits 18:16 CPSIZE[2:0]: CRAM page size. These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size).
Page 453 RM0351 Flexible static memory controller (FSMC) Bit 8 BURSTEN: Burst enable bit. This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode: 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1: Burst mode enable.
Page 454 Flexible static memory controller (FSMC) RM0351 Res. Res. ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET Bits 31:30 Reserved, must be kept at reset value Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
Page 455 RM0351 Flexible static memory controller (FSMC) Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to- write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ).
Page 456 Flexible static memory controller (FSMC) RM0351 Bits 7:4 ADDHLD[3:0]: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 38 Figure 50), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 ×...
Page 457 RM0351 Flexible static memory controller (FSMC) Bits 29:28 ACCMOD[1:0]: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D...
Page 458: Table 92. Programmable Nand Flash Access Parameters
Flexible static memory controller (FSMC) RM0351 Bits 3:0 ADDSET[3:0]: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 38 Figure 50), used in asynchronous accesses: 0000: ADDSET phase duration = 0 ×...
Page 459: Table 94. 16-Bit Nand Flash
RM0351 Flexible static memory controller (FSMC) Table 93. 8-bit NAND Flash (continued) FMC signal name Function Chip Select NOE(= NRE) Output enable (memory signal name: read enable, NRE) Write enable NWAIT/INT NAND Flash ready/busy input signal to the FMC Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.
Page 460: Table 95. Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0351 16.6.2 NAND Flash supported memories and transactions Table 95 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash controller are shown in gray. Table 95. Supported memories and transactions Memory Allowed/ Device...
Page 461: Figure 56. Nand Flash Controller Waveforms For Common Memory Access
RM0351 Flexible static memory controller (FSMC) Figure 56. NAND Flash controller waveforms for common memory access 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is (MEMHOLD + 2) HCLK cycles.
Page 462: Figure 57. Access To Non 'Ce Don't Care' Nand-Flash
Flexible static memory controller (FSMC) RM0351 details in Section 16.6.5: NAND Flash prewait functionality). The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank. While waiting, the controller holds the NCE signal active (low).
Page 463 RM0351 Flexible static memory controller (FSMC) When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the t timing. However any CPU read access to the NAND Flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.
Page 464 Flexible static memory controller (FSMC) RM0351 To perform an ECC computation: Enable the ECCEN bit in the FMC_PCR register. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. Read the ECC value available in the FMC_ECCR register and store it in a variable.
Page 465 RM0351 Flexible static memory controller (FSMC) Bits 12:9 TCLR[3:0]: CLE to RE delay. Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space.
Page 466 Flexible static memory controller (FSMC) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN Bits 31:7 Reserved, must be kept at reset value Bit 6 FEMPT: FIFO empty. Read-only bit that provides the status of the FIFO 0: FIFO not empty 1: FIFO empty Bit 5 IFEN: Interrupt falling edge detection enable bit...
Page 467 RM0351 Flexible static memory controller (FSMC) Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions: 0000 0000: 1 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 468 Flexible static memory controller (FSMC) RM0351 Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 0000 0000: 0 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 469: Table 96. Ecc Result Relevant Bits
RM0351 Flexible static memory controller (FSMC) ECC result registers (FMC_ECCR) Address offset: 0x94 Reset value: 0x0000 0000 This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 16.6.6: Computation of the error correction code (ECC) in NAND Flash...
Page 470: Table 97. Fmc Register Map
Flexible static memory controller (FSMC) RM0351 16.7 FMC register map Table 97. FMC register map Offset Register CPSIZE MWID MTYP FMC_BCR1 [2:0] [1:0] [1:0] 0x00 Reset value CPSIZE MWID MTYP FMC_BCR2 [2:0] [1:0] [1:0] 0x08 Reset value CPSIZE MWID MTYP FMC_BCR3 [2:0] [1:0]...
Page 471 RM0351 Flexible static memory controller (FSMC) Table 97. FMC register map (continued) Offset Register FMC_BWTR3 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x114 Reset value FMC_BWTR4 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x11C Reset value ECCPS PWID FMC_PCR TAR[3:0] TCLR[3:0] [2:0] [1:0] 0x80 Reset value FMC_SR 0x84 Reset value...
Page 472: Table 98. Quadspi Implementation
Quad-SPI interface (QUADSPI) RM0351 Quad-SPI interface (QUADSPI) 17.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers •...
Page 473: Table 99. Quadspi Pins
RM0351 Quad-SPI interface (QUADSPI) 17.4 QUADSPI functional description 17.4.1 QUADSPI block diagram Figure 58. QUADSPI block diagram when dual-flash mode is disabled Figure 59. QUADSPI block diagram when dual-flash mode is enabled 17.4.2 QUADSPI pins Table 99 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11 for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode.
Page 474: Figure 60. An Example Of A Read Command In Quad Mode
Quad-SPI interface (QUADSPI) RM0351 Table 99. QUADSPI pins Signal name Signal type Description BK1_IO2 Digital input/output Bidirectional IO in quad mode, for FLASH 1 BK1_IO3 Digital input/output Bidirectional IO in quad mode, for FLASH 1 Bidirectional IO in dual/quad modes or serial output BK2_IO0/SO Digital input/output in single mode, for FLASH 2...
Page 475 RM0351 Quad-SPI interface (QUADSPI) When IMODE = 00, the instruction phase is skipped, and the command sequence starts with the address phase, if present. Address phase In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the operation.
Page 476 Quad-SPI interface (QUADSPI) RM0351 In order to assure enough “turn-around” time for changing the data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the Flash memory. Data phase During the data phase, any number of bytes can be sent to, or received from the Flash memory.
Page 477 RM0351 Quad-SPI interface (QUADSPI) In each phase which is configured in dual mode: • IO0/IO1 are at high-impedance (input) during the data phase for read operations, and outputs in all other cases • IO2 is in output mode and forced to ‘0’ •...
Page 478: Figure 61. An Example Of A Ddr Command In Quad Mode
Quad-SPI interface (QUADSPI) RM0351 Figure 61. An example of a DDR command in quad mode Dual-flash mode When the DFM bit (QUADSPI_CR[6]) is 1, the QUADSPI is in dual-flash mode, where two external quad SPI Flash memories (FLASH 1 and FLASH 2) are used in order to send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput as well as the capacity.
Page 479 RM0351 Quad-SPI interface (QUADSPI) parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those of FLASH 2. 17.4.5 QUADSPI indirect mode When in indirect mode, commands are started by writing to QUADSPI registers and data is transferred by writing or reading the data register, in the same way as for other communication peripherals.
Page 480 Quad-SPI interface (QUADSPI) RM0351 FIFO and data management In indirect mode, data go through a 16-byte FIFO which is internal to the QUADSPI. FLEVEL[4:0] (QUADSPI_SR[12:8]) indicates how many bytes are currently being held in the FIFO. In indirect write mode (FMODE = 00), firmware adds data to the FIFO when it writes QUADSPI_DR.
Page 481 RM0351 Quad-SPI interface (QUADSPI) If the automatic-polling-mode-stop (APMS) bit is set, operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at ‘1’ and the periodic accesses continue until there is an abort or the QUADSPI is disabled (EN = 0). The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is deactivated).
Page 482 Quad-SPI interface (QUADSPI) RM0351 If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. When the QUADSPI executes two commands, one immediately after the other, it raises the chip select signal (nCS) high between the two commands for only one CLK cycle by default. If the Flash memory requires more time between commands, the chip select high time (CSHT) field can be used to specify the minimum number of CLK cycles (up to 8) that nCS must remain high.
Page 483 RM0351 Quad-SPI interface (QUADSPI) 17.4.11 QUADSPI usage The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]). Indirect mode procedure When FMODE is programmed to 00, indirect write mode is selected and data can be sent to the Flash memory. With FMODE = 01, indirect read mode is selected where data can be read from the Flash memory.
Page 484 Quad-SPI interface (QUADSPI) RM0351 QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01). When an address is required (ADMODE is not 00) and the data register does not need to be written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the address is updated with a write to QUADSPI_AR.
Page 485 RM0351 Quad-SPI interface (QUADSPI) QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR. SIOO has no effect when IMODE = 00 (no instruction). 17.4.13 QUADSPI error management A error can be generated in the following case: •...
Page 486: Figure 62. Ncs When Ckmode = 0 (T = Clk Period)
Quad-SPI interface (QUADSPI) RM0351 Figure 62. nCS when CKMODE = 0 (T = CLK period) When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and DDRM=0 (SDR mode), nCS still falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure Figure 63.
Page 487: Table 100. Quadspi Interrupt Requests
RM0351 Quad-SPI interface (QUADSPI) Figure 65. nCS when CKMODE = 1 with an abort (T = CLK period) When not in dual-flash mode (DFM = 0), only FLASH 1 is accessed and thus the BK2_nCS stays high. In dual-flash mode, BK2_nCS behaves exactly the same as BK1_nCS. Thus, if there is a FLASH 2 and if the application always stays in dual-flash mode, then FLASH 2 may use BK1_nCS and the pin outputting BK2_nCS can be used for other functions.
Page 488 Quad-SPI interface (QUADSPI) RM0351 17.6 QUADSPI registers 17.6.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 PRESCALER APMS Res. TOIE SMIE FTIE TCIE TEIE Res. Res. Res. Res. FTHRES FSEL Res. SSHIFT TCEN DMAEN ABORT Bits 31: 24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1).
Page 489 RM0351 Quad-SPI interface (QUADSPI) Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt.
Page 490 Quad-SPI interface (QUADSPI) RM0351 Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays.
Page 491 RM0351 Quad-SPI interface (QUADSPI) 17.6.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSIZE Res. Res. Res. Res. Res. CSHT Res. Res. Res. Res. Res. Res.
Page 492 Quad-SPI interface (QUADSPI) RM0351 17.6.3 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLEVEL[4:0] Res. Res. BUSY Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 FLEVEL[4:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO.
Page 493 RM0351 Quad-SPI interface (QUADSPI) 17.6.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 494 Quad-SPI interface (QUADSPI) RM0351 Bits 31:0 DL[31: 0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE.
Page 495 RM0351 Quad-SPI interface (QUADSPI) Bit 28 SIOO: Send instruction only once mode Section 17.4.12: Sending the instruction only once on page 484. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0.
Page 496 Quad-SPI interface (QUADSPI) RM0351 Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line...
Page 497 RM0351 Quad-SPI interface (QUADSPI) 17.6.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31: 0 ALTERNATE[31: 0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0.
Page 498 Quad-SPI interface (QUADSPI) RM0351 17.6.10 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 MASK[31:16] MASK[15:0] Bits 31: 0 MASK[31: 0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic...
Page 499 RM0351 Quad-SPI interface (QUADSPI) 17.6.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INTERVAL[15:0] Bits 31: 16 Reserved, must be kept at reset value. Bits 15: 0 INTERVAL[15: 0]: Polling interval Number of CLK cycles between to read during automatic polling phases.
Page 500: Table 101. Quadspi Register Map And Reset Values
Quad-SPI interface (QUADSPI) RM0351 17.6.14 QUADSPI register map Table 101. QUADSPI register map and reset values Offset Register FTHRES QUADSPI_CR PRESCALER[7:0] [3:0] 0x0000 Reset value QUADSPI_DCR FSIZE[4:0] CSHT 0x0004 Reset value QUADSPI_SR FLEVEL[5:0] 0x0008 Reset value QUADSPI_FCR 0x000C Reset value QUADSPI_DLR DL[31:0] 0x0010...
Page 501 RM0351 Analog-to-digital converters (ADC) Analog-to-digital converters (ADC) 18.1 Introduction This section describes the implementation of up to 3 ADCs: • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). • ADC3 is controlled independently. Each ADC consists of a 12-bit successive approximation analog-to-digital converter.
Page 502 Analog-to-digital converters (ADC) RM0351 18.2 ADC main features • High-performance features – Up to 3x ADCs, out of which two of them can operate in dual mode – ADC1 is connected to 16 external channels + 3 internal channels – ADC2 is connected to 16 external channels + 2 internal channels –...
Page 503: Table 102. Main Adc Features
RM0351 Analog-to-digital converters (ADC) – DAC1 and DAC2 internal channels, connected to ADC2 and ADC3 • Start-of-conversion can be initiated: – by software for both regular and injected conversions – by hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions •...
Page 504: Figure 66. Adc Block Diagram
Analog-to-digital converters (ADC) RM0351 18.4 ADC functional description 18.4.1 ADC block diagram Figure 66 shows the ADC block diagram and Table 104 gives the ADC pin description. Figure 66. ADC block diagram 504/1830 DocID024597 Rev 5...
Page 505: Table 103. Adc Internal Signals
RM0351 Analog-to-digital converters (ADC) 18.4.2 Pins and internal signals Table 103. ADC internal signals Signal Internal signal name Description type Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). EXT[15:0] Inputs These inputs are shared between the ADC master and the ADC slave.
Page 506 Analog-to-digital converters (ADC) RM0351 18.4.3 Clocks Dual clock domain architecture The dual clock-domain architecture means that the ADCs clock is independent from the AHB bus clock. The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 67: ADC clock scheme):...
Page 507 RM0351 Analog-to-digital converters (ADC) Figure 67. ADC clock scheme Clock ratio constraint between ADC clock and AHB clock There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio: •...
Page 508: Figure 68. Adc1 Connectivity
Analog-to-digital converters (ADC) RM0351 18.4.4 ADC1/2/3 connectivity ADC1, ADC2 and ADC3 are tightly coupled and share some external channels as described in the below figures. Figure 68. ADC1 connectivity 508/1830 DocID024597 Rev 5...
Page 509: Figure 69. Adc2 Connectivity
RM0351 Analog-to-digital converters (ADC) Figure 69. ADC2 connectivity DocID024597 Rev 5 509/1830...
Page 510: Figure 70. Adc3 Connectivity
Analog-to-digital converters (ADC) RM0351 Figure 70. ADC3 connectivity 510/1830 DocID024597 Rev 5...
Page 511 RM0351 Analog-to-digital converters (ADC) 18.4.5 Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors.
Page 512 Analog-to-digital converters (ADC) RM0351 18.4.7 Single-ended and differential input channels Channels can be configured to be either single-ended input or differential input by writing into bits DIFSEL[15:1] in the ADC_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). Note that DIFSEL[18:16] are fixed to single ended channels (internal channels only) and are always read as 0.
Page 513: Figure 71. Adc Calibration
RM0351 Analog-to-digital converters (ADC) the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADC_CALFACT register (depending on single-ended or differential input calibration) The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC is disabled for extended periods, then it is recommended that a new calibration cycle is run before re-enabling the ADC.
Page 514: Figure 72. Updating The Adc Calibration Factor
Analog-to-digital converters (ADC) RM0351 CALFACT_S for single-ended input channel or bits CALFACT_D for differential input channel. Figure 72. Updating the ADC calibration factor Converting single-ended and differential analog inputs with a single ADC If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1.
Page 515: Figure 73. Mixing Single-Ended And Differential Channels
RM0351 Analog-to-digital converters (ADC) Figure 73. Mixing single-ended and differential channels 18.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 18.4.6: ADC Deep-power-down mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN)). Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a stabilization time of t before it starts converting accurately, as shown in Figure...
Page 516: Figure 74. Enabling / Disabling The Adc
Analog-to-digital converters (ADC) RM0351 Software procedure to disable the ADC Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is ongoing. If required, stop any regular and injected conversion ongoing by setting ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0. Set ADDIS=1.
Page 517 RM0351 Analog-to-digital converters (ADC) Note: There is no hardware protection to prevent these forbidden write accesses and ADC behavior may become in an unknown state. To recover from this situation, the ADC must be disabled (clear ADEN=0 as well as all the bits of ADC_CR register). 18.4.11 Channel selection (SQRx, JSQRx) There are up to 19 multiplexed channels per ADC:...
Page 518 Analog-to-digital converters (ADC) RM0351 18.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level.
Page 519 RM0351 Analog-to-digital converters (ADC) 18.4.13 Single conversion mode (CONT=0) In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either: • Setting the ADSTART bit in the ADC_CR register (for a regular channel) •...
Page 520 Analog-to-digital converters (ADC) RM0351 Note: To convert a single channel, program a sequence with a length of 1. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Injected channels cannot be converted continuously.
Page 521: Figure 75. Analog To Digital Conversion Time
RM0351 Analog-to-digital converters (ADC) 18.4.16 Timing The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [ 2.5 + 12.5 ] x T CONV...
Page 522: Figure 76. Stopping Ongoing Regular Conversions
Analog-to-digital converters (ADC) RM0351 Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used). Figure 76. Stopping ongoing regular conversions Figure 77. Stopping ongoing regular and injected conversions 522/1830 DocID024597 Rev 5...
Page 523: Table 105. Configuring The Trigger Polarity For Regular External Triggers
RM0351 Analog-to-digital converters (ADC) 18.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity.
Page 524: Table 107. Adc1, Adc2 And Adc3 - External Triggers For Regular Channels
Analog-to-digital converters (ADC) RM0351 Note: The regular trigger selection cannot be changed on-the-fly. The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 18.4.21: Queue of context for injected conversions on page 528 Each ADC master shares the same input triggers with its ADC slave as described in Figure Figure 78.
Page 525: Table 108. Adc1, Adc2 And Adc3 - External Trigger For Injected Channels
RM0351 Analog-to-digital converters (ADC) Table 107. ADC1, ADC2 and ADC3 - External triggers for regular channels (continued) Name Source Type EXTSEL[3:0] EXT10 TIM1_TRGO2 Internal signal from on-chip timers 1010 EXT11 TIM2_TRGO Internal signal from on-chip timers 1011 EXT12 TIM4_TRGO Internal signal from on-chip timers 1100 EXT13 TIM6_TRGO...
Page 526 Analog-to-digital converters (ADC) RM0351 reset and the injected channel sequence switches are launched (all the injected channels are converted once). Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence.
Page 527: Figure 79. Injected Conversion Latency
RM0351 Analog-to-digital converters (ADC) Figure 79. Injected conversion latency 1. The maximum latency value can be found in the electrical characteristics of the STM32L4x5/STM32L4x6 datasheet. 18.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADC_CFGR register. It is used to convert a short sequence (sub-group) of n conversions (n ≤...
Page 528 Analog-to-digital converters (ADC) RM0351 – • DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11 – 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10 and 11. Each conversion generates an EOC event and the last one also generates an EOS event.
Page 529 RM0351 Analog-to-digital converters (ADC) All the parameters of the context are defined into a single register ADC_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters: • The JSQR register can be written at any moment even when injected conversions are ongoing.
Page 530: Figure 80. Example Of Jsqr Queue Of Context (Sequence Change)
Analog-to-digital converters (ADC) RM0351 Behavior when changing the trigger or sequence context Figure 80 Figure 81 show the behavior of the context Queue when changing the sequence or the triggers. Figure 80. Example of JSQR queue of context (sequence change) 1.
Page 531: Figure 82. Example Of Jsqr Queue Of Context With Overflow Before Conversion
RM0351 Analog-to-digital converters (ADC) Queue of context: Behavior when a queue overflow occurs Figure 82 Figure 83 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 82. Example of JSQR queue of context with overflow before conversion 1.
Page 532: Figure 84. Example Of Jsqr Queue Of Context With Empty Queue (Case Jqm=0)
Analog-to-digital converters (ADC) RM0351 It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). •...
Page 533: Figure 85. Example Of Jsqr Queue Of Context With Empty Queue (Case Jqm=1)
RM0351 Analog-to-digital converters (ADC) Figure 85. Example of JSQR queue of context with empty queue (case JQM=1) 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Flushing the queue of context The figures below show the behavior of the context Queue in various situations when the queue is flushed.
Page 534: Figure 87. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=0). Case When Jadstp Occurs During An Ongoing Conversion And A New
Analog-to-digital converters (ADC) RM0351 Figure 87. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 88.
Page 535: Figure 89. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=1)
RM0351 Analog-to-digital converters (ADC) Figure 89. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 90.
Page 536: Figure 91. Flushing Jsqr Queue Of Context By Setting Addis=1 (Jqm=1)
Analog-to-digital converters (ADC) RM0351 Figure 91. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1) 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Queue of context: Starting the ADC with an empty queue The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized.
Page 537: Table 109. Tsar Timings Depending On Resolution
RM0351 Analog-to-digital converters (ADC) Table 109. T timings depending on resolution (ADC clock cycles) CONV (ns) at (ns) at CONV (with Sampling Time= (bits) =80 MHz =80 MHz (ADC clock cycles) 2.5 ADC clock cycles) 12.5 ADC clock cycles 156.25 ns 15 ADC clock cycles 187.5 ns 10.5 ADC clock cycles 131.25 ns...
Page 538: Figure 92. Single Conversions Of A Sequence, Software Trigger
Analog-to-digital converters (ADC) RM0351 18.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers) Figure 92. Single conversions of a sequence, software trigger 1. EXTEN=0x0, CONT=0 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 93. Continuous conversion of a sequence, software trigger 1.
Page 539: Figure 94. Single Conversions Of A Sequence, Hardware Trigger
RM0351 Analog-to-digital converters (ADC) Figure 94. Single conversions of a sequence, hardware trigger 1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. Figure 95. Continuous conversions of a sequence, hardware trigger 1.
Page 540: Table 110. Offset Computation Versus Data Resolution
Analog-to-digital converters (ADC) RM0351 Figure Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in Figure 98 Figure Note: Left-alignment is not supported in oversampling mode.
Page 541: Figure 96. Right Alignment (Offset Disabled, Unsigned Value)
RM0351 Analog-to-digital converters (ADC) Figure 96. Right alignment (offset disabled, unsigned value) Figure 97. Right alignment (offset enabled, signed value) DocID024597 Rev 5 541/1830...
Page 542: Figure 98. Left Alignment (Offset Disabled, Unsigned Value)
Analog-to-digital converters (ADC) RM0351 Figure 98. Left alignment (offset disabled, unsigned value) Figure 99. Left alignment (offset enabled, signed value) 542/1830 DocID024597 Rev 5...
Page 543: Figure 100. Example Of Overrun (Ovr)
RM0351 Analog-to-digital converters (ADC) ADC overrun (OVR, OVRMOD) The overrun flag (OVR) notifies of a buffer overrun event, when the regular converted data was not read (by the CPU or the DMA) before new converted data became available. The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE=1.
Page 544 Analog-to-digital converters (ADC) RM0351 Managing conversions without using the DMA and without overrun It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software.
Page 545 RM0351 Analog-to-digital converters (ADC) DMA circular mode (DMACFG=1) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream.
Page 546 Analog-to-digital converters (ADC) RM0351 Note: This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTART to re-start a conversion: it is up to the software to read the data before launching a new conversion. No delay is inserted between conversions of different groups (a regular conversion followed by an injected conversion or conversely): •...
Page 547: Figure 101. Autodly=1, Regular Conversion In Continuous Mode, Software Trigger
RM0351 Analog-to-digital converters (ADC) Figure 101. AUTODLY=1, regular conversion in continuous mode, software trigger 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3 3. Injected configuration DISABLED Figure 102. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0;...
Page 548: (Discen=1, Jdiscen=1)
Analog-to-digital converters (ADC) RM0351 Figure 103. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3. 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6 548/1830 DocID024597 Rev 5...
Page 549: Figure 104. Autodly=1, Regular Continuous Conversions Interrupted By Injected Conversions
RM0351 Analog-to-digital converters (ADC) Figure 104. AUTODLY=1, regular continuous conversions interrupted by injected conversions 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 Figure 105. AUTODLY=1 in auto- injected mode (JAUTO=1) 1.
Page 550: Table 111. Analog Watchdog Channel Selection
Analog-to-digital converters (ADC) RM0351 18.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 106. Analog watchdog’s guarded area AWDx flag and interrupt An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the ADC_IER register (x=1,2,3).
Page 551: Table 112. Analog Watchdog 1 Comparison
RM0351 Analog-to-digital converters (ADC) These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).
Page 552: Figure 107. Adcy_Awdx_Out Signal Generation (On All Regular Channels)
Analog-to-digital converters (ADC) RM0351 ADCy_AWDx_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCy_AWDx_OUT signal as ETR.
Page 553: Figure 108. Adcy_Awdx_Out Signal Generation (Awdx Flag Not Cleared By Software)
RM0351 Analog-to-digital converters (ADC) Figure 108. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) Figure 109. ADCy_AWDx_OUT signal generation (on a single regular channel) Figure 110. ADCy_AWDx_OUT signal generation (on all injected channels) DocID024597 Rev 5 553/1830...
Page 554: Figure 111. 20-Bit To 16-Bit Result Truncation
Analog-to-digital converters (ADC) RM0351 18.4.30 Oversampler The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: –...
Page 555: Table 114. Maximum Output Results Versus N And M (Gray Cells Indicate Truncation)
RM0351 Analog-to-digital converters (ADC) Table 114. Maximum output results versus N and M (gray cells indicate truncation) No-shift 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Over shift shift shift shift shift shift shift shift sampling Raw data OVSS = OVSS = OVSS = OVSS =...
Page 556: Figure 113. Triggered Regular Oversampling Mode (Trovs Bit = 1)
Analog-to-digital converters (ADC) RM0351 Analog watchdog The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference: – the RES[1:0] bits are ignored, comparison is always done on using the full 12-bit values HT[11:0] and LT[11:0] – the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADC_DR[15:4] Note:...
Page 557: Figure 114. Regular Oversampling Modes (4X Ratio)
RM0351 Analog-to-digital converters (ADC) Oversampling regular channels only The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion: • in continued mode, the accumulation re-starts from the last valid data (prior to the conversion abort request due to the injected trigger).
Page 558: Figure 115. Regular And Injected Oversampling Modes Used Simultaneously
Analog-to-digital converters (ADC) RM0351 Oversampling regular and Injected channels It is possible to have both ROVSE and JOVSE bits set. In this case, the regular oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on Figure 115 below.
Page 559: Table 115. Oversampler Operating Modes Summary
RM0351 Analog-to-digital converters (ADC) Auto-injected mode It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations are not supported.
Page 560 Analog-to-digital converters (ADC) RM0351 18.4.31 Dual ADC modes In devices with two ADCs or more, dual ADC modes can be used (see Figure 118): • ADC1 and ADC2 can be used together in dual mode (ADC1 is master) In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADC_CCR register.
Page 561: Figure 118. Dual Adc Block Diagram (1)
RM0351 Analog-to-digital converters (ADC) Figure 118. Dual ADC block diagram External triggers also exist on slave ADC but are not shown for the purposes of this diagram. The ADC common data register (ADC_CDR) contains both the master and slave ADC regular converted data. DocID024597 Rev 5 561/1830...
Page 562: Figure 119. Injected Simultaneous Mode On 4 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0351 Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL[3:0] bits in the ADC_JSQR register).
Page 563 RM0351 Analog-to-digital converters (ADC) ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels.
Page 564: Figure 120. Regular Simultaneous Mode On 16 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0351 Figure 120. Regular simultaneous mode on 16 channels: dual ADC mode If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a regular trigger event to occur (“n” is defined by DISCNUM). This mode can be combined with AUTDLY mode: •...
Page 565 RM0351 Analog-to-digital converters (ADC) complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). • The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase.
Page 566: Figure 121. Interleaved Mode On 1 Channel In Continuous Conversion Mode: Dual Adc Mode
Analog-to-digital converters (ADC) RM0351 Figure 121. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode Figure 122. Interleaved mode on 1 channel in single conversion mode: dual ADC mode If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the regular sequence require a regular trigger event to occur.
Page 567: Figure 123. Interleaved Conversion With Injection
RM0351 Analog-to-digital converters (ADC) Figure 123. Interleaved conversion with injection Alternate trigger mode This mode is selected by programming bits DUAL[4:0] = 01001. This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC. This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0.
Page 568: Figure 124. Alternate Trigger: Injected Group Of Each Adc
Analog-to-digital converters (ADC) RM0351 Figure 124. Alternate trigger: injected group of each ADC Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion.
Page 569: Figure 125. Alternate Trigger: 4 Injected Channels (Each Adc) In Discontinuous Mode
RM0351 Analog-to-digital converters (ADC) Figure 125. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode Combined regular/injected simultaneous mode This mode is selected by programming bits DUAL[4:0] = 00001. It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group.
Page 570: Figure 126. Alternate + Regular Simultaneous
Analog-to-digital converters (ADC) RM0351 Figure 126. Alternate + regular simultaneous If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 127 shows the behavior in this case (note that the 6th trigger is ignored because the associated alternate conversion is not complete).
Page 571: Figure 128. Interleaved Single Channel Ch0 With Injected Sequence Ch11, Ch12
RM0351 Analog-to-digital converters (ADC) Figure 128. Interleaved single channel CH0 with injected sequence CH11, CH12 Figure 129. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first Figure 130. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for...
Page 572: Figure 131. Dma Requests In Regular Simultaneous Mode When Mdma=0B00
Analog-to-digital converters (ADC) RM0351 regular simultaneous mode when MDMA=0b00). Figure 131. DMA Requests in regular simultaneous mode when MDMA=0b00 In simultaneous regular and interleaved modes, it is also possible to save one DMA channel and transfer both data using a single DMA channel. For this MDMA bits must be configured in the ADC_CCR register: •...
Page 573: Figure 132. Dma Requests In Regular Simultaneous Mode When Mdma=0B10
RM0351 Analog-to-digital converters (ADC) Figure 132. DMA requests in regular simultaneous mode when MDMA=0b10 Figure 133. DMA requests in interleaved mode when MDMA=0b10 DocID024597 Rev 5 573/1830...
Page 574 Analog-to-digital converters (ADC) RM0351 Note: When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. •...
Page 575 To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area.
Page 576: Figure 134. Temperature Sensor Channel Block Diagram
Analog-to-digital converters (ADC) RM0351 Figure 134. Temperature sensor channel block diagram 1. The CH17SEL bit must be set to enable the conversion of the temperature sensor voltage V Reading the temperature To use the sensor: Select the ADC1_IN17 or ADC3_IN17 input channels. Program with the appropriate sampling time (refer to electrical characteristics section of the device datasheet).
Page 577: Figure 135. Vbat Channel Block Diagram
RM0351 Analog-to-digital converters (ADC) Refer to the electrical characteristics of the device datasheet for the sampling time value to be applied when converting the V /3 voltage. The figure below shows the block diagram of the V sensing feature. Figure 135. V channel block diagram 1.
Page 578 Analog-to-digital converters (ADC) RM0351 Calculating the actual V voltage using the internal reference voltage The V power supply voltage applied to the microcontroller may be subject to variation or not precisely known. The embedded internal voltage reference (V ) and its calibration REFINT data acquired by the ADC during the manufacturing process at V = 3.0 V can be used to...
Page 579: Table 116. Adc Interrupts Per Each Adc
RM0351 Analog-to-digital converters (ADC) 18.5 ADC interrupts For each ADC, an interrupt can be generated: • after ADC power-up, when the ADC is ready (flag ADRDY) • on the end of any conversion for regular groups (flag EOC) • on the end of a sequence of conversion for regular groups (flag EOS) •...
Page 580 Analog-to-digital converters (ADC) RM0351 18.6 ADC registers (for each ADC) Refer to Section 1.1 on page 67 for a list of abbreviations used in register descriptions. 18.6.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 581 RM0351 Analog-to-digital converters (ADC) Bit 5 JEOC: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register 0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
Page 582 Analog-to-digital converters (ADC) RM0351 18.6.2 ADC interrupt enable register (ADC_IER) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3 AWD2 AWD1 EOSMP ADRDY Res. Res. Res.
Page 583 RM0351 Analog-to-digital converters (ADC) Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no regular conversion is ongoing).
Page 584 Analog-to-digital converters (ADC) RM0351 18.6.3 ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x2000 0000 ADCA DEEP ADVREG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LDIF Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 585 RM0351 Analog-to-digital converters (ADC) Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured.
Page 586 Analog-to-digital converters (ADC) RM0351 Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).
Page 587 RM0351 Analog-to-digital converters (ADC) 18.6.4 ADC configuration register (ADC_CFGR) Address offset: 0x0C Reset value: 0x8000 0000 JAWD1 AWD1 AWD1S JDISC DISC JQDIS AWD1CH[4:0] JAUTO DISCNUM[2:0] DFSD Res. CONT EXTEN[1:0] EXTSEL[3:0] ALIGN RES[1:0] MCFG Bit 31 JQDIS: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : 0: Injected Queue enabled 1: Injected Queue disabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures...
Page 588 Analog-to-digital converters (ADC) RM0351 Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on regular channels 1: Analog watchdog 1 enabled on regular channels Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 589 RM0351 Analog-to-digital converters (ADC) Bit 16 DISCEN: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. 0: Discontinuous mode for regular channels disabled 1: Discontinuous mode for regular channels enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.
Page 590 Analog-to-digital converters (ADC) RM0351 Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: 0000: Event 0 0001: Event 1 0010: Event 2 0011: Event 3 0100: Event 4 0101: Event 5 0110: Event 6...
Page 591 RM0351 Analog-to-digital converters (ADC) Bit 2 DFSDMCFG: DFSDM mode configuration This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN=0. 0: DFSDM mode disabled 1: DFSDM mode enabled Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0.
Page 592 Analog-to-digital converters (ADC) RM0351 Bits 31:11 Reserved, must be kept at reset value. Bit 10 ROVSM: Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. 0: Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted...
Page 593 RM0351 Analog-to-digital converters (ADC) Bits 4:2 OVSR[2:0]: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 256x Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 594 Analog-to-digital converters (ADC) RM0351 Bits 31 SMPPLUS: Addition of one clock cycle to the sampling time. 1: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers. 0: The sampling time remains set to 2.5 ADC clock cycles remains To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0.
Page 595 RM0351 Analog-to-digital converters (ADC) 18.6.8 ADC watchdog threshold register 1 (ADC_TR1) Address offset: 0x20 Reset value: 0x0FFF 0000 Res. Res. Res. Res. HT1[11:0] Res. Res. Res. Res. LT1[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1.
Page 596 Analog-to-digital converters (ADC) RM0351 Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to Section 18.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 597 RM0351 Analog-to-digital converters (ADC) 18.6.11 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. SQ4[4:0] Res. SQ3[4:0] Res. SQ2[4] SQ2[3:0] Res. SQ1[4:0] Res. Res. L[3:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 4th in the regular conversion sequence.
Page 598 Analog-to-digital converters (ADC) RM0351 18.6.12 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x34 Reset value: 0x0000 0000 Res. Res. Res. SQ9[4:0] Res. SQ8[4:0] Res. SQ7[4] SQ7[3:0] Res. SQ6[4:0] Res. SQ5[4:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 9th in the regular conversion sequence.
Page 599 RM0351 Analog-to-digital converters (ADC) 18.6.13 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. SQ14[4:0] Res. SQ13[4:0] Res. SQ12[4] SQ12[3:0] Res. SQ11[4:0] Res. SQ10[4:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 14th in the regular conversion sequence.
Page 600 Analog-to-digital converters (ADC) RM0351 18.6.14 ADC regular sequence register 4 (ADC_SQR4) Address offset: 0x3C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SQ16[4:0] Res.
Page 601 RM0351 Analog-to-digital converters (ADC) 18.6.16 ADC injected sequence register (ADC_JSQR) Address offset: 0x4C Reset value: 0x0000 0000 Res. JSQ4[4:0] Res. JSQ3[4:0] Res. JSQ2[4:2] JSQ2[1:0] Res. JSQ1[4:0] JEXTEN[1:0] JEXTSEL[3:0] JL[1:0] Bit 31 Reserved, must be kept at reset value. Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence These bits are written by software with the channel number (0..18) assigned as the 4th in the injected conversion sequence.
Page 602 Analog-to-digital converters (ADC) RM0351 Bits 7:6 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled 00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge...
Page 603 RM0351 Analog-to-digital converters (ADC) Bit 31 OFFSETy_EN: Offset y Enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]. Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 604 Analog-to-digital converters (ADC) RM0351 18.6.19 ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR) Address offset: 0xA0 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD2CH[18:16] AWD2CH[15:0] Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection These bits are set and cleared by software.
Page 605 RM0351 Analog-to-digital converters (ADC) 18.6.21 ADC Differential mode Selection Register (ADC_DIFSEL) Address offset: 0xB0 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DIFSEL[18:16] DIFSEL[15:0] Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 DIFSEL[18:16]: Differential mode for channels 18 to 16.
Page 606 Analog-to-digital converters (ADC) RM0351 Bits 31:23 Reserved, must be kept at reset value. Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors.
Page 607 RM0351 Analog-to-digital converters (ADC) Bits 31:27 Reserved, must be kept at reset value. Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
Page 608 Analog-to-digital converters (ADC) RM0351 Bit 2 EOC_MST: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
Page 609 RM0351 Analog-to-digital converters (ADC) Bits 21:18 PRESC[3:0]: ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. 0000: input ADC clock not divided 0001: input ADC clock divided by 2 0010: input ADC clock divided by 4 0011: input ADC clock divided by 6...
Page 610: Table 117. Delay Bits Versus Adc Resolution
Analog-to-digital converters (ADC) RM0351 Bit 12 Reserved, must be kept at reset value. Bits 11:8 DELAY: Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 117 for the value of ADC resolution versus DELAY bits values.
Page 611: Table 118. Adc Global Register Map
RM0351 Analog-to-digital converters (ADC) 18.7.3 ADC common regular data register for dual mode (ADC_CDR) Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 RDATA_SLV[15:0] RDATA_MST[15:0] Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC.
Page 612: Table 119. Adc Register Map And Reset Values For Each Adc
Analog-to-digital converters (ADC) RM0351 Table 119. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) Offset Register ADC_ISR 0x00 Reset value ADC_IER 0x04 Reset value ADC_CR 0x08 Reset value DISCNUM EXTSEL AWD1CH[4:0] ADC_CFGR [2:0] [3:0]...
Page 613 RM0351 Analog-to-digital converters (ADC) Table 119. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register 0x44- Reserved Res. 0x48 JEXTSEL JSQ4[4:0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] JL[1:0] ADC_JSQR [3:0] 0x4C Reset value 0x50- Reserved Res.
Page 614: Common Registers) Offset =0X300)
Analog-to-digital converters (ADC) RM0351 Table 119. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register DIFSEL[18:0] ADC_DIFSEL 0xB0 Reset value CALFACT_D[6:0] CALFACT_S[6:0] ADC_CALFACT 0xB4 Reset value Table 120. ADC register map and reset values (master and slave ADC common registers) offset =0x300) Offset Register...
Page 615 RM0351 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 19.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 616 Digital-to-analog converter (DAC) RM0351 19.3 DAC functional description 19.3.1 DAC block diagram Figure 137. DAC channel block diagram 1. The output mode controller switches between the normal mode in buffer/unbuffered configuration and the Sample and Hold mode. The DAC includes: •...
Page 617: Table 121. Dac Pins
RM0351 Digital-to-analog converter (DAC) The DAC includes up to two separate output channels. Each output channel can be connected to on-chip peripherals such as COMP, OPAMP and ADC. In this case, the DAC output channel can be disconnected from the DAC_OUTx output pin and the corresponding GPIO can be used for another purpose.
Page 618: Figure 138. Data Registers In Single Dac Channel Mode
Digital-to-analog converter (DAC) RM0351 Figure 138. Data registers in single DAC channel mode • Dual DAC channels (when available), there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –...
Page 619: Table 122. Dac Trigger Selection
RM0351 Digital-to-analog converter (DAC) Figure 140. Timing diagram for conversion with trigger disabled TEN = 0 19.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation: ×...
Page 620 Digital-to-analog converter (DAC) RM0351 Table 122. DAC trigger selection (continued) Source Type TSELx[2:0] EXTI9 External pin SWTRIG Software control bit 19.3.7 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set.
Page 621: Figure 141. Dac Lfsr Register Calculation Algorithm
RM0351 Digital-to-analog converter (DAC) Figure 141. DAC LFSR register calculation algorithm The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then transferred into the DAC_DORx register.
Page 622: Figure 143. Dac Triangle Wave Generation
Digital-to-analog converter (DAC) RM0351 maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on. It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 143.
Page 623: Table 123. Sample And Refresh Timings
RM0351 Digital-to-analog converter (DAC) To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register should be: • 010: DAC is connected to the external pin • 011: DAC is connected to on-chip peripherals Sample and Hold mode In sample and Hold mode, the DAC core converts data on a triggered conversion, then, holds the converted voltage on a capacitor.
Page 624 Digital-to-analog converter (DAC) RM0351 Note: In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time. The tolerated voltage drop during the hold phase “Vd”...
Page 625: Table 124. Channel Output Modes Summary
RM0351 Digital-to-analog converter (DAC) Figure 145. DAC sample and hold mode phase diagram Like in normal mode, the sample and hold mode has different configurations. To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register should be: • 100: DAC is connected to the external pin •...
Page 626 Digital-to-analog converter (DAC) RM0351 Table 124. Channel output modes summary (continued) MODEx[2:0] Mode Buffer Output connections Connected to external pin Enabled Connected to external pin and to on chip peripherals (ex, comparators) Sample & hold mode Connected to external pin and to on chip peripherals (ex, comparators) Disabled Connected to on chip peripherals (ex, comparators) 19.3.11...
Page 627 RM0351 Digital-to-analog converter (DAC) If the DAC channel is active, Write 0 to ENx bit in DAC_CR to disable the channel. Select a mode where the buffer is enabled, by writing to DACx_MCR register, MODEx[2:0] = 000b or 001b or 100b or 101b, Start the DAC channelx calibration, by setting the CENx bit in DACx_CR register to 1, Apply a trimming algorithm: Write a code into OTRIMx[4:0] bits, starting by 00000b...
Page 628 Digital-to-analog converter (DAC) RM0351 When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: •...
Page 629 RM0351 Digital-to-analog converter (DAC) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
Page 630 Digital-to-analog converter (DAC) RM0351 Simultaneous trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 631 RM0351 Digital-to-analog converter (DAC) Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 632: Table 125. Effect Of Low-Power Modes On Dac
Digital-to-analog converter (DAC) RM0351 19.4 DAC low-power modes Table 125. Effect of low-power modes on DAC Mode Description Sleep No effect, DAC used with DMA Low-power run No effect. Low-power sleep No effect. DAC used with DMA. DAC remains active with a static value, if sample and hold mode is Stop 0 / Stop 1 selected using LSI clock The DAC registers content is kept.
Page 633 RM0351 Digital-to-analog converter (DAC) 19.5 DAC registers Refer to Section 1 on page 67 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 19.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU Res.
Page 634 Digital-to-analog converter (DAC) RM0351 Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event...
Page 635 RM0351 Digital-to-analog converter (DAC) Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 636 Digital-to-analog converter (DAC) RM0351 19.5.2 DAC software trigger register (DAC_SWTRGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 637 RM0351 Digital-to-analog converter (DAC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res. Res. Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
Page 638 Digital-to-analog converter (DAC) RM0351 19.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[11:0] Res. Res. Res.
Page 639 RM0351 Digital-to-analog converter (DAC) Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
Page 640 Digital-to-analog converter (DAC) RM0351 19.5.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DOR[11:0] Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
Page 641 RM0351 Digital-to-analog converter (DAC) Bit 31 BWST2: DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete.
Page 642 Digital-to-analog converter (DAC) RM0351 Bits 31:21 Reserved, must be kept at reset value. Bits 20:16 OTRIM2[4:0]: DAC Channel 2 offset trimming value Bits 15:5 Reserved, must be kept at reset value. Bits 4:0 OTRIM1[4:0]: DAC Channel 1 offset trimming value 19.5.16 DAC mode control register (DAC_MCR) Address offset: 0x3C...
Page 643 RM0351 Digital-to-analog converter (DAC) Bits 18:16 MODE2[2:0]: DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored.
Page 644 Digital-to-analog converter (DAC) RM0351 Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 TSAMPLE1[9:0]: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.
Page 645 RM0351 Digital-to-analog converter (DAC) Bits 25:16 THOLD2[9:0]: DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI Bits 15:10 Reserved, must be kept at reset value. Bits 9:0 THOLD1[9:0]: DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI Note: These bits can be written only when the DAC channel is disabled and in normal operating...
Page 646: Table 126. Dac Register Map And Reset Values
Digital-to-analog converter (DAC) RM0351 19.5.21 DAC register map Table 126 summarizes the DAC registers. Table 126. DAC register map and reset values Offset Register DAC_CR MAMP2[3:0] MAMP1[3:0] 0x00 Reset value DAC_ SWTRGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1...
Page 647 RM0351 Digital-to-analog converter (DAC) Table 126. DAC register map and reset values Offset Register DAC_CCR OTRIM2[4:0] OTRIM1[4:0] 0x38 Reset value X X X X MODE2 MODE1 DAC_MCR [2:0] [2:0] 0x3C Reset value DAC_SHSR TSAMPLE1[9:0] 0x40 Reset value DAC_SHSR TSAMPLE2[9:0] 0x44 Reset value DAC_SHHR THOLD2[9:0]...
Page 648 Digital camera interface (DCMI) RM0351 Digital camera interface (DCMI) This section applies to STM32L496xx/4A6xx devices. 20.1 DCMI introduction The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
Page 649: Figure 146.Dcmi Block Diagram
RM0351 Digital camera interface (DCMI) The data flow is synchronized either by hardware using the optional DCMI_HSYNC (horizontal synchronization) and DCMI_VSYNC (vertical synchronization) signals or by synchronization codes embedded in the data flow. 20.4.1 DCMI block diagram Figure 146 shows the DCMI block diagram. Figure 146.DCMI block diagram Figure 147.Top-level block diagram 20.4.2...
Page 650: Table 127. Dcmi External Signals
Digital camera interface (DCMI) RM0351 The camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the EDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused input pins must be connected to ground. shows the DCMI pins.
Page 651: Table 128. Positioning Of Captured Data Bytes In 32-Bit Words (8-Bit Width)
RM0351 Digital camera interface (DCMI) Table 128.Positioning of captured data bytes in 32-bit words (8-bit width) Byte address 31:24 23:16 15:8 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 10-bit data When EDM[1:0] in DCMI_CR are programmed to “01”, the camera interface captures 10-bit data at its input DCMI_D[0..9] and stores them as the 10 least significant bits of a 16-bit word.
Page 652: Table 131. Positioning Of Captured Data Bytes In 32-Bit Words (14-Bit Width)
Digital camera interface (DCMI) RM0351 Table 131.Positioning of captured data bytes in 32-bit words (14-bit width) Byte address 31:30 29:16 15:14 13:0 [13:0] [13:0] [13:0] [13:0] 20.4.4 Synchronization The digital camera interface supports embedded or hardware (DCMI_HSYNC and DCMI_VSYNC) synchronization. When embedded synchronization is used, it is up to the digital camera module to make sure that the 0x00 and 0xFF values are used ONLY for synchronization (not in data).
Page 653 RM0351 Digital camera interface (DCMI) capture is enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the deactivation of the DCMI_VSYNC signal (next start of frame). Transfer can then be continuous, with successive frames transferred by DMA to successive buffers or the same/circular buffer.
Page 654: Figure 150.Frame Capture Waveforms In Snapshot Mode
Digital camera interface (DCMI) RM0351 detect a frame/line start or frame/line end. This means that there can be different codes for the frame/line start and frame/line end with the unmasked bit position remaining the same. Example FS = 0xA5 Unmask code for FS = 0x10 In this case the frame start code is embedded in the bit 4 of the frame start code.
Page 655: Figure 151.Frame Capture Waveforms In Continuous Grab Mode
RM0351 Digital camera interface (DCMI) Figure 151.Frame capture waveforms in continuous grab mode 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. In continuous grab mode, you can configure the FCRC bits in DCMI_CR to grab all pictures, every second picture or one out of four pictures to decrease the frame capture rate.
Page 656: Figure 153.Data Capture Waveforms
Digital camera interface (DCMI) RM0351 If the VSYNC signal goes active before the number of lines is specified in the DCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated when enabled. Figure 153.Data capture waveforms 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2.
Page 657: Table 132.Data Storage In Monochrome Progressive Video Format
RM0351 Digital camera interface (DCMI) 20.5 Data format description 20.5.1 Data formats Three types of data are supported: 8-bit progressive video: either monochrome or raw Bayer format ● YCbCr 4:2:2 progressive video ● RGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits ●...
Page 658: Table 133.Data Storage In Rgb Progressive Video Format
Digital camera interface (DCMI) RM0351 20.5.3 RGB format Characteristics: Raster format ● ● Interleaved: one buffer: R, G & B interleaved: BRGBRGBRG, etc. ● Optimized for display output ● The RGB planar format is compatible with standard OS frame buffer display formats. Only 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported.
Page 659: Table 135. Data Storage In Ycbcr Progressive Video Format - Y Extraction Mode
RM0351 Digital camera interface (DCMI) pixel , encoded in 8 bits, is stored as shown in Table 135. The result is a monochrome image having the same resolution as the original YCbCr data. Table 135.Data storage in YCbCr progressive video format - Y extraction mode Byte address 31:24 23:16...
Page 660 Digital camera interface (DCMI) RM0351 Bits 31:21 Reserved, must be kept at reset value. Bit 20 OELS: Odd/Even Line Select (Line Select Start) This bit works in conjunction with LSM field (LSM = 1) 0: Interface captures first line after the frame start, second one being dropped 1: Interface captures second line from the frame start, first one being dropped Bit 19 LSM: Line Select mode 0: Interface captures all received lines...
Page 661 RM0351 Digital camera interface (DCMI) Bit 6 HSPOL: Horizontal synchronization polarity This bit indicates the level on the DCMI_HSYNC pin when the data are not valid on the parallel interface. 0: DCMI_HSYNC active low 1: DCMI_HSYNC active high Bit 5 PCKPOL: Pixel clock polarity This bit configures the capture edge of the pixel clock 0: Falling edge active.
Page 662 Digital camera interface (DCMI) RM0351 20.7.2 DCMI status register (DCMI_SR) Address offset: 0x04 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bits 31:3 Reserved, must be kept at reset value. Bit 2 FNE: FIFO not empty This bit gives the status of the FIFO 1: FIFO contains valid data...
Page 663 RM0351 Digital camera interface (DCMI) 20.7.3 DCMI raw interrupt status register (DCMI_RIS) Address offset: 0x08 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DCMI_RIS gives the raw interrupt status and is accessible in read only.
Page 664 Digital camera interface (DCMI) RM0351 20.7.4 DCMI interrupt enable register (DCMI_IER) Address offset: 0x0C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw The DCMI_IER register is used to enable interrupts.
Page 665 RM0351 Digital camera interface (DCMI) 20.7.5 DCMI masked interrupt status register (DCMI_MIS) This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
Page 666 Digital camera interface (DCMI) RM0351 20.7.6 DCMI interrupt clear register (DCMI_ICR) Address offset: 0x14 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 w w w w w The DCMI_ICR register is write-only.
Page 667 RM0351 Digital camera interface (DCMI) 20.7.7 DCMI embedded synchronization code register (DCMI_ESCR) Address offset: 0x18 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 FEC: Frame end delimiter code This byte specifies the code of the frame end delimiter.
Page 668 Digital camera interface (DCMI) RM0351 20.7.8 DCMI embedded synchronization unmask register (DCMI_ESUR) Address offset: 0x1C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 FEU: Frame end delimiter unmask This byte specifies the mask to be applied to the code of the frame end delimiter.
Page 669 RM0351 Digital camera interface (DCMI) 20.7.9 DCMI crop window start (DCMI_CWSTRT) Address offset: 0x20 Reset value: 0x0000 0x0000 28 27 26 25 24 23 22 21 20 19 18 17 16 13 12 11 10 Res. Res. Res. VST[12:0 Res. Res. HOFFCNT[13:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...
Page 670 Digital camera interface (DCMI) RM0351 20.7.11 DCMI data register (DCMI_DR) Address offset: 0x28 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Byte3 Byte2 Byte1 Byte0...
Page 671: Table 137.Dcmi Register Map And Reset Values
RM0351 Digital camera interface (DCMI) 20.7.12 DCMI register map Table 137 summarizes the DCMI registers. Table 137.DCMI register map and reset values Offset Register DCMI_CR EDM FCRC 0x00 Reset value DCMI_SR 0x04 Reset value DCMI_RIS 0x08 Reset value DCMI_IER 0x0C Reset value DCMI_MIS 0x10...
Page 672: Table 138. Vrefbuf Buffer Modes
Voltage reference buffer (VREFBUF) RM0351 Voltage reference buffer (VREFBUF) 21.1 Introduction The STM32L4x5/STM32L4x6 devices embed a voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. When the VREF+ pin is double-bonded with VDDA pin in a package, the voltage reference buffer is not available and must be kept disable (refer to datasheet for packages pinout description).
Page 673 RM0351 Voltage reference buffer (VREFBUF) ENVR Bits 31:4 Reserved, must be kept at reset value. Bit 3 VRR: Voltage reference buffer ready 0: the voltage reference buffer output is not ready. 1: the voltage reference buffer output reached the requested level. Bit 2 VRS: Voltage reference scale This bit selects the value generated by the voltage reference buffer.
Page 674: Table 139. Vrefbuf Register Map And Reset Values
Voltage reference buffer (VREFBUF) RM0351 21.3.3 VREFBUF register map The following table gives the VREFBUF register map and the reset values. Table 139. VREFBUF register map and reset values Offset Register VREFBUF_CSR 0x00 Reset value VREFBUF_CCR TRIM[5:0] 0x04 Reset value Refer to Section 2.2.2 on page 75 for the register boundary addresses.
Page 675 RM0351 Comparator (COMP) Comparator (COMP) 22.1 Introduction The device embeds two ultra-low power comparators COMP1, and COMP2 The comparators can be used for a variety of functions including: • Wake-up from low-power mode triggered by an analog signal, • Analog signal conditioning, •...
Page 676: Table 140. Comp1 Input Plus Assignment
Comparator (COMP) RM0351 22.3 COMP functional description 22.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 155: Comparators block diagram. Figure 155. Comparators block diagram 22.3.2 COMP pins and internal signals The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.
Page 677: Table 142. Comp2 Input Plus Assignment
RM0351 Comparator (COMP) Table 141. COMP1 input minus assignment (continued) COMP1_INM COMP1_INMSEL[2:0] ¾ V REFINT REFINT DAC Channel1 DAC Channel2 Table 142. COMP2 input plus assignment COMP2_INP COMP2_INPSEL Table 143. COMP2 input minus assignment COMP2_INM COMP2_INMSEL[2:0] ¼ V REFINT ½ V REFINT ¾...
Page 678: Figure 156. Window Mode
Comparator (COMP) RM0351 For this purpose, the comparator control and status registers can be write-protected (read- only). Once the programming is completed, the COMPxLOCK bit can be set to 1. This causes the whole register to become read-only, including the COMPxLOCK bit. The write protection can only be reset by a MCU reset.
Page 679: Figure 157. Comparator Hysteresis
RM0351 Comparator (COMP) Figure 157. Comparator hysteresis 22.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes).It consists of a selection of a blanking window which is a timer output compare signal.
Page 680: Table 144. Comparator Behavior In The Low Power Modes
Comparator (COMP) RM0351 22.3.8 COMP power and speed modes COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application. The bits COMPx_PWR_MODE[1:0] in COMPx_CSR registers can be programmed as follows: 00: High speed / full power 01 or 10: Medium speed / medium power 11: Low speed / ultra-low-power...
Page 681: Table 145. Interrupt Control Bits
RM0351 Comparator (COMP) Table 145. Interrupt control bits Enable control Exit from Sleep Exit from Stop Exit from Interrupt event Event flag mode modes Standby mode VALUE in COMP1 output through EXTI COMP1_CSR VALUE in COMP2 output through EXTI COMP2_CSR DocID024597 Rev 5 681/1830...
Page 682 Comparator (COMP) RM0351 22.6 COMP registers 22.6.1 Comparator 1 control and status register (COMP1_CSR) The COMP1_CSR is the Comparator 1 control/status register. It contains all the bits /flags related to comparator1. Address offset: 0x00 System reset value: 0x0000 0000 SCAL LOCK VALUE Res.
Page 683 RM0351 Comparator (COMP) Bits 20:18 BLANKING[2:0]: Comparator 1 blanking source selection bits These bits select which timer output controls the comparator 1 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source 100: TIM3 OC3 selected as blanking source All other values: reserved Bits 17:16 HYST[1:0]: Comparator 1 hysteresis selection bits...
Page 684 Comparator (COMP) RM0351 22.6.2 Comparator 2 control and status register (COMP2_CSR) The COMP2_CSR is the Comparator 2 control/status register. It contains all the bits /flags related to comparator2. Address offset: 0x04 System reset value: 0x0000 0000 SCAL LOCK VALUE Res. Res.
Page 685 RM0351 Comparator (COMP) Bits 17:16 HYST[1:0]: Comparator 2 hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). Select the Hysteresis voltage of the comparator 2. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Bit 15 POLARITY: Comparator 2 polarity selection bit This bit is set and cleared by software (only if LOCK not set).
Page 686: Table 146. Comp Register Map And Reset Values
Comparator (COMP) RM0351 22.6.3 COMP register map The following table summarizes the comparator registers. Table 146. COMP register map and reset values Offset Register COMP1_CSR 0x00 Reset value COMP2_CSR 0x04 Reset value Refer to Section 2.2.2 on page 75 for the register boundary addresses. 686/1830 DocID024597 Rev 5...
Page 687 RM0351 Operational amplifiers (OPAMP) Operational amplifiers (OPAMP) 23.1 Introduction The device embeds two operational amplifiers with two inputs and one output each. The three I/Os can be connected to the external pins, this enables any type of external interconnections. The operational amplifier can be configured internally as a follower or as an amplifier with a non-inverting gain ranging from 2 to 16.
Page 688: Table 147. Operational Amplifier Possible Connections
Operational amplifiers (OPAMP) RM0351 23.3.2 Initial configuration The default configuration of the operational amplifier is a functional mode where the three IOs are connected to external pins. In the default mode the operational amplifier uses the factory trimming values. See electrical characteristics section of the datasheet for factory trimming conditions, usually the temperature is 30 °C and the voltage is 3 V.
Page 689: Figure 159. Standalone Mode: External Gain Setting Mode
RM0351 Operational amplifiers (OPAMP) 23.3.4 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: • Standalone mode (external gain setting mode) • Follower configuration mode • PGA modes Note: The amplifier output pin is directly connected to the output pad to minimize the output impedance.
Page 690: Figure 160. Follower Configuration
Operational amplifiers (OPAMP) RM0351 Follower configuration mode The procedure to use the OPAMP in follower mode is presented hereafter. • configure OPAMODE bits as “internal follower” • configure VP_SEL bits as “GPIO connected to VINP”. • As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is copied to pin OPAMP_VOUT.
Page 691: Figure 161. Pga Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Not Used
RM0351 Operational amplifiers (OPAMP) Programmable Gain Amplifier mode The procedure to use the OPAMP to amplify the amplitude of an input signal is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, • configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”, •...
Page 692: Figure 162. Pga Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Used For Filtering
Operational amplifiers (OPAMP) RM0351 Programmable Gain Amplifier mode with external filtering The procedure to use the OPAMP to amplify the amplitude of an input signal, with an external filtering, is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, •...
Page 693: Table 148. Operating Modes And Calibration
RM0351 Operational amplifiers (OPAMP) The user is able to switch from ‘factory’ values to ‘user’ trimmed values using the USERTRIM bit in the OPAMP_CSR register. This bit is reset at startup and so the ‘factory’ value are applied by default to the OPAMP trimming registers. User is liable to change the trimming values in calibration or in functional mode.
Page 694: Table 149. Effect Of Low-Power Modes On The Opamp
Operational amplifiers (OPAMP) RM0351 Calibration procedure Here are the steps to perform a full calibration of either one of the operational amplifiers: Select correct OPA_RANGE in OPAMP_CSR, then set the OPAEN bit in OPAMP_CSR to 1 to enable the operational amplifier. Set the USERTRIM bit in the OPAMP_CSR register to 1.
Page 695 RM0351 Operational amplifiers (OPAMP) Table 149. Effect of low-power modes on the OPAMP Mode Description Standby The OPAMP registers are powered down and must be re-initialized after exiting Standby or Shutdown mode. Shutdown 23.5 OPAMP registers 23.5.1 OPAMP1 control/status register (OPAMP1_CSR) Address offset: 0x00 Reset value: 0x0000 0000 OPA_...
Page 696 Operational amplifiers (OPAMP) RM0351 Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00: GPIO connected to VINM (valid also in PGA mode for filtering) 01: Dedicated low leakage input, (available only on BGA132 and BGA169 for STM32L496xx/4A6xx devices) connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected.
Page 697 RM0351 Operational amplifiers (OPAMP) Reset value: 0x0000 XXXX (factory trimmed values) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIMLPOFFSETP Res. Res. Res. TRIMLPOFFSETN Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value.
Page 698 Operational amplifiers (OPAMP) RM0351 Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00: GPIO connected to VINM (valid also in PGA mode for filtering) 01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected.
Page 699: Table 150. Opamp Register Map And Reset Values
RM0351 Operational amplifiers (OPAMP) Reset value: 0x0000 XXXX (factory trimmed values) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIMLPOFFSETP Res. Res. Res. TRIMLPOFFSETN Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value.
Page 700 Digital filter for sigma delta modulators (DFSDM) RM0351 Digital filter for sigma delta modulators (DFSDM) 24.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators to a microcontroller. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution.
Page 701 RM0351 Digital filter for sigma delta modulators (DFSDM) 24.2 DFSDM main features • Up to 8 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – clock output for Σ∆ modulator(s) •...
Page 702: Table 151. Dfsdm1 Implementation
Digital filter for sigma delta modulators (DFSDM) RM0351 24.3 DFSDM implementation This section describes the configuration implemented in DFSDMx. Table 151. DFSDM1 implementation DFSDM features DFSDM1 Number of channels Number of filters Input from internal ADC Supported trigger sources Pulses skipper ID registers support 1.
Page 703: Figure 163. Single Dfsdm Block Diagram
RM0351 Digital filter for sigma delta modulators (DFSDM) 24.4 DFSDM functional description 24.4.1 DFSDM block diagram Figure 163. Single DFSDM block diagram 1. This example shows 4 DFSDM filters and 8 input channels (max. configuration). ADC inputs are only available for DocID024597 Rev 5 703/1830...
Page 704: Table 152. Dfsdm External Pins
Digital filter for sigma delta modulators (DFSDM) RM0351 STM32L496xx/4A6xx devices. 24.4.2 DFSDM pins and internal signals Table 152. DFSDM external pins Name Signal Type Remarks Power supply Digital power supply. Power supply Digital ground power supply. CKIN[7:0] Clock input Clock signal provided from external Σ∆ modulator. FT input. DATIN[7:0] Data input Data signal provided from external Σ∆...
Page 705: Table 155. Dfsdm Break Connection
RM0351 Digital filter for sigma delta modulators (DFSDM) Table 154. DFSDM triggers connection (continued) Trigger name Trigger source dfsdm_jtrg9 EXTI11 dfsdm_jtrg10 EXTI15 Table 155. DFSDM break connection Break name Break destination dfsdm_break[0] TIM1 break dfsdm_break[1] TIM1 break2 dfsdm_break[2] TIM8 break dfsdm_break[3] TIM8 break2 24.4.3...
Page 706 Digital filter for sigma delta modulators (DFSDM) RM0351 The DFSDM serial channel transceivers can receive an external serial clock to sample an external serial data stream. The internal DFSDM clock must be at least 4 times faster than the external serial clock if standard SPI coding is used, and 6 times faster than the external serial clock if Manchester coding is used.
Page 707: Figure 164. Input Channel Pins Redirection
RM0351 Digital filter for sigma delta modulators (DFSDM) Figure 164. Input channel pins redirection Output clock generation A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs. The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV bits in DFSDM_CH0CFGR1 register).
Page 708 Digital filter for sigma delta modulators (DFSDM) RM0351 SPI data input format operation In SPI format, the data stream is sent in serial format through data and clock signals. Data signal is always provided from DATINy pin. A clock signal can be provided externally from CKINy pin or internally from a signal derived from the CKOUT signal source.
Page 709: Figure 165. Channel Transceiver Timing Diagrams
RM0351 Digital filter for sigma delta modulators (DFSDM) Figure 165. Channel transceiver timing diagrams DocID024597 Rev 5 709/1830...
Page 710: Figure 166. Clock Absence Timing Diagram For Spi
Digital filter for sigma delta modulators (DFSDM) RM0351 Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1 register.
Page 711: Figure 167. Clock Absence Timing Diagram For Manchester Coding
RM0351 Digital filter for sigma delta modulators (DFSDM) The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (CKOUT signal). There must be a voltage level change on DATINy pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CH0CFGR1 register).
Page 712 Digital filter for sigma delta modulators (DFSDM) RM0351 Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence detailed hereafter:...
Page 713: Figure 168. First Conversion For Manchester Coding (Manchester Synchronization)
RM0351 Digital filter for sigma delta modulators (DFSDM) Figure 168. First conversion for Manchester coding (Manchester synchronization) External serial clock frequency measurement The measuring of a channel serial clock input frequency provides a real data rate from an external Σ∆ modulator, which is important for application purposes. An external serial clock input frequency can be measured by a timer counting DFSDM clocks (f ) during one conversion duration.
Page 714 Digital filter for sigma delta modulators (DFSDM) RM0351 Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not interrupt the conversion for correct conversion duration result. Conversion times: injected conversion or regular conversion with FAST = 0 (or first conversion if FAST=1):...
Page 715 RM0351 Digital filter for sigma delta modulators (DFSDM) 24.4.5 Configuring the input serial interface The following parameters must be configured for the input serial interface: • Output clock predivider. There is a programmable predivider to generate the output clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in DFSDM_CH0CFGR1 register.
Page 716 Digital filter for sigma delta modulators (DFSDM) RM0351 The setting of data packing mode (DATPACK[1:0] in the DFSDM_CHyCFGR1 register) has no effect in case of ADC data input. Note: Extension of ADC specification: in case the internal ADC is configured in interleaved mode (e.g.
Page 717: Figure 169. Dfsdm_Chydatinr Registers Operation Modes And Assignment
RM0351 Digital filter for sigma delta modulators (DFSDM) DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR registers. Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y = 0, 2, 4, 6).
Page 718 Digital filter for sigma delta modulators (DFSDM) RM0351 Injected conversions can be launched by software or by a trigger. They are never interrupted by regular conversions. The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the DFSDM_FLTxCR1 register indicates the selected channel.
Page 719: Table 156. Filter Maximum Output Resolution (Peak Data Values From Filter Output)
RM0351 Digital filter for sigma delta modulators (DFSDM) Figure 170. Example: Sinc filter response Table 156. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- x +/- x +/- 2x +/- x +/- x...
Page 720: Table 157. Integrator Maximum Output Resolution
Digital filter for sigma delta modulators (DFSDM) RM0351 Table 157. Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc filter type (largest data) IOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- FOSR.
Page 721 RM0351 Digital filter for sigma delta modulators (DFSDM) There are 2 options for comparing the threshold registers with the data values • Option1: in this case, the input data are taken from final output data register (AWFSEL=0). This option is characterized by: –...
Page 722 Digital filter for sigma delta modulators (DFSDM) RM0351 Analog watchdog filter data for given channel y is available for reading by firmware on field WDATA[15:0] in DFSDM_CHyWDATR register. That analog watchdog filter data is converted continuously (if CHEN=1 in DFSDM_CHyCFGR1 register) with the data rate given by the analog watchdog filter setting and the channel input clock frequency.
Page 723 RM0351 Digital filter for sigma delta modulators (DFSDM) circuit event is invoked. Each input channel has its short-circuit detector. Any channel can be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHyCFGR1 register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits, status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]).
Page 724 Digital filter for sigma delta modulators (DFSDM) RM0351 CKIN ⁄ Datarate samples ...FAST = 1 --------------------------------- - ⋅ Maximum output data rate in case of parallel data input: DATAIN_RATE ⁄ Datarate samples ...FAST = 0, Sincx filter --------------------------------------------------------------------------------------------------------- - ⋅ –...
Page 725 RM0351 Digital filter for sigma delta modulators (DFSDM) Signed data format in registers: Data is in a signed format in registers for final output data, analog watchdog, extremes detector, offset correction. The msb of output data word represents the sign of value (two’s complement format). 24.4.15 Launching conversions Injected conversions can be launched using the following methods:...
Page 726 Digital filter for sigma delta modulators (DFSDM) RM0351 The regular conversions executing in continuous mode can be stopped by writing ‘0’ to RCONT. After clearing RCONT, the on-going conversion is stopped immediately. In continuous mode, the data rate can be increased by setting the FAST bit in the DFSDM_FLTxCR1 register.
Page 727 RM0351 Digital filter for sigma delta modulators (DFSDM) the sequence of injected conversions finishes, the continuous regular conversions start again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular conversion result). Precedence also matters when actions are initiated by the same write to DFSDM, or if multiple actions are pending at the end of another action.
Page 728: Table 158. Dfsdm Interrupt Requests
Digital filter for sigma delta modulators (DFSDM) RM0351 • Analog watchdog interrupt: – occurred when converted data (output data or data from analog watchdog filter - according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR registers –...
Page 729 RM0351 Digital filter for sigma delta modulators (DFSDM) 24.6 DFSDM DMA transfer To decrease the CPU intervention, conversions can be transferred into memory using a DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1 in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Page 730 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider 0: Output clock generation is disabled (CKOUT signal is set to low state) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 - 256 (Divider = CKOUTDIV+1).
Page 731 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 6 CKABEN: Clock absence detector enable on channel y 0: Clock absence detector disabled on channel y 1: Clock absence detector enabled on channel y Bit 5 SCDEN: Short-circuit detector enable on channel y 0: Input channel y will not be guarded by the short-circuit detector 1: Input channel y will be continuously guarded by the short-circuit detector Bit 4 Reserved, must be kept at reset value.
Page 732 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software. Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right will be performed to have final results.
Page 733 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y Bits 11:8 Reserved, must be kept at reset value.
Page 734 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (only for STM32L496xx/4A6xx devices, ifDATMPX[1:0]=1).
Page 735 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 31 Reserved, must be kept at reset value. Bit 30 AWFSEL: Analog watchdog fast mode select 0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 1: Analog watchdog on channel transceivers value (after watchdog filter) Bit 29 FAST: Fast conversion mode selection for regular conversions...
Page 736 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 17 RSWSTART: Software start of a conversion on the regular channel 0: Writing ‘0’ has no effect 1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’.
Page 737 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 2 Reserved, must be kept at reset value. Bit 1 JSWSTART: Start a conversion of the injected group of channels 0: Writing ‘0’ has no effect. 1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’...
Page 738 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 5 SCDIE: Short-circuit detector interrupt enable 0: short-circuit detector interrupt is disabled 1: short-circuit detector interrupt is enabled Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0) Bit 4 AWDIE: Analog watchdog interrupt enable 0: Analog watchdog interrupt is disabled 1: Analog watchdog interrupt is enabled...
Page 739 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:24 SCDF[7:0]: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register.
Page 740 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 2 JOVRF: Injected conversion overrun flag 0: No injected conversion overrun has occurred 1: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns This bit is set by hardware.
Page 741 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 3 CLRROVRF: Clear the regular conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register Bit 2 CLRJOVRF: Clear the injected conversion overrun flag 0: Writing ‘0’...
Page 742 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:29 FORD[2:0]: Sinc filter order 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type 4: Sinc filter type 5: Sinc filter type 6-7: Reserved FOSR ⎛...
Page 743 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 JDATA[23:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. Bits 7:3 Reserved, must be kept at reset value.
Page 744 Digital filter for sigma delta modulators (DFSDM) RM0351 24.8.9 DFSDM analog watchdog high threshold register (DFSDM_FLTxAWHTR) Address offset: 0x120 + 0x80 * x, x = 0...3 Reset value: 0x0000 0000 AWHT[23:8] AWHT[7:0] Res. Res. Res. Res. BKAWH[3:0] Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog.
Page 745 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 AWLT[23:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution).
Page 746 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing ‘0’ has no effect CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing ‘0’...
Page 747 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 EXMIN[23:0]: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. Bits 7:3 Reserved, must be kept at reset value.
Page 748: Table 159. Dfsdm Register Map And Reset Values
Digital filter for sigma delta modulators (DFSDM) RM0351 24.8.16 DFSDM register map The following table summarizes the DFSDM registers. Table 159. DFSDM register map and reset values Offset Register DFSDM_ CKOUTDIV[7:0] CH0CFGR1 0x00 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH0CFGR2 0x04 reset value DFSDM_ AWFOSR[4:0]...
Page 749 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 159. DFSDM register map and reset values (continued) Offset Register DFSDM_ CH2CFGR1 0x40 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH2CFGR2 0x44 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH2AWSCDR 0x48 reset value DFSDM_ WDATA[15:0] CH2WDATR 0x4C...
Page 750 Digital filter for sigma delta modulators (DFSDM) RM0351 Table 159. DFSDM register map and reset values (continued) Offset Register DFSDM_ OFFSET[23:0] DTRBS[4:0] CH4CFGR2 0x84 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH4AWSCDR 0x88 reset value DFSDM_ WDATA[15:0] CH4WDATR 0x8C reset value DFSDM_ INDAT1[15:0] INDAT0[15:0]...
Page 751 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 159. DFSDM register map and reset values (continued) Offset Register DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH6AWSCDR 0xC8 reset value DFSDM_ WDATA[15:0] CH6WDATR 0xCC reset value DFSDM_ INDAT1[15:0] INDAT0[15:0] CH6DATINR 0xD0 reset value 0xD4 - Reserved 0xDC...
Page 752 Digital filter for sigma delta modulators (DFSDM) RM0351 Table 159. DFSDM register map and reset values (continued) Offset Register DFSDM_ CLRSCDF[7:0] CLRCKABF[7:0] FLT0ICR 0x10C reset value DFSDM_ JCHG[7:0] FLT0JCHGR 0x110 reset value DFSDM_ FOSR[9:0] IOSR[7:0] FLT0FCR 0x114 reset value DFSDM_ JDATA[23:0] FLT0JDATAR 0x118...
Page 753 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 159. DFSDM register map and reset values (continued) Offset Register DFSDM_ RCH[2:0] FLT1CR1 0x180 reset value DFSDM_ AWDCH[7:0] EXCH[7:0] FLT1CR2 0x184 reset value DFSDM_ FLT1ISR 0x188 reset value DFSDM_ FLT1ICR 0x18C reset value JCHG[7:0] DFSDM_...
Page 754 Digital filter for sigma delta modulators (DFSDM) RM0351 Table 159. DFSDM register map and reset values (continued) Offset Register DFSDM_ EXMAX[23:0] FLT1EXMAX 0x1B0 reset value DFSDM_ EXMIN[23:0] FLT1EXMIN 0x1B4 reset value DFSDM_ CNVCNT[27:0] FLT1CNVTIMR 0x1B8 reset value 0x1BC - Reserved 0x1FC DFSDM_ RCH[2:0]...
Page 755 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 159. DFSDM register map and reset values (continued) Offset Register RDATA DFSDM_ RDATA[23:0] CH[2:0] FLT2RDATAR 0x21C reset value DFSDM_ AWHT[23:0] BKAWH[3:0] FLT2AWHTR 0x220 reset value DFSDM_ AWLT[23:0] BKAWL[3:0] FLT2AWLTR 0x224 reset value DFSDM_ AWHTF[7:0] AWLTF[7:0]...
Page 756 Digital filter for sigma delta modulators (DFSDM) RM0351 Table 159. DFSDM register map and reset values (continued) Offset Register DFSDM_ FOSR[9:0] IOSR[7:0] FLT3FCR 0x294 reset value DFSDM_ JDATA[23:0] FLT3JDATAR 0x298 reset value RDATA DFSDM_ RDATA[23:0] CH[2:0] FLT3RDATAR 0x29C reset value DFSDM_ AWHT[23:0] BKAWH[3:0]...
Page 757 RM0351 Liquid crystal display controller (LCD) Liquid crystal display controller (LCD) 25.1 Introduction The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8 common terminals and up to 44 segment terminals to drive 176 (44x4) or 320 (40x8) LCD picture elements (pixels).
Page 758 Liquid crystal display controller (LCD) RM0351 25.2 LCD main features • Highly flexible frame rate control. • Supports Static, 1/2, 1/3, 1/4 and 1/8 duty. • Supports Static, 1/2, 1/3 and 1/4 bias. • Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed.
Page 759: Figure 171. Lcd Controller Block Diagram
RM0351 Liquid crystal display controller (LCD) 25.3 LCD functional description 25.3.1 General description The LCD controller has five main blocks (see Figure 171): Figure 171. LCD controller block diagram Note: LCDCLK is the same as RTCCLK. Please refer to the RTC/LCD clock description in the RCC section of this manual.
Page 760: Table 160. Example Of Frame Rate Calculation
Liquid crystal display controller (LCD) RM0351 25.3.2 Frequency generator This clock source must be stable in order to obtain accurate LCD timing and hence minimize DC voltage offset across LCD segments. The input clock LCDCLK can be divided by any value from 1 to 2 x 31 (see Section 25.6.2: LCD frame control register (LCD_FCR) on page...
Page 761: Figure 172. 1/3 Bias, 1/4 Duty
RM0351 Liquid crystal display controller (LCD) addition, a dedicated blink prescaler selects the blink frequency. This frequency is defined (BLINKF + 3) BLINK ck_div with BLINKF[2:0] = 0, 1, 2, ... ,7 The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz or 4 Hz. 25.3.3 Common driver Common signals are generated by the common driver block (see...
Page 762: Figure 173. Static Duty Case 1
Liquid crystal display controller (LCD) RM0351 COM[n] n[0 to 7] is active during phase n in the odd frame, so the COM pin is driven to During phase n of the even frame the COM pin is driven to V In the case of 1/3 or 1/4) bias: •...
Page 763: Figure 174. Static Duty Case 2
RM0351 Liquid crystal display controller (LCD) Figure 174. Static duty case 2 In this mode, the segment terminals are multiplexed and each of them control four pixels. A pixel is activated only when both of its corresponding SEG and COM lines are active in the same phase.
Page 764: Figure 175. 1/2 Duty, 1/2 Bias
Liquid crystal display controller (LCD) RM0351 Figure 175. 1/2 duty, 1/2 bias 25.3.4 Segment driver The segment driver block controls the SEG lines according to the pixel data coming from the 8 to 1 mux driven in each phase by the common driver block. In the case of 1/4 or 1/8 duty When COM[0] is active, the pixel information (active/inactive) related to the pixel connected to COM[0] (content of the first two LCD_RAM locations) goes through the 8 to 1 mux.
Page 765: Figure 176. 1/3 Duty, 1/3 Bias
RM0351 Liquid crystal display controller (LCD) Figure 176. 1/3 duty, 1/3 bias DocID024597 Rev 5 765/1830...
Page 766: Figure 177. 1/4 Duty, 1/3 Bias
Liquid crystal display controller (LCD) RM0351 Figure 177. 1/4 duty, 1/3 bias 766/1830 DocID024597 Rev 5...
Page 767: Figure 178. 1/8 Duty, 1/4 Bias
RM0351 Liquid crystal display controller (LCD) Figure 178. 1/8 duty, 1/4 bias DocID024597 Rev 5 767/1830...
Page 768: Table 161. Blink Frequency
Liquid crystal display controller (LCD) RM0351 Blink The segment driver also implements a programmable blink feature to allow some pixels to continuously switch on at a specific frequency. The blink mode can be configured by the BLINK[1:0] bits in the LCD_FCR register, making possible to blink up to 1, 2, 4, 8 or all pixels (see Section 25.6.2: LCD frame control register (LCD_FCR)).
Page 769 RM0351 Liquid crystal display controller (LCD) In case the internal step-up converter is used (capacitor C on VLCD pin is required): • Configure the VLCD pin as alternate function LCD in the GPIO_AFR register. • Wait for the external capacitor C to be charged (C connected to the VLCD pin, approximately 2 ms for C...
Page 770: Figure 179. Lcd Voltage Control
Liquid crystal display controller (LCD) RM0351 Figure 179. LCD voltage control 1. R and R are the low value resistance network and the high value resistance network, respectively. The R divider can be always switched on using the HD bit in the LCD_FCR configuration register (see Section 25.6.2).
Page 771: Figure 180. Deadtime
RM0351 Liquid crystal display controller (LCD) In buffer mode, intermediate voltages are generated by the high value resistor bridge R reduce power consumption, the low value resistor bridge R is automatically disabled whatever the HD bit or PON bits configuration. Buffers can be used independently of the V supply source (internal or external) but can only be enabled or disabled when LCD controller is not activated.
Page 772 Liquid crystal display controller (LCD) RM0351 25.3.6 Double buffer memory Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification. The application software can access the first buffer level (LCD_RAM) through the APB interface.
Page 773: Table 162. Remapping Capability
RM0351 Liquid crystal display controller (LCD) Summary of COM and SEG functions versus duty and remap All the possible ways of multiplexing the COM and SEG functions are described in Table 162. Figure 181 gives examples showing the signal connections to the external pins. Table 162.
Page 774 Liquid crystal display controller (LCD) RM0351 Table 162. Remapping capability (continued) Configuration bits SEG x COM LQFP144 Output pin Function WLCSP72 DUTY MUX_SEG UFBGA132 LQFP64 LQFP100 COM3 not used COM[2:0] COM[2:0] 44x3 SEG[43:40]/SEG[31:28]/COM[7:4] SEG[43:40] SEG[39:0] SEG[39:0] COM3 not used COM[2:0] COM[2:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28]...
Page 775 RM0351 Liquid crystal display controller (LCD) Table 162. Remapping capability (continued) Configuration bits SEG x COM LQFP144 Output pin Function WLCSP72 DUTY MUX_SEG UFBGA132 LQFP64 LQFP100 COM[3:2] not used COM[1:0] COM[1:0] 28x2 SEG[43:40]/SEG[31:28]/COM[7:4] not used SEG[27:0] SEG[27:0] COM[3:2] not used COM[1:0] COM[1:0] 32x2...
Page 776: Figure 181. Seg/Com Mux Feature Example
Liquid crystal display controller (LCD) RM0351 Figure 181. SEG/COM mux feature example 776/1830 DocID024597 Rev 5...
Page 777: Figure 182. Flowchart Example
RM0351 Liquid crystal display controller (LCD) 25.3.8 Flowchart Figure 182. Flowchart example DocID024597 Rev 5 777/1830...
Page 778: Table 163. Lcd Behavior In Low-Power Modes
Liquid crystal display controller (LCD) RM0351 25.4 LCD low-power modes the LCD controller can be displayed in Stop mode or can be fully disabled to reduce power consumption. Table 163. LCD behavior in low-power modes Mode Description Sleep No effect. LCD interrupt causes the device to exit the Sleep mode. Low-power run No effect.
Page 779 RM0351 Liquid crystal display controller (LCD) Configure and enable the LCD IRQ channel in the NVIC Configure the LCD to generate interrupts 25.6 LCD registers The peripheral registers have to be accessed by words (32-bit). 25.6.1 LCD control register (LCD_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 780 Liquid crystal display controller (LCD) RM0351 Bits 4:2 DUTY[2:0]: Duty selection These bits determine the duty cycle. Values 101, 110 and 111 are forbidden. 000: Static duty 001: 1/2 duty 010: 1/3 duty 011: 1/4 duty 100: 1/8 duty 101: Reserved 110: Reserved 111: Reserved Bit 1 VSEL: Voltage source selection...
Page 781 RM0351 Liquid crystal display controller (LCD) Bits 31:26 Reserved, must be kept at reset value Bits 25:22 PS[3:0]: PS 16-bit prescaler These bits are written by software to define the division factor of the PS 16-bit prescaler. ck_ps = LCDCLK/(2). See Section 25.3.2.
Page 782 Liquid crystal display controller (LCD) RM0351 Bits 9:7 DEAD[2:0]: Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate.
Page 783 RM0351 Liquid crystal display controller (LCD) Note: The data in this register can be updated any time, however the new values are applied only at the beginning of the next frame (except for UDDIE, SOFIE that affect the device behavior immediately).
Page 784 Liquid crystal display controller (LCD) RM0351 Bit 2 UDR: Update display request Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.
Page 785: Table 165. Lcd Register Map And Reset Values
RM0351 Liquid crystal display controller (LCD) Bit 2 Reserved, must be kept at reset value Bit 1 SOFC: Start of frame flag clear This bit is written by software to clear the SOF flag in the LCD_SR register. 0: No effect 1: Clear SOF flag Bit 0 Reserved, must be kept at reset value 25.6.5...
Page 786 Liquid crystal display controller (LCD) RM0351 Table 165. LCD register map and reset values (continued) Register LCD_CLR 0x0C Reset value 0x14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_RAM (COM0) 0x18...
Page 787 RM0351 Liquid crystal display controller (LCD) Table 165. LCD register map and reset values (continued) Register 0x44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_RAM (COM6) 0x48...
Page 788 Touch sensing controller (TSC) RM0351 Touch sensing controller (TSC) 26.1 Introduction The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (for example glass, plastic).
Page 789: Figure 183. Tsc Block Diagram
RM0351 Touch sensing controller (TSC) 26.3 TSC functional description 26.3.1 TSC block diagram The block diagram of the touch sensing controller is shown in Figure 183: TSC block diagram. Figure 183. TSC block diagram 26.3.2 Surface charge transfer acquisition overview The surface charge transfer acquisition is a proven, robust and efficient way to measure a capacitance.
Page 790: Figure 184. Surface Charge Transfer Analog I/O Group Structure
Touch sensing controller (TSC) RM0351 The remaining GPIOs are dedicated to the electrodes and are commonly called channels. For some specific needs (such as proximity detection), it is possible to simultaneously enable more than one channel per analog I/O group. Figure 184.
Page 791: Table 166. Acquisition Sequence Summary
RM0351 Touch sensing controller (TSC) Table 166. Acquisition sequence summary G1_IO1 G1_IO2 G1_IO3 G1_IO4 State State description (electrode) (sampling) (electrode) (electrode) Output open- Input floating drain low with Input floating with analog switch Discharge all C with analog analog switch closed switch closed closed...
Page 792: Figure 186. Charge Transfer Acquisition Sequence
Touch sensing controller (TSC) RM0351 26.3.4 Charge transfer acquisition sequence An example of a charge transfer acquisition sequence is detailed in Figure 186. Figure 186. Charge transfer acquisition sequence For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high state (charge of C ) and the pulse low state (transfer of charge from C to C...
Page 793: Table 167. Spread Spectrum Deviation Versus Ahb Clock Frequency
RM0351 Touch sensing controller (TSC) 26.3.5 Spread spectrum feature The spread spectrum feature allows to generate a variation of the charge transfer frequency. This is done to improve the robustness of the charge transfer acquisition in noisy environments and also to reduce the induced emission. The maximum frequency variation is in the range of 10% to 50% of the nominal charge transfer period.
Page 794: Table 168. I/O State Depending On Its Mode And Iodef Bit Value
Touch sensing controller (TSC) RM0351 26.3.7 Sampling capacitor I/O and channel I/O mode selection To allow the GPIOs to be controlled by the touch sensing controller, the corresponding alternate function must be enabled through the standard GPIO registers and the GPIOxAFR registers.
Page 795 RM0351 Touch sensing controller (TSC) Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR or TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 26.3.8 Acquisition mode The touch sensing controller offers two acquisition modes:...
Page 796: Table 169. Effect Of Low-Power Modes On Tsc
Touch sensing controller (TSC) RM0351 26.4 TSC low-power modes Table 169. Effect of low-power modes on TSC Mode Description Sleep No effect. Peripheral interrupts cause the device to exit Sleep mode. Low power run No effect. Low power sleep No effect. Peripheral interrupts cause the device to exit Low-power sleep mode. Stop 0 / Stop 1 Peripheral registers content is kept.
Page 797 RM0351 Touch sensing controller (TSC) 26.6 TSC registers Refer to Section 1.1 on page 67 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 26.6.1 TSC control register (TSC_CR) Address offset: 0x00 Reset value: 0x0000 0000 CTPH[3:0]...
Page 798 Touch sensing controller (TSC) RM0351 Bit 16 SSE: Spread spectrum enable This bit is set and cleared by software to enable/disable the spread spectrum feature. 0: Spread spectrum disabled 1: Spread spectrum enabled Note: This bit must not be modified when an acquisition is ongoing. Bit 15 SSPSC: Spread spectrum prescaler This bit is set and cleared by software.
Page 799 RM0351 Touch sensing controller (TSC) Bit 2 AM: Acquisition mode This bit is set and cleared by software to select the acquisition mode. 0: Normal acquisition mode (acquisition starts as soon as START bit is set) 1: Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) Note: This bit must not be modified when an acquisition is ongoing.
Page 800 Touch sensing controller (TSC) RM0351 26.6.3 TSC interrupt clear register (TSC_ICR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 801 RM0351 Touch sensing controller (TSC) 26.6.4 TSC interrupt status register (TSC_ISR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 802 Touch sensing controller (TSC) RM0351 26.6.6 TSC I/O analog switch control register (TSC_IOASCR) Address offset: 0x18 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
Page 803 RM0351 Touch sensing controller (TSC) 26.6.8 TSC I/O channel control register (TSC_IOCCR) Address offset: 0x28 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
Page 804 Touch sensing controller (TSC) RM0351 Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 GxS: Analog I/O group x status These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. 0: Acquisition on analog I/O group x is ongoing or not started 1: Acquisition on analog I/O group x is complete Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O...
Page 805: Table 171. Tsc Register Map And Reset Values
RM0351 Touch sensing controller (TSC) 26.6.11 TSC register map Table 171. TSC register map and reset values Offset Register CTPH[3:0] CTPL[3:0] SSD[6:0] TSC_CR [2:0] 0x0000 Reset value TSC_IER 0x0004 Reset value TSC_ICR 0x0008 Reset value TSC_ISR 0x000C Reset value TSC_IOHCR 0x0010 Reset value 0x0014...
Page 806 Touch sensing controller (TSC) RM0351 Table 171. TSC register map and reset values (continued) Offset Register CNT[13:0] TSC_IOG3CR 0x003C Reset value CNT[13:0] TSC_IOG4CR 0x0040 Reset value CNT[13:0] TSC_IOG5CR 0x0044 Reset value CNT[13:0] TSC_IOG6CR 0x0048 Reset value CNT[13:0] TSC_IOG7CR 0x004C Reset value CNT[13:0] TSC_IOG8CR 0x0050...
Page 807 RM0351 True Random Number Generator (RNG) True Random Number Generator (RNG) 27.1 Introduction The RNG is a true random number generator that continuously provides 32-bit entropy samples, based on an analog noise source. It can be used by the application as a live entropy source to build a NIST compliant Deterministic Random Bit Generator (DRBG).
Page 808: Table 172. Rng Internal Input/Output Signals
True Random Number Generator (RNG) RM0351 Figure 188. RNG block diagram 27.3.2 RNG internal signals Table 172 describes a list of useful-to-know internal signals available at the RNG level, not at the STM32 product level (on pads). Table 172. RNG internal input/output signals Signal name Signal type Description...
Page 809: Figure 189. Entropy Source Model
RM0351 True Random Number Generator (RNG) Figure 189. Entropy source model The main components of the RNG are: • A source of physical randomness (analog noise source) • A digitization stage for this analog noise source • A stage delivering post-processed noise source (raw data) •...
Page 810 True Random Number Generator (RNG) RM0351 Post processing The sample values obtained from a true random noise source consist of 2-bit bitstrings. Because this noise source output is biased, the RNG implements a post-processing component that reduces that bias to a tolerable level. The RNG post-processing consists of two stages, applied to each noise source bits: •...
Page 811 RM0351 True Random Number Generator (RNG) 27.3.4 RNG initialization When a hardware reset occurs the following chain of events occurs: The analog noise source is enabled, and logic starts sampling the analog output after four RNG clock cycles, filling LFSR shift register and associated 16-bit post-processing shift register.
Page 812 True Random Number Generator (RNG) RM0351 Caution: When the CEC bit in the RNG_CR register is set to “1”, the RNG clock frequency must be higher than AHB clock frequency divided by 16, otherwise the clock checker will flag a clock error (CECS or CEIS in the RNG_SR register) and the RNG will stop producing random numbers.
Page 813: Table 173. Rng Interrupt Requests
RM0351 True Random Number Generator (RNG) Table 173. RNG interrupt requests Interrupt event Event flag Enable control bit Data ready flag DRDY Seed error flag SEIS Clock error flag CEIS The user can enable or disable the above interrupt sources individually by changing the mask bits or the general interrupt control bit IE in the RNG_CR register.
Page 814 True Random Number Generator (RNG) RM0351 27.8 RNG registers The RNG is associated with a control register, a data register and a status register. 27.8.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 815 RM0351 True Random Number Generator (RNG) Bits 31:7 Reserved, must be kept at reset value Bit 6 SEIS: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to ‘0’. 0: No faulty sequence detected 1: At least one faulty sequence has been detected.
Page 816: Table 174. Rng Register Map And Reset Map
True Random Number Generator (RNG) RM0351 27.8.4 RNG register map Table 174 gives the RNG register map and reset values. Table 174. RNG register map and reset map Register size Register name Offset reset value RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0...
Page 817 RM0351 Advanced encryption standard hardware accelerator (AES) Advanced encryption standard hardware accelerator (AES) 28.1 Introduction The AES hardware accelerator can be used to both encipher and decipher data using AES algorithm. It is a fully compliant implementation of the following standard: •...
Page 818: Figure 190. Aes Block Diagram
Advanced encryption standard hardware accelerator (AES) RM0351 28.3 AES functional description Figure 190 shows the block diagram of the AES accelerator. Figure 190. AES block diagram The AES accelerator processes data blocks of 128-bits (4 words) using a key with a length of either 256 bits or 128 bits, and an initialization vector when CBC, CTR, GCM, GMAC or CMAC chaining mode is selected.
Page 819 RM0351 Advanced encryption standard hardware accelerator (AES) in the AES_KEYRx registers and the AES is disabled by hardware. In this mode, the AES_KEYRx registers must not be read when AES is enabled and until the CCF flag is set to 1 by hardware. The status flag CCF in the AES_SR register is set once the computation phase is complete.
Page 820: Figure 191. Ecb Encryption Mode
Advanced encryption standard hardware accelerator (AES) RM0351 to switch the AES to mode 3 (decryption mode), there is no need to write the AES_KEYRx registers if their content corresponds to the derivation key (previously computed by mode 2). In mode 4 (key derivation + decryption), the AES_KEYRx registers contain only the encryption key.
Page 821: Figure 192. Ecb Decryption Mode
RM0351 Advanced encryption standard hardware accelerator (AES) Figure 192. ECB decryption mode 28.5.2 Cipher block chaining (CBC) In cipher-block chaining (CBC) mode, each block of plain text is XORed with the previous cipher text block before being encrypted. To make each message unique, an initialization vector (AES_IVRx) is used during the first block processing.
Page 822: Figure 193. Cbc Mode Encryption
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 193. CBC mode encryption Figure 194. CBC mode decryption Note: When the AES is enabled, reading the AES_IVR returns the value 0x0000 0000. 822/1830 DocID024597 Rev 5...
Page 823 RM0351 Advanced encryption standard hardware accelerator (AES) Suspended mode for a given message It is possible to suspend a message if another message with a higher priority needs to be processed. After sending this highest priority message, the suspended message may be resumed in both encryption or decryption mode.
Page 824: Figure 195. Example Of Suspend Mode Management
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 195. Example of suspend mode management 824/1830 DocID024597 Rev 5...
Page 825: Figure 196. Ctr Mode Encryption
RM0351 Advanced encryption standard hardware accelerator (AES) 28.5.3 Counter Mode (CTR) In counter mode, a 32-bit counter is used in addition to a nonce value for the XOR operation with the cipher text or plain text (refer to Figure 196 Figure 197).
Page 826: Figure 198. 32-Bit Counter + Nonce Organization
Advanced encryption standard hardware accelerator (AES) RM0351 The nonce value and 32-bit counter are accessible through the AES_IVRx register and organized like below in Figure 198: Figure 198. 32-bit counter + nonce organization In counter mode, the counter is incremented from the initialized value for each block to be processed in order to guarantee a unique sequence which is not repeated for a long time.
Page 827 RM0351 Advanced encryption standard hardware accelerator (AES) the size of the header on 64 bits and the size of the payload on 64 bits. During computation we have to distinguish between the blocks of the header and the blocks of the payload. Header •...
Page 828 Advanced encryption standard hardware accelerator (AES) RM0351 Repeat (p), (q), (r) and (s) until ciphering or deciphering of all the payload blocks. Alternatively, DMA may be used. GCM Final Phase: • In this last step, we generate the authentication tag. Choose the combination GCMPH[1:0] = 11 in AES_CR.
Page 829 RM0351 Advanced encryption standard hardware accelerator (AES) Suspend mode during Payload phase: the user must respect the following steps: • Before interrupting the current message: Read 4 times the AES_DOUTR register. Make sure that busy flag is set to 0 (only in encryption mode, not necessary in decryption mode).
Page 830 Advanced encryption standard hardware accelerator (AES) RM0351 Note: In this stage, no output is provided in AES_DOUTR register. Set GCMPH=”01” in AES_CR to indicate that we are in the header phase. Enable the AES by setting EN bit in AES_CR. Insert B0 for first transfer, and then B for further transfers.
Page 831 RM0351 Advanced encryption standard hardware accelerator (AES) To suspend mode CMAC during header phase, the user must respect the following steps: • Before interrupting the current message: Make sure that CCF flag in AES_SR is set to 1. Clear CCF flag in AES_SR register by setting CCFC bit to 1 in AES_CR. Save AES initialization vector registers AES_IVx and AES_SUSPxR registers in the memory (AES_IVx registers are modified during header phase) Disable AES processor by setting EN in AES_CR to 0.
Page 832: Figure 199. 128-Bit Block Construction According To The Data Type
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 199. 128-bit block construction according to the data type 832/1830 DocID024597 Rev 5...
Page 833: Figure 200. 128-Bit Block Construction According To The Data Type (Continued)
RM0351 Advanced encryption standard hardware accelerator (AES) Figure 200. 128-bit block construction according to the data type (continued) 28.9 Operating modes 28.9.1 Mode 1: encryption Disable the AES by resetting EN bit in the AES_CR register. Configure the mode 1 by programming MODE[1:0] = 00 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits.
Page 834: Figure 201. Mode 1: Encryption With 128-Bit Key Length
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 201. Mode 1: encryption with 128-bit key length 28.9.2 Mode 2: key derivation Disable the AES by resetting the EN bit in the AES_CR register. Configure mode 2 by programming MODE[1:0] = 01 in the AES_CR register. Note: CHMOD[2:0] bits are not significant in this case because this key derivation mode is independent from the chaining algorithm selected.
Page 835: Figure 203. Mode 3: Decryption With 128-Bit Key Length
RM0351 Advanced encryption standard hardware accelerator (AES) 28.9.3 Mode 3: decryption Disable the AES by resetting the EN bit in the AES_CR register. Configure mode 3 by programming MODE[1:0] = 10 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits.
Page 836: Figure 204. Mode 4: Key Derivation And Decryption With 128-Bit Key Length
Advanced encryption standard hardware accelerator (AES) RM0351 forced to CTR decryption mode if the software writes MODE[1:0] = 11 and CHMOD[2:0] = 010. Select key length 128-bit or 256-bit via KEYSIZE bits configuration in AES_CR register. Write the AES_KEYRx register with the encryption key. Write the AES_IVRx register if the CBC mode is selected.
Page 837: Figure 205. Dma Requests And Data Transfers During Input Phase (Aes_In)
RM0351 Advanced encryption standard hardware accelerator (AES) Note: For mode 2 (key derivation), access to the AES_KEYRx registers can be done by software using the CPU. No DMA channel is provided for this purpose. Consequently, the DMAINEN bit and DMAOUTEN bits in the AES_CR register have no effect during this mode. The CCF flag is not relevant when DMAOUTEN = 1 and software does not need to read it in this case.
Page 838: Table 175. Processing Time (In Clock Cycle)
Advanced encryption standard hardware accelerator (AES) RM0351 28.12 Processing time The following tables summarize the time required to process a 128-bit block for each mode of operation. Table 175. Processing time (in clock cycle) Computation Output Mode of operation Input phase Total phase phase...
Page 839: Table 178. Aes Interrupt Requests
RM0351 Advanced encryption standard hardware accelerator (AES) 28.13 AES interrupts Table 178. AES interrupt requests Enable Exit from Interrupt event Event flag control bit Wait AES computation completed flag CCFIE AES read error flag RDERR ERRIE AES write error flag WRERR ERRIE DocID024597 Rev 5...
Page 840 Advanced encryption standard hardware accelerator (AES) RM0351 28.14 AES registers 28.14.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SIZE Res. GCMPH[1:0] ERRIE CCFIE ERRC CCFC...
Page 841 RM0351 Advanced encryption standard hardware accelerator (AES) Bit 9 CCFIE: CCF flag interrupt enable An interrupt is generated if the CCF flag is set. 0: CCF interrupt disabled 1: CCF interrupt enabled Bit 8 ERRC: Error clear Writing 1 to this bit clears the RDERR and WRERR flags. This bit is always read low.
Page 842 Advanced encryption standard hardware accelerator (AES) RM0351 28.14.2 AES status register (AES_SR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 843 RM0351 Advanced encryption standard hardware accelerator (AES) Bit 2 WRERR: Write error flag This bit is set by hardware when an unexpected write operation to the AES_DINR register is detected (during computation or data output phase). An interrupt is generated if the ERRIE bit has been previously set in the AES_CR register.
Page 844 Advanced encryption standard hardware accelerator (AES) RM0351 28.14.3 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 DINR[31:16] DINR[15:0] Bits 31:0 DINR[31:0]: Data input register This register must be written 4 times during the input phase: – In mode 1 (encryption), 4 words must be written which represent the plain text from MSB to LSB. –...
Page 845 RM0351 Advanced encryption standard hardware accelerator (AES) 28.14.5 AES key register 0 (AES_KEYR0) (LSB: key [31:0]) Address offset: 0x10 Reset value: 0x0000 0000 KEYR0[31:16] KEYR0[15:0] Bits 31:0 KEYR0[31:0]: Data output register (LSB key [31:0]) This register must be written before the EN bit in the AES_CR register is set: In mode 1 (encryption), mode 2 (key derivation) and mode 4 (key derivation + decryption), the value to be written represents the encryption key from LSB, meaning key [31:0].
Page 846 Advanced encryption standard hardware accelerator (AES) RM0351 28.14.7 AES key register 2 (AES_KEYR2) (key [95:64]) Address offset: 0x18 Reset value: 0x0000 0000 KEYR2[31:16] KEYR2[15:0] Bits 31:0 KEYR2[31:0]: Data output register (key [95:64]) Refer to the description of AES_KEYR0. 28.14.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) Address offset: 0x1C Reset value: 0x0000 0000 KEYR3[31:16]...
Page 847 RM0351 Advanced encryption standard hardware accelerator (AES) Bits 31:0 IVR0[31:0]: initialization vector register (LSB IVR[31:0]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: – The ECB mode (electronic codebook) is selected. –...
Page 848 Advanced encryption standard hardware accelerator (AES) RM0351 28.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) Address offset: 0x28 Reset value: 0x0000 0000 IVR2[31:16] IVR2[15:0] Bits 31:0 IVR2[31:0]: Initialization vector register (IVR[95:64]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: –...
Page 849 RM0351 Advanced encryption standard hardware accelerator (AES) KEYR431:16] KEYR4[15:0] Bits 31:0 KEYR4[31:0]: Data output register (key [159:128]) Same description as AES_KEYR0 for the key[159:128]. 28.14.14 AES key register 5 (AES_KEYR5) (key[191:160]) Address offset: 0x34 Reset value: 0x0000 0000 KEYR5[31:16] KEYR5[15:0] Bits 31:0 KEYR5[31:0]: Data output register (key [191:160]) Same description as AES_KEYR0 for the key[191:160].
Page 850 Advanced encryption standard hardware accelerator (AES) RM0351 KEYR731:16] KEYR7[15:0] Bits 31:0 KEYR7[31:0]: Data output register (MSB key [255:224]) Same description as AES_KEYR0 for the key[255:224]. Note: The key registers from 4 to 7 are used only when 256-bit key length is selected. These registers have no effect when 128-bit key length is selected (only key registers from 0 to 3 are used).
Page 851: Table 179. Aes Register Map
RM0351 Advanced encryption standard hardware accelerator (AES) 28.14.17 AES registers (AES_SUSPxR) (x = 0..7) Suspend Address offset: 0x040 (AES_SUSP0R) to 0x05C (AES_SUSP7R) Reset value: 0x0000 0000 These registers contain the complete internal register states of the AES processor when the GCM/GMAC is selected, and are useful when a suspend has to be done because a high- priority task has to use the AES processor while it is already in use by another task.
Page 852 Advanced encryption standard hardware accelerator (AES) RM0351 Table 179. AES register map (continued) Offset Register AES_KEYR3 AES_KEYR3[31:0] 0x001C Reset value AES_IVR0 AES_IVR0[31:0] 0x0020 Reset value AES_IVR1 AES_IVR1[31:0] 0x0024 Reset value AES_IVR2 AES_IVR2[31:0] 0x0028 Reset value AES_IVR3 AES_IVR3[31:0] 0x002C Reset value AES_KEYR4 AES_KEYR4[31:0] 0x0030...
Page 853 RM0351 Hash processor (HASH) Hash processor (HASH) This section applies to STM32L496xx/4A6xx devices. 29.1 Introduction The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.
Page 854: Figure 207. Hash Block Diagram
Hash processor (HASH) RM0351 SHA-1 (respectively SHA-256) algorithm – 66 clock cycles for processing one 512-bit block of data using MD5 algorithm • AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB error is generated) • 8 × 32-bit words (H0 to H7) for output message digest •...
Page 855: Table 180. Hash Internal Input/Output Signals
RM0351 Hash processor (HASH) Table 180. HASH internal input/output signals Signal name Signal type Description hash_hclk2 digital input AHB2 bus clock hash_it digital output Hash processor global interrupt request hash_in_dma digital input/output DMA burst request/ acknowledge 29.3.3 About secure hash algorithms The hash processor is a fully compliant implementation of the secure hash algorithm defined by FIPS PUB 180-1 standard (SHA1), FIPS PUB 180-2 standard (SHA-224, SHA- 256) and the IETF RFC1321 publication (MD5).
Page 856: Figure 208. Message Data Swapping Feature
Hash processor (HASH) RM0351 HASH_DIN data endianness when bit swapping is disabled (DATATYPE=”00”) can be described as following: the least significant bit of the message has to be at MSB position in the first word entered into the hash processor, the 32nd bit of the bit string has to be at MSB position in the second word entered into the hash processor and so on.
Page 857 RM0351 Hash processor (HASH) 29.3.5 Message digest computing The hash processor sequentially processes 512-bit blocks when computing the message digest. Thus, each time 16 × 32-bit words (= 512 bits) have been written to the hash processor by the DMA or the CPU, the HASH automatically starts computing the message digest.
Page 858: Table 181. Hash Processor Outputs
Hash processor (HASH) RM0351 this digest computation. To launch the final digest computation, the software must set MDMAT bit to 0 before the last DMA transfer in order to trigger the final digest computation as it is done for single DMA transfers (see description before). Once computed, the digest can be read from the output registers as described in Table 181.
Page 859 RM0351 Hash processor (HASH) Example from FIPS PUB180-2 Let us assume that the original message is the ASCII binary-coded form of “abc”, of length L = 24: byte 0 byte 1 byte 2 byte 3 01100001 01100010 01100011 UUUUUUUU <-- 1st word written to HASH_DIN --> NBLW has to be loaded with the value 24: a “1”...
Page 860 Hash processor (HASH) RM0351 HMAC(message) = Hash((key | pad) XOR [0x5C] Hash((key | pad) XOR [0x36] message)) where: • represents a repetition of X n times, where n equal to the size of the underlying hash function data block that is 512 bits for SHA-1, SHA224, SHA-256, MD5 hash algorithms (i.e.
Page 861: Figure 209. Hash Save/Restore Mechanism
RM0351 Hash processor (HASH) 30313233 34353637 38393A3B 3C3D3E3F Message input (lenght=34, i.e. padding required). HASH_STR must be set to 0x20 to start message padding and inner hash computation (see ‘U’ as don’t care) 53616D70 6C65206D 65737361 67652066 6F72206B 65796C65 6E3D626C 6F636B6C 656EUUUU Outer hash key input (lenght=64, i.e.
Page 862 Hash processor (HASH) RM0351 Data loaded by software When the DMA is not used to load the message into the hash processor, the context can be saved only when no block processing is ongoing. This means that the user application must wait until DINIS = 1 (last block processed and input FIFO empty) or NBW ≠...
Page 863: Figure 210. Hash Interrupt Mapping Diagram
RM0351 Hash processor (HASH) Note: If the context swapping does not involve HMAC operations, the HASH_CSR38 to HASH_CSR53 registers do not need to be saved and restored. If the context swapping occurs between two blocks (the last block was completely processed and the next block has not yet been pushed into the IN FIFO, NBW = 000 in the HASH_CR register), the HASH_CSR22 to HASH_CSR37 registers do not need to be saved and restored.
Page 864: Table 182. Hash Interrupt Requests
Hash processor (HASH) RM0351 The above interrupt sources can be enabled or disabled individually by changing the mask bits in the HASH_IMR register. Setting the appropriate mask bit to 1 enables the interrupt. The status of the individual interrupt events can be read from the HASH_SR register. gives a summary of the available features.
Page 865 RM0351 Hash processor (HASH) 29.6 HASH registers The HASH core is associated with several control and status registers and five message digest registers. All these registers are accessible through 32-bit word accesses only, else an AHB2 error is generated. 29.6.1 HASH control register (HASH_CR) Address offset: 0x00 Reset value: 0x0000 0000...
Page 866 Hash processor (HASH) RM0351 Bits 11:8 NBW: Number of words already pushed This bitfield reflects the number of words in the message that have already been pushed into the IN FIFO. NBW increments (+1) when a write access is performed to the HASH_DIN register while DINNE = 1. It goes to zero when the INIT bit is written to 1 or when a digest calculation starts (DCAL written to 1 or DMA end of transfer).
Page 867 RM0351 Hash processor (HASH) Bit 3 DMAE: DMA enable 0: DMA transfers disabled 1: DMA transfers enabled. A DMA request is sent as soon as the hash core is ready to receive data. After this bit is set it is cleared by hardware while the last data of the message is written to the hash processor.
Page 868 Hash processor (HASH) RM0351 29.6.2 HASH data input register (HASH_DIN) Address offset: 0x04 Reset value: 0x0000 0000 HASH_DIN is the data input register. It is 32-bit wide. This register is used to enter the message by blocks of 512 bits. When the HASH_DIN register is programmed, the value presented on the AHB databus is ‘pushed’...
Page 869 RM0351 Hash processor (HASH) 29.6.3 HASH start register (HASH_STR) Address offset: 0x08 Reset value: 0x0000 0000 The HASH_STR register has two functions: • It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) •...
Page 870 Hash processor (HASH) RM0351 29.6.4 HASH digest registers (HASH_HR0..7) These registers contain the message digest result named as follows: H0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description In this case, the HASH_H5 to HASH_H7 register is not used, and it is read as zero. A, B, C and D, respectively, in the MD5 algorithm description In this case, the HASH_H4 to HASH_H7 register is not used, and it is read as zero.
Page 871 RM0351 Hash processor (HASH) HASH_HR2 Address offset: 0x14 and 0x318 Reset value: 0x0000 0000 HASH_HR3 Address offset: 0x18 and 0x31C Reset value: 0x0000 0000 HASH_HR4 Address offset: 0x1C and 0x320 Reset value: 0x0000 0000 HASH_HR5 Address offset: 0x324 Reset value: 0x0000 0000 DocID024597 Rev 5 871/1830...
Page 872 Hash processor (HASH) RM0351 HASH_HR6 Address offset: 0x328 Reset value: 0x0000 0000 HASH_HR7 Address offset: 0x32C Reset value: 0x0000 0000 Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these registers are forced to their reset values. 29.6.5 HASH interrupt enable register (HASH_IMR) Address offset: 0x20...
Page 873 RM0351 Hash processor (HASH) 29.6.6 HASH status register (HASH_SR) Address offset: 0x24 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 874 Hash processor (HASH) RM0351 29.6.7 HASH context swap registers (HASH_CSRx) These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task.
Page 875: Table 184. Hash Register Map And Reset Values
RM0351 Hash processor (HASH) 29.6.8 HASH register map Table 9 gives the summary HASH register map and reset values. Table 184. HASH register map and reset values Register size Register name Offset and reset value HASH_CR 0x00 Reset value HASH_DIN DATAIN 0x04 Reset value...
Page 876 Advanced-control timers (TIM1/TIM8) RM0351 Advanced-control timers (TIM1/TIM8) 30.1 TIM1/TIM8 introduction The advanced-control timers (TIM1/TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 877: Figure 211. Advanced-Control Timer Block Diagram
RM0351 Advanced-control timers (TIM1/TIM8) Figure 211. Advanced-control timer block diagram 1. See Figure 255: Break and Break2 circuitry overview for details DocID024597 Rev 5 877/1830...
Page 878 Advanced-control timers (TIM1/TIM8) RM0351 30.3 TIM1/TIM8 functional description 30.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 879: Figure 212. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0351 Advanced-control timers (TIM1/TIM8) Figure 212. Counter timing diagram with prescaler division change from 1 to 2 Figure 213. Counter timing diagram with prescaler division change from 1 to 4 DocID024597 Rev 5 879/1830...
Page 880 Advanced-control timers (TIM1/TIM8) RM0351 30.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 881: Figure 214. Counter Timing Diagram, Internal Clock Divided By 1
RM0351 Advanced-control timers (TIM1/TIM8) Figure 214. Counter timing diagram, internal clock divided by 1 Figure 215. Counter timing diagram, internal clock divided by 2 DocID024597 Rev 5 881/1830...
Page 882: Figure 216. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1/TIM8) RM0351 Figure 216. Counter timing diagram, internal clock divided by 4 Figure 217. Counter timing diagram, internal clock divided by N 882/1830 DocID024597 Rev 5...
Page 883: Figure 218. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 218. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 219. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) DocID024597 Rev 5 883/1830...
Page 884 Advanced-control timers (TIM1/TIM8) RM0351 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 885: Figure 220. Counter Timing Diagram, Internal Clock Divided By 1
RM0351 Advanced-control timers (TIM1/TIM8) Figure 220. Counter timing diagram, internal clock divided by 1 Figure 221. Counter timing diagram, internal clock divided by 2 DocID024597 Rev 5 885/1830...
Page 886: Figure 222. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1/TIM8) RM0351 Figure 222. Counter timing diagram, internal clock divided by 4 Figure 223. Counter timing diagram, internal clock divided by N 886/1830 DocID024597 Rev 5...
Page 887: Figure 224. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0351 Advanced-control timers (TIM1/TIM8) Figure 224. Counter timing diagram, update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 888: Figure 225. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1/TIM8) RM0351 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 889: Figure 226. Counter Timing Diagram, Internal Clock Divided By 2
RM0351 Advanced-control timers (TIM1/TIM8) Figure 226. Counter timing diagram, internal clock divided by 2 Figure 227. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 DocID024597 Rev 5 889/1830...
Page 890: Figure 228. Counter Timing Diagram, Internal Clock Divided By N
Advanced-control timers (TIM1/TIM8) RM0351 Figure 228. Counter timing diagram, internal clock divided by N Figure 229. Counter timing diagram, update event with ARPE=1 (counter underflow) 890/1830 DocID024597 Rev 5...
Page 891: Figure 230. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 230. Counter timing diagram, Update event with ARPE=1 (counter overflow) 30.3.3 Repetition counter Section 30.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero.
Page 892: Figure 231. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timers (TIM1/TIM8) RM0351 In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the overflow.
Page 893: Figure 232. External Trigger Input Block
RM0351 Advanced-control timers (TIM1/TIM8) 30.3.4 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 30.3.5) • trigger for the slave mode (see Section 30.3.26) •...
Page 894: Figure 234. Tim8 Etr Input Circuitry
Advanced-control timers (TIM1/TIM8) RM0351 Figure 234. TIM8 ETR input circuitry 894/1830 DocID024597 Rev 5...
Page 895: Figure 235. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0351 Advanced-control timers (TIM1/TIM8) 30.3.5 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed...
Page 896: Figure 236. Ti2 External Clock Connection Example
Advanced-control timers (TIM1/TIM8) RM0351 Figure 236. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 897: Figure 237. Control Circuit In External Clock Mode 1
RM0351 Advanced-control timers (TIM1/TIM8) Figure 237. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 238 gives an overview of the external trigger input block.
Page 898: Figure 239. Control Circuit In External Clock Mode 2
Advanced-control timers (TIM1/TIM8) RM0351 As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 899: Figure 240. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0351 Advanced-control timers (TIM1/TIM8) 30.3.6 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 240 Figure 243 give an overview of one Capture/Compare channel.
Page 900: Figure 241. Capture/Compare Channel 1 Main Circuit
Advanced-control timers (TIM1/TIM8) RM0351 Figure 241. Capture/compare channel 1 main circuit Figure 242. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) 1. OCxREF, where x is the rank of the complementary channel 900/1830 DocID024597 Rev 5...
Page 901: Figure 243. Output Stage Of Capture/Compare Channel (Channel 4)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 243. Output stage of capture/compare channel (channel 4) Figure 244. Output stage of capture/compare channel (channel 5, idem ch. 6) 1. Not available externally. The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
Page 902 Advanced-control timers (TIM1/TIM8) RM0351 30.3.7 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 903: Figure 245. Pwm Input Mode Timing
RM0351 Advanced-control timers (TIM1/TIM8) 30.3.8 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 904 Advanced-control timers (TIM1/TIM8) RM0351 forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the TIMx_CCMRx register.
Page 905: Figure 246. Output Compare Mode, Toggle On Oc1
RM0351 Advanced-control timers (TIM1/TIM8) shadow register is updated only at the next update event UEV). An example is given in Figure 246. Figure 246. Output compare mode, toggle on OC1 30.3.11 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 906: Figure 247. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1/TIM8) RM0351 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 880. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 907: Figure 248. Center-Aligned Pwm Waveforms (Arr=8)
RM0351 Advanced-control timers (TIM1/TIM8) Center-aligned mode (up/down counting) on page 887. Figure 248 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Page 908 Advanced-control timers (TIM1/TIM8) RM0351 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 909: Figure 249. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle
RM0351 Advanced-control timers (TIM1/TIM8) Figure 249. Generation of 2 phase-shifted PWM signals with 50% duty cycle 30.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers.
Page 910: Figure 250. Combined Pwm Mode On Channel 1 And 3
Advanced-control timers (TIM1/TIM8) RM0351 Figure 250. Combined PWM mode on channel 1 and 3 30.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The OC5REF signal is used to define the resulting combined signal.
Page 911: Figure 251. 3-Phase Combined Pwm Signals With Multiple Trigger Pulses Per Period
RM0351 Advanced-control timers (TIM1/TIM8) Figure 251. 3-phase combined PWM signals with multiple trigger pulses per period The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals. Please refer to Section 30.3.27: ADC synchronization for more details. 30.3.15 Complementary outputs and dead-time insertion The advanced-control timers (TIM1/TIM8) can output two complementary signals and...
Page 912: Figure 252. Complementary Output With Dead-Time Insertion
Advanced-control timers (TIM1/TIM8) RM0351 Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: •...
Page 913: Figure 254. Dead-Time Waveforms With Delay Greater Than The Positive Pulse
RM0351 Advanced-control timers (TIM1/TIM8) Figure 254. Dead-time waveforms with delay greater than the positive pulse The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 30.4.18: TIM1/TIM8 break and dead- time register (TIMx_BDTR) for delay calculation.
Page 914 Advanced-control timers (TIM1/TIM8) RM0351 The output enable signal and output levels during break are depending on several control bits: – the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event. –...
Page 915: Figure 255. Break And Break2 Circuitry Overview
RM0351 Advanced-control timers (TIM1/TIM8) All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 255 below. Figure 255. Break and Break2 circuitry overview Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled.
Page 916 Advanced-control timers (TIM1/TIM8) RM0351 When one of the breaks occurs (selected level on one of the break inputs): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off.
Page 917: Figure 256. Various Output Behavior In Response To A Break Event On Brk (Ossi = 1)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 256. Various output behavior in response to a break event on BRK (OSSI = 1) DocID024597 Rev 5 917/1830...
Page 918: Table 185. Behavior Of Timer Outputs Versus Brk/Brk2 Inputs
Advanced-control timers (TIM1/TIM8) RM0351 The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 185.
Page 919: Figure 258. Pwm Output State Following Brk Assertion (Ossi=0)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 258. PWM output state following BRK assertion (OSSI=0) 30.3.17 Bidirectional break inputs Beside regular digital break inputs and internal break events coming from the comparators, the timer 1 and 8 are featuring bidirectional break inputs/outputs combining the two sources, as represented on Figure 259.
Page 920: Figure 260. Clearing Timx Ocxref
Advanced-control timers (TIM1/TIM8) RM0351 30.3.18 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs.
Page 921: Figure 261. 6-Step Generation, Com Example (Ossr=1)
RM0351 Advanced-control timers (TIM1/TIM8) 30.3.19 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 922: Figure 262. Example Of One Pulse Mode
Advanced-control timers (TIM1/TIM8) RM0351 30.3.20 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 923 RM0351 Advanced-control timers (TIM1/TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 924: Figure 263. Retriggerable One Pulse Mode
Advanced-control timers (TIM1/TIM8) RM0351 Figure 263. Retriggerable one pulse mode 30.3.22 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’...
Page 925: Table 186. Counting Direction Versus Encoder Signals
RM0351 Advanced-control timers (TIM1/TIM8) Table 186. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite signal (TI1FP1 Active edge for TI2, Rising Falling Rising Falling TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 926: Figure 265. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
Advanced-control timers (TIM1/TIM8) RM0351 Figure 265 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 265. Example of encoder interface mode with TI1FP1 polarity inverted. The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 927: Figure 266. Measuring Time Interval Between Edges On 3 Signals
RM0351 Advanced-control timers (TIM1/TIM8) 30.3.24 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 928 Advanced-control timers (TIM1/TIM8) RM0351 Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, •...
Page 929: Figure 267. Example Of Hall Sensor Interface
RM0351 Advanced-control timers (TIM1/TIM8) Figure 267. Example of Hall sensor interface DocID024597 Rev 5 929/1830...
Page 930: Figure 268. Control Circuit In Reset Mode
Advanced-control timers (TIM1/TIM8) RM0351 30.3.26 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 931: Figure 269. Control Circuit In Gated Mode
RM0351 Advanced-control timers (TIM1/TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 932: Figure 270. Control Circuit In Trigger Mode
Advanced-control timers (TIM1/TIM8) RM0351 Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 933: Figure 271. Control Circuit In External Clock Mode 2 + Trigger Mode
RM0351 Advanced-control timers (TIM1/TIM8) Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
Page 934 Advanced-control timers (TIM1/TIM8) RM0351 30.3.27 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: –...
Page 935 RM0351 Advanced-control timers (TIM1/TIM8) This is done in the following steps: Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
Page 936 Advanced-control timers (TIM1/TIM8) RM0351 30.4 TIM1/TIM8 registers Refer to for a list of abbreviations used in register descriptions. 30.4.1 TIM1/TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] UDIS Bits 15:12 Reserved, must be kept at reset value.
Page 937 RM0351 Advanced-control timers (TIM1/TIM8) Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 938 Advanced-control timers (TIM1/TIM8) RM0351 Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2).
Page 939 RM0351 Advanced-control timers (TIM1/TIM8) Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 940 Advanced-control timers (TIM1/TIM8) RM0351 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 941 RM0351 Advanced-control timers (TIM1/TIM8) Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4...
Page 942: Table 187. Timx Internal Trigger Connection
Advanced-control timers (TIM1/TIM8) RM0351 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 943 RM0351 Advanced-control timers (TIM1/TIM8) Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled...
Page 944 Advanced-control timers (TIM1/TIM8) RM0351 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 30.4.5...
Page 945 RM0351 Advanced-control timers (TIM1/TIM8) Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 B2IF: Break 2 interrupt flag...
Page 946 Advanced-control timers (TIM1/TIM8) RM0351 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 947 RM0351 Advanced-control timers (TIM1/TIM8) Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 948 Advanced-control timers (TIM1/TIM8) RM0351 Bits16 OC1M[3]: Output Compare 1 mode - bit 3 Refer to OC1M description on bits 6:4 Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 949 RM0351 Advanced-control timers (TIM1/TIM8) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 950 Advanced-control timers (TIM1/TIM8) RM0351 Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 951 RM0351 Advanced-control timers (TIM1/TIM8) Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 952 Advanced-control timers (TIM1/TIM8) RM0351 Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC4M[3]: Output Compare 4 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bit 16 OC3M[3]: Output Compare 3 mode - bit 3 Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable...
Page 953 RM0351 Advanced-control timers (TIM1/TIM8) Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC.
Page 954 Advanced-control timers (TIM1/TIM8) RM0351 Bit 9 CC3P: Capture/Compare 3 output polarity Refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable Refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 complementary output polarity Refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable Refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description...
Page 955 RM0351 Advanced-control timers (TIM1/TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. 00: non-inverted/rising edge.
Page 956: Table 188. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
Advanced-control timers (TIM1/TIM8) RM0351 Table 188. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output disabled (not driven by the timer: Hi-Z) OCx=0, OCxN=0 Output disabled (not driven OCxREF + Polarity...
Page 957 RM0351 Advanced-control timers (TIM1/TIM8) 30.4.10 TIM1/TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Re s. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Page 958 Advanced-control timers (TIM1/TIM8) RM0351 30.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[15:0] Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 959 RM0351 Advanced-control timers (TIM1/TIM8) 30.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
Page 960 Advanced-control timers (TIM1/TIM8) RM0351 30.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
Page 961 RM0351 Advanced-control timers (TIM1/TIM8) Bit 24 BK2E: Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 255: Break and Break2 circuitry overview). 0: Break2 function disabled 1: Break2 function enabled Note: The BRKIN2 must only be used with OSSR = OSSI = 1.
Page 962 Advanced-control timers (TIM1/TIM8) RM0351 Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
Page 963 RM0351 Advanced-control timers (TIM1/TIM8) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 30.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER)).
Page 964 Advanced-control timers (TIM1/TIM8) RM0351 Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
Page 965 RM0351 Advanced-control timers (TIM1/TIM8) Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 966 Advanced-control timers (TIM1/TIM8) RM0351 30.4.22 TIM8 option register 1 (TIM8_OR1) Address offset: 0x50 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_ Res. Res. Res. Res. Res. Res. Res.
Page 967 RM0351 Advanced-control timers (TIM1/TIM8) OC6M[2:0] OC6FE Res. Res. OC5M[2:0] OC5PE OC5FE Res. Res. Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC6M[3]: Output Compare 6 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bit 16 OC5M[3]: Output Compare 5 mode - bit 3 Bit 15 OC6CE: Output compare 6 clear enable Bits 14:12 OC6M: Output compare 6 mode...
Page 968 Advanced-control timers (TIM1/TIM8) RM0351 Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2).
Page 969 RM0351 Advanced-control timers (TIM1/TIM8) 30.4.26 TIM1 option register 2 (TIM1_OR2) Address offset: 0x60 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BKDF1 ETRSEL[1:0] Res. Res. BKINP Res. Res. Res. Res.
Page 970 Advanced-control timers (TIM1/TIM8) RM0351 Bit 8 BKDF1BK0E: BRK dfsdm1_break[0] enable This bit enables the dfsdm1_break[0] for the timer’s BRK input. dfsdm1_break[0] output is ‘ORed’ with the other BRK sources. 0: dfsdm1_break[0] input disabled 1: dfsdm1_break[0] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 971 RM0351 Advanced-control timers (TIM1/TIM8) Bit 11 BK2CMP2P: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 972 Advanced-control timers (TIM1/TIM8) RM0351 Bit 0 BK2INE: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 973 RM0351 Advanced-control timers (TIM1/TIM8) Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 974 Advanced-control timers (TIM1/TIM8) RM0351 BK2C BK2C BK2IN BK2DF1 BK2CMP BK2CM Res. Res. Res. Res. Res. Res. Res. Res. Res. BK2INE MP2P MP1P BK3E Bits 31:12 Reserved, must be kept at reset value Bit 11 BK2CMP2P: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2 polarity bit.
Page 975 RM0351 Advanced-control timers (TIM1/TIM8) Bit 0 BK2INE: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 976: Table 189. Tim1 Register Map And Reset Values
Advanced-control timers (TIM1/TIM8) RM0351 30.4.30 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 189. TIM1 register map and reset values Offset Register TIM1_CR1 [1:0] [1:0] 0x00 Reset value TIM1_CR2 MMS2[3:0] [2:0] 0x04 Reset value...
Page 977 RM0351 Advanced-control timers (TIM1/TIM8) Table 189. TIM1 register map and reset values (continued) Offset Register TIM1_PSC PSC[15:0] 0x28 Reset value TIM1_ARR ARR[15:0] 0x2C Reset value TIM1_RCR REP[15:0] 0x30 Reset value TIM1_CCR1 CCR1[15:0] 0x34 Reset value TIM1_CCR2 CCR2[15:0] 0x38 Reset value TIM1_CCR3 CCR3[15:0] 0x3C...
Page 978 Advanced-control timers (TIM1/TIM8) RM0351 Table 189. TIM1 register map and reset values (continued) Offset Register TIM1_CCR6 CCR6[15:0] 0x5C Reset value ETRSEL TIM1_OR2 [2:0] 0x60 Reset value TIM1_OR3 0x64 Reset value Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
Page 979: Table 190. Tim8 Register Map And Reset Values
RM0351 Advanced-control timers (TIM1/TIM8) 30.4.31 TIM8 register map TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 190. TIM8 register map and reset values Offset Register TIM8_CR1 [1:0] [1:0] 0x00 Reset value TIM8_CR2 MMS2[3:0] [2:0] 0x04 Reset value...
Page 980 Advanced-control timers (TIM1/TIM8) RM0351 Table 190. TIM8 register map and reset values (continued) Offset Register TIM8_PSC PSC[15:0] 0x28 Reset value TIM8_ARR ARR[15:0] 0x2C Reset value TIM8_RCR REP[15:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIM8_CCR2 CCR2[15:0] 0x38 Reset value TIM8_CCR3 CCR3[15:0] 0x3C...
Page 981 RM0351 Advanced-control timers (TIM1/TIM8) Table 190. TIM8 register map and reset values (continued) Offset Register TIM8_CCR6 CCR6[15:0] 0x5C Reset value ETRSEL TIM8_OR2 [2:0] 0x60 Reset value TIM8_OR3 0x64 Reset value Refer to Section 2.2.2 on page 75 for the register boundary addresses. DocID024597 Rev 5 981/1830...
Page 982 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 31.1 TIM2/TIM3/TIM4/TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 983: Figure 272. General-Purpose Timer Block Diagram
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 272. General-purpose timer block diagram DocID024597 Rev 5 983/1830 1052...
Page 984 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 31.3 TIM2/TIM3/TIM4/TIM5 functional description 31.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up, down or both up and down but also down or both up and down.
Page 985: Figure 273. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 273. Counter timing diagram with prescaler division change from 1 to 2 Figure 274. Counter timing diagram with prescaler division change from 1 to 4 DocID024597 Rev 5 985/1830 1052...
Page 986: Figure 275. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 31.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 987: Figure 276. Counter Timing Diagram, Internal Clock Divided By 2
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 276. Counter timing diagram, internal clock divided by 2 Figure 277. Counter timing diagram, internal clock divided by 4 DocID024597 Rev 5 987/1830 1052...
Page 988: Figure 278. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 278. Counter timing diagram, internal clock divided by N Figure 279. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) 988/1830 DocID024597 Rev 5...
Page 989: Figure 280. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 280. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
Page 990: Figure 281. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 281. Counter timing diagram, internal clock divided by 1 Figure 282. Counter timing diagram, internal clock divided by 2 990/1830 DocID024597 Rev 5...
Page 991: Figure 283. Counter Timing Diagram, Internal Clock Divided By 4
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 283. Counter timing diagram, internal clock divided by 4 Figure 284. Counter timing diagram, internal clock divided by N DocID024597 Rev 5 991/1830 1052...
Page 992: Figure 285. Counter Timing Diagram, Update Event When Repetition Counter
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 285. Counter timing diagram, Update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 993: Figure 286. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 994: Figure 287. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 287. Counter timing diagram, internal clock divided by 2 Figure 288. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. 994/1830 DocID024597 Rev 5...
Page 995: Figure 289. Counter Timing Diagram, Internal Clock Divided By N
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 289. Counter timing diagram, internal clock divided by N Figure 290. Counter timing diagram, Update event with ARPE=1 (counter underflow) DocID024597 Rev 5 995/1830 1052...
Page 996: Figure 291. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 291. Counter timing diagram, Update event with ARPE=1 (counter overflow) 31.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) •...
Page 997: Figure 292. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 292. Control circuit in normal mode, internal clock divided by 1 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 293.
Page 998: Figure 294. Control Circuit In External Clock Mode 1
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
Page 999: Figure 295. External Trigger Input Block
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 295. External trigger input block For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register...
Page 1000: Figure 296. Control Circuit In External Clock Mode 2
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 296. Control circuit in external clock mode 2 31.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).

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