Tr Board; Cw Module - Mindray DC-70 Service Manual

4.2.2

TR Board

TR board has the capacity for basic ultrasound services. Single board fulfills 64 channels'
transmitting and receiving.
Beam data sends back to the engine board via the serial and the addition from one board to another.
Engine board controls TR board via the asteroidal.
Pencil Probe
Probe Board
Adjacent TR board on
frond end side, if exists.
Adjacent TR board on
back end side, if exists.
Engine Board
clock
DSP FPGA
Mother
Board
DC-DC board
PHV board
The functions of TR board:
Transmitting: in accomplishing the transmitting focus of the entire unit, TR_FPGA controls 64

channels on a single board to send high-voltage ultrasound signal to the probe.
Receiving: in accomplishing the receiving focus, TR_FPGA controls 64 channels on a single

board to receive ultrasound echo signal of the probe.
Beam data processing: is to receive the beam data which is weighted from the previous TR

board, and passes to the next TR board. Finally, it adds all beam data on array channels
together and sends it to engine board's DSP_FPGA.
CW: it refers to the CW mini board on TR_A board. It fulfills the adjustment of CW based on

AFE plan. The adjustment result will send to TR_FPGA.
Pencil probe support: is available to fulfill the switch on TR_A board between the receiving

channel of the pencil probe and the regular receiving channel. It finally connects to CW mini
board.
Control: it is necessary to take controls to accomplish the functions, such as: Download the

parameters to TR_FPGA in real-time as DSP_FPGA controls the interface; Delay control in
transmitting; Receive the gain control of the clip, etc.
4.2.3

CW Module

CW is an option. The transmitting circuit of CW shares the transmitting circuit with B/Color mode.
The receiving circuit of CW is more than B/Color mode's.
4-4 Product Principle
Pen Probe TX/RX
TR Board
connect to TR_A slot
64ch TX/RX
present
data bus
JTAG data
present
data bus
JTAG data
present
TX circuits
reset
reset status
JTAG downstream
ctrl
control bus
data bus (from TR_A)
XCVR_REFCLK
AFE_CLK
TX_CLK
BF_CLK
RATE
ATGC bus
slot ID
power
between local and bus
scan status
Figure 4-4 Schematic diagram of TR board
TX-RX switch
including pen probe TX-RX switch
64ch Pen Prb
TX RX
RX circuits
switch
ctrl
ctrl
TR
FPGA
TX_CLK BF_CLK
ctrl
Clock distribution
ATGC
Including switch
ATGC
64ch
RX
CW
power
RX
data
present/ID
RX data
AFE_CLK
CW mini
board
(TR_A)