Dp++ Port (Cn22) - Asus AAEON GENE-CML5 User Manual

2.4.19

DP++ Port (CN22)

Pin Pin Name
1 DDI1_TX0_DP
2 GND
3 DDI1_TX0_DN
4 DDI1_TX1_DP
5 GND
6 DDI1_TX1_DN
7 DDI1_TX2_DP
8 GND
9 DDI1_TX2_DN
10 DDI1_TX3_DP
11 GND
12 DDI1_TX3_DN
13 DDI1_AUX_EN
14 GND
15 DDI1_DP_CTRLCLK_AUX_DP
16 GND
17 DDI1_DP_CTRLDATA_AUX_DN DIFF
18 DDI1_DP_HPD
19 GND
20 +V3P3S
Chapter 2 – Hardware Information
Signal Type Signal Level
DIFF
GND
DIFF
DIFF
GND
DIFF
DIFF
GND
DIFF
DIFF
GND
DIFF
IO
GND
DIFF
GND
DDI1_DP_HPD
GND
PWR
30