Sony DVS-7200A Maintenance Manual page 77

3-2. Switch Settings on the CPU-246 Board and LEDs Description (BKDS-7015)
TP1 (H9) : CK40M
The 40 MHz square waves are visible when the system is operating normally.
TP2 (H9) : LCK40M
The 40 MHz square waves are visible when the system is operating normally. However, the waveform at
this point has opposite polarity to that of TP1 on the CPU-246 board.
TP3 (R11) : RESET
The system reset signal is visible.
TP4 (H11) : AS
The AS signal which is generated by the main CPU (IC8 on the CPU-246 board) is visible.
TP5 (H11) : STERM
The STERM signal which is generated by the main CPU (IC8 on the CPU-246 board) is visible.
TP6 (G6) : DSACK0
The DSACK0 signal which is generated by the MDEC (IC10 on the CPU-246 board) is visible.
TP7 (G6) : DSACK1
The DSACK1 signal which is generated by the MDEC (IC10 on the CPU-246 board) is visible.
TP8 and TP9 (J11) : M3 and M2
Not used.
TP10 (K9) : VD
The vertical sync signal which is generated by the reference signal supplied from the DVS-7200A is
visible. The sync signal of 16 ms rate is visible on the 525 scanning lines. The sync signal of 20 ms rate
is visible on the 625 scanning lines.
TP11 (K9) : VDSNS
The "H" level appears when the reference signal from the DVS-7200A is received. The "L" level appears
if the reference signal can not be received.
TP12 and TP13 (J11) : S0 and S1
Not used.
3-9
DVS-7200AE MMP1