Table of Contents
Advertisement
gated onto the ZD bus by the DI-EN signal during
Z8~
read
operations (RD-D) except on-board PROM reads and during interrupt
operations (XINTA).
The ZD bus is gated onto the control panel
bus whenever a control panel operation is not in progress.
The
ZD bus is gated onto the
S-10~
data output bus (D00-D07) by DO-EN
during memory write and output operations of the Z80.
The data
from the on-board PROM is gated onto the ZD bus directly by the
PROM-EN signal during on-board PROM read operations.
-ADDRESS BUS
The sixteen
~adress
lines from the
Z8~
(ZA~-ZAI5)
are connected
through drivers to the
S-l~~
address bus
(A~-AI5)
except during
input/output operations.
In this latter case, if the address
mirroring feature is enabled then the low order 8 address bits
from the
Z8~
are gated onto both the top and bottom 8 bits of the
S-10~
address bus.
This feature allows simulation of 8080 I/O
operations for systems that include
S-l~~
boards that take
advantage of this
8~8~
characteristic.
VECTORED INTERRUPTS
-The on-board vectored interrupt capability provides for
Cl
priority response to 8 interrupt levels.
Whenever the Z80
generates an interrupt acknowledge condition (INTA), the state of
the eight interrupt request lines (VI0-VI7) is latched (8B, 8C)
and the latch outputs are fed to a priority encoder (8D).
The
three encoder outputs indicate the highest priority pendi.ng
interrupt request.
These lines are merged with "I" bits at the
mUltiplexors (2D, IE) to provide the correct RST instruction on
the
Z8~
data bus (ZD0-ZD7) when the multiplexor is enabled by MX-
EN.
The INT-RQ signal out of the encoder indicates that at least
one interrupt request level is pending and causes an interrupt
request to the Z80 if on-board interrupts are enabled (OBIE).
AUTO-JUMP
-The auto-jump feature causes an automatic jump to a jumpE!r-wire-
specified address (2E) upon power-an or reset.
The register at
4G is configured to be a four state"counter.
The restart
condition (RST) resets the register and each successive read
cycle (RD) causes the register to shift to the next statE! until
the auto-jump sequence is done in the fourth state (AUJ-DONE).
The first three states cause the three bytes of an unconditional
jump instruction to the specified address to be multiplexed (IE,
2D) onto the Z80 data bus (ZD0-ZD7). _The AUJ-DONE signal
disables the auto-jump feature until the next restart condition
reinitiates the entire sequence.
The AUJS signal causes the two
address bytes to be selected by the multiplexors (IE, 2D) during
the second and third states.
The jump opcode is generated during
the first state as a special case of the interrupt logic which
generates a JMP instruction rather than an RST.
-North Star Z80A PROCESSOR BOARD
26
• - • +-
-.,.
....
..
::~:
-
Advertisement
Table of Contents
