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THEORY OF OPERATION
Z80A AND CONTROL CIRCUITS
The primary function of the ZPB is to interface the Z80A
processor to the S-100 bus with its control lines.
The following
list gives the S-100 control signals along with pertinent
comments about their use and derivation.
A slash at the end of a
name indicates that the signal is active low (negative logic).
Pin Signal
1111
Disables the address line drivers onto the 5-100
bus when true.
Disables drivers for PSYNC, PDBIN, PWAIT, PWR,
PMREQ, and PRFSH when true.
Disables the data output bus (DO) drivers when
true.
True during a memory write operation of the Z80.
This signal should be disconnected if the ZPB is
used in a system where MWRITE is generated on the
control panel board or some other board.
Indicates that the Z80 is reading the DI bus
during a memory read, input, or interrupt
acknowledge operation.
The hold acknowledge response by the Z80 to a hold
request (PHOLD).
Indicates that the Z80 execution
is suspended and that a DMA bus operation may
begin.
Used to request the Z80 to suspend activity and
allow direct memory access by a peripheral device.
Interrupt request line to the Z80 from the on-
board
Ve~tored
interrupt logic or from some other
board.
This signal ("interrupts enabled" on 8080 systems)
is normally true but goes false momentarily during
interrupt acknowledge sequences thus providing an
edge to latch the VI lines for boards such as the
IMSAI PIC-8.
Memory cycle request signal from the Z80.
Non-maskable interrupt request to Z80.
System reset synchronized to the Z80 clock.
True
when the RESET switch is depressed or momentarily
when power first comes on.
When false, causes the Z80 to WAIT.
Usually
generated by memory boards to extend memory cycles
for slow access time memories.
See also XRDY.
Description
MWRITE
PMREQ/
PNMI
POC/
PHOLD/
PINT/
PHLDA
PRDY
PINTE/
PDBIN
ADDR-DSBL/
CC-DSBL/
DO-DSBL/
72
28
73
22
78
74
65
12
99
19
23
-68
North Star Z80A PROCESSOR BOARD
24
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