NorthStar Z80 Manual page 26

75 PRESET/
66 PRFSH/
76 -PSYNC
27 PWAIT
77 PWR/
71 RUN
48
SHLTA
46 SINP
96
SIN'tA
47 SMEMR
44 SMI
DATA BUS
Connected to the reset switch.
Dynamic memory refresh signal generated by the
Z89.
This signal is true between memory and/or 10
cycles of the Z89. Usually one clock cycle wide
(sometimes two). Usually used by wait state
counters on memory boards.
True when the Z89 is in the wait state caused by
PRDY or XRDY.
Timing signal generated during memory write and
output operattons which indicates that valid data
is on the DO bus.
Signal generated by a control panel to indicate
the processor should be in run mode
True if the Z89 is executing a halt instruction.
True during an input operation.
True during an interrupt-acknowledgeoperation.-~
True during a memory read operation.
True during the instruction opcode fetch portion
of each instruction cycle of the Z89. For
instructions with two opcode bytes, this signal is
true twice.
True during output operations.
Generated by a control panel to indicate that the
Z89 should be iD run mode during a single step
operation.
Always false. On 8989 systems indicates that a
stack reference cycle is in progress.
Disables 01 bus receivers and-enables CP bus
receivers. Used during input of sense switches
from a control panel.
Disables drivers for SMEMR, SWO, SINP, SHLTA, SMl,
SOUT, and SINTA.
True when the Z89 is sending data out on the DO
bus.
Causes the Z89 to enter wait mode when false.
Usually generated by a control panel to cause a
control panel stop. There has been some conflict
of use between this signal and PRDY so care should
be taken to guarantee that drivers on this line
from different boards cannot be simultaneously
active.
-NOTE: This and the following sections will be more meaningful if
the schematic drawings are referenced while they are read. The
capitalized signal names refer to names used in the drawings.
-The Z89 data bus (ZD9-ZD7) is the 8 data bits directly connected
to the Z89 processor. The data bus from the control panel (CP9-
CP7) is gated onto the ~D bus by the CPIN-EN signal during
control panel operations. The S-H'19 data input bus, (019-017) is
25 North Star Z89A PROCESSOR BOARD