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NXP Semiconductors QorIQ LS1028A Reference Manual

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NXP Semiconductors
Document Number: LS1028ARDBRM
Reference Manual
Rev. b, 11/2018
QorIQ LS1028A Reference Design Board
Reference Manual
COMPANY CONFIDENTIAL

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  • Page 1 NXP Semiconductors Document Number: LS1028ARDBRM Reference Manual Rev. b, 11/2018 QorIQ LS1028A Reference Design Board Reference Manual COMPANY CONFIDENTIAL...

  • Page 2: Table Of Contents

    4.9 Control and Status Registers....................66 4.10 General Control (CTL)......................66 4.11 Auxiliary (AUX)........................67 4.12 System Status (STAT_SYS)....................67 4.13 Alarm (ALARM)........................68 4.14 Presence Detect 1 (STAT_PRES1)..................69 QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 3 4.59 Interrupt Drive 5 (IRQDRV5)....................107 4.60 Core Management Space Registers..................107 4.61 Core Management Address (CMSA)................... 108 4.62 Core Management Data (CMSD)..................109 Appendix A Revision History................110 QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 4: Chapter 1 Ls1028Ardb Overview

    LS1028A reference design board (LS1028ARDB) is a computing, evaluation, development, and test platform ® ® supporting the QorIQ LS1028A processor, which is a dual-core Arm Cortex -v8 A72 processor with frequency up to 1.3 GHz. The LS1028ARDB is optimized to support SGMII (1 Gbit/s), QSGMII (5 Gbit/s), PCIe x1 (8 Gbit/s), and SATA (6 Gbit/s) over high- speed SerDes ports, USB 3.0, DisplayPort, and also a high-bandwidth DDR4 memory.
  • Page 5 Pulse width modulation QSGMII Quad serial gigabit media independent interface QSPI Quad serial peripheral interface Reset configuration word Real time clock Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 6: Related Documentation

    QorIQ LS1028A Chip Errata Lists the details of all known silicon errata for the LS1028A Contact FAE / sales representative Table continues on the next page...

  • Page 7: Block Diagrams

    Layerscape LS1028A BSP This document explains how to use the QorIQ LS1028A BSP, Contact FAE / sales which is a Linux-based development kit, to evaluate and explore...
  • Page 8 LS1028ARDB Overview Figure 1. LS1028A block diagram The figure below shows the LS1028ARDB block diagram. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 9: Board Features

    S AI4 TX LINE OUT Audio LINEOUT (for S peakers) Figure 2. LS1028ARDB block diagram 1.4 Board features The table below lists the features of the LS1028ARDB. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 10 Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near field communications (NFC) controller Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 11 • Supports link transfer rates of up to HBR2 (5.4 Gbit/s) LS1043A processor) Clocks Differential system 100 MHz clock (DIFF_SYSCLK) Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 12 • Package type is Flip Chip, Plastic-ball, Grid Array (FC-PBGA), 17 mm x 17 mm • Socket and heat sink are included Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 13 • Manages the following: — System reset sequencing — SoC POR configuration at reset • Implements registers for system control and monitoring • General fault monitoring and logging QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 14: Chapter 2 Ls1028Ardb Functional Description

    2.1 Processor ® ® The LS1028ARDB board is based on the QorIQ LS1028A processor having two Arm Cortex - A72 processor cores. The LS1028ARDB board supports as many features of the LS1028A as possible. In addition, the LS1028ARDB board supports an LS1043A interposer that allows early evaluation of the board with limited features and restrictions.

  • Page 15: Power Supplies

    MIKROBUS CONNECTORS LEDs MISC PARTS (BUFFERS & TRANSLATORS USB_HVDD L S1028 USB _HVDD 3.3V @ .45 A LPF x2 Figure 3. Power supplies - Part 1 QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 16 2.2.1 Primary power supply The LS1028ARDB is powered up through an external 12 V DC power adapter. The specifications of the DC adapter are as follows: QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 17 DDR4 DRAM memories Semiconductors LS1028A DRAM controller core and I/O VTT_0V6 0.6 V at 3 A Address and control bus termination supply Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 18 Filtered 1V8 also powers LS1028A power supplies: AVDD_CGA1, AVDD_CGA2, AVDD_PLAT, DP_SAVDD, AVDD_D1, and AVDD_PIXEL. NOTE Jumper-enabled 1V8 also powers PROG_MTR and PROG_SFP. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 19 On the availability of 12 V supply to the power regulators, the orderly enable of all power supplies are sequenced using powergood of the regulators, as shown in the following figure. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...
  • Page 20 R ST_OUT (to CP LD) VR500 RST_OUT Figure 6. Power up voltage sequence NOTE The LS1028ARDB follows the power supply sequencing requirements as detailed in QorIQ LS1028A Data Sheet. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 21: Clocks

    LP - HCS L S LOT[1:2]_C LK_R EQ To CP LD OE_B Differential S LOT[1:2]_P RE S ENT_B S ingle- ended Figure 7. LS1028ARDB clock architecture QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 22 • Frequency: 125 MHz (EC1_RX_CLK) controller / IEEE (KC5032A125.000C1GE00 • Output type: 1588 port LVCMOS • Operating voltage: 1.8 V Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 23: Ddr Interface

    VCC_GVDD_S (1.2 V), VTT (0.6 V) and VREFCA (0.6 V). The memory interface including all the necessary termination and I/O power are routed, as shown in the following figure. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...

  • Page 24: Usb Interface

    (DFP) or upstream facing port (UFP). Based on the configuration detected on the Type C port, the USB2 PHY can operate either in host or device mode. The following figure shows the architecture of the USB 3.0 interface. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL...
  • Page 25 Both, USB1 and USB2 connectors have an LED nearby, USB1_5V and USB2_5V, respectively, which are active when the +5 V USB power supply is enabled to the connectors. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...

  • Page 26: Displayport

    Figure 10. SerDes architecture The LS1028A SerDes module support several protocols, which are assigned to dedicated functions on the LS1028ARDB, as shown in the table below. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 27: Ethernet Controller Interface

    2.8.1 SGMII Ethernet The onboard Ethernet PHY, Qualcomm AR8033 PHY (U23) connects to the ENETC of the LS1028A processor using SGMII protocol over LYNX36 SerDes lane A. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 28 The onboard Ethernet PHY, NXP F104S8A PHY (U24), connects to the TSN switch of the LS1028 processor using QSGMII protocol over SerDes lane B. The following figure shows the QSGMII interface. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 29 (J12) is used to analyze time synchronization by measuring the pulse per second (PPS) signal. A 6-pin header (J13) is used to access TSN switch 1588 pins and IEEE 1722 pins. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...

  • Page 30: Synchronous Audio Interface (Sai)

    28) and LS1028ARDB uses the multiplexer 74LVC2G3157DPJ (U92, from Nexperia) to demux. The IEEE signals available on header J11 and J13 depend upon the RCW settings and the appropriate signal through the CPLD. For more information on the RCW settings, see QorIQ LS1028A Reference Manual.

  • Page 31: Connectors

    LYNX36 SerDes lane 3. Table 13. Register configuration M.2 connector select Signal name Mount register/capacitor Values 0 Ω Type E PEXM2_2_REFCLK_P R214 Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 32: Duart Interface

    It is recommended to use UART1 as a debug port. The LTC2804-1 transceiver can support 1 Mbit/s data rate on each of the serial ports. The figure below shows the LS1028ARDB DUART connections. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 33: Can Interface

    The TJA1052T/3 transceivers can support data rate of up to 5 Mbit/s in CAN with Flexible Data-Rate (CAN FD) phase. The figure below shows the CAN architecture. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...

  • Page 34: I2C Interface

    (1.8 V to 3.3 V and 3.3 V to 1.8 V) for CPLD and external I2C devices. The figure below shows the I2C bus architecture. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL...
  • Page 35 All channels on I2C1 are translated to 3V3 except channel 1, which operates at 1V8 (OVDD) power supply. The I2C devices available on the I2C1 bus are shown in the figure below. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...
  • Page 36 (primary) I2C1_CH0 0x50 Atmel AT24C512C-XHD- UEFI/ boot memory Provides I2C booting B: 64 KB EEPROM option. Write protectable. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 37 BLE / BEE / NFC Provides I2C connectivity defined by the to mikro-click modules on plugged-in mikro- connectors J29 and J30. click module Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 38: Xspi Interface

    0.05" 2x10 “IS P - B” x1/ x4 XS PI_A_D[3:0] XSPI_A_SCK XSPI_A_D[7:4] XSPI_A_DQS Figure 18. XSPI architecture The table below shows the devices attached to the LS1028ARDB XSPI interface. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 39 The NAND and NOR device selection is based on the RCW_BOOT_SRC settings. Refer to System configuration on page 46 for more details. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 40: Jtag Port

    The LS1028A processor supports two enhanced secured digital host controllers (eSDHC): eSDHC1 and eSDHC2. The LS1043 interposer can support only one SDHC controller and it is connected to SDHC1. The figure below shows the eSDHC1 and eSDHC2 connections in the LS1028ARDB. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 41: Mikro-Click Modules

    Since SPI and UART buses to the mikroBUS sockets are shared, modules using the same communication interface (both SPI or both UART) cannot be used. However, a combination can be supported. For example, a UART based module and QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...
  • Page 42 The UART2 interface can be used to communicate either with mikro-click modules or with RS232 compliant devices using the LTC2804-1 transceiver. The selection is done through a mux which is controlled through the CFG_MUX_UART2_SEL0 signal by CPLD. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 43: Gpios

    GPIO1_DAT25. 2.19 Interrupt handling All interrupts coming from all devices on LS1028ARDB are communicated to the LS1028A processor through GPIO1_DAT25. The following are the interrupt assignments: QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 44: Temperature Measurement

    • Reset assertion to processor and devices • Processor and system configuration • Interrupt management • System alert monitoring and status display • Remapping of system boot devices QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 45 BOM rev PCB _R EV[2:0] 000 = “Rev A” 001 = “Rev B” Selectively DNP resistors to encode P CB rev Figure 22. System controller architecture QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 46 BRDCFG and DUTCFG registers. BRDCFG registers are always active, and software may change them to result in immediate changes to the system configuration. DUTCFG registers are used to control processor configuration pins that are only sampled QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL...
  • Page 47 Controls how XSPI_A chip-select 0 is connected to devices/peripherals. CFG_MEM_WP SW3[4] CTL[3] Allows/prevents write to SYSTEM ID, UEFI flash, and DDR4 SPD. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 48 The LS1028A processor asserts ASLEEP and HRESET_B in response. ASLEEP is monitored with an LED, otherwise the signals are ignored. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 49 Tristate configuration signals drive outputs. This ensures proper configuration hold time. The CPLD is no longer involved in reset activity. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 50 The CPLD has finished reset management. The reset sequencer watches for reset switch events and will restart at reset sequencer step 1 if any are detected. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 51: Chapter 3 Board Configuration And Debug Support

    The RCW source settings are mapped to 9-bit values when an LS1043A processor is installed. Reset mode SW2[5] SW_RST_MODE RESET_REQ_B • 0: Ignore RESET_REQ_B • 1: Trigger system reset on RESET_REQ_B (default value) QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 52 • 0: SPI signal routed to mikro-click module 1 (default value) CFG_MUX_SPI2uBUS2_B • 1: SPI signal routed to mikro-click module 2 Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 53: Leds

    The information collected from LEDs can be used for debugging purposes. The following table lists all the LEDs available on the top-side of the LS1028ARDB board. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...
  • Page 54 Unless reprogrammed by user software, the thermal trip point is 85 °C. Green General status. See Multi-status LEDs for details. Green Green Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 55 • YELLOW: power cycle in progress/fault • GREEN: System ready Green/Yellow SWP0 • GREEN : Link is active Green/Yellow SWP1 • YELLOW: Link is 1000BaseT Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 56 1010 = 0xA Start reset due to (cause): JTAG HRESET_B (PORESET_B) RST_WATCH 1011 = 0xB Start reset due to (cause): Watchdog timeout Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 57 Start reset due to (cause): Pushbutton switch RECONFIG 1110 = 0xE Start reset due to (cause): Reconfig request POST_RST 1111 = 0xF Recover from requester reset QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 58: Chapter 4 Qixis Programming Model

    USB Control (USB_CTL) 00xx0000b 01Eh Watchdog (WATCH) xxxxxxxb 01Fh Power Control 2 (PWR_CTL2) 00000000b 021h Power Status 0 (PWR_MSTAT) 110010xxb 024h Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 59 DUT Configuration 2 (DUTCFG2) xxxxxxx1b 062h DUT Configuration 11 (DUTCFG11) xxxxxxxxb 06Bh GPIO I/O (GPIO_IO) xxx111xxb 080h GPIO Direction (GPIO_DIR) 00000000b 084h Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 60: Register Conventions

    Software writes are preserved. CRST Control Reset: registers are not reset except under exceptional situations, such as power cycles or watchdog timeout. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 61: Identification Registers

    The ID register contains a unique classification number. This ID number is used by system software to identify board types. The ID number remains same for all board revisions. Diagram Bits NONE Fields Field Function The board-specific identifier for the system. 47h= LS1028ARDB QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 62: Board Version (Ver)

    The BRD field lets end users determine the version of the board. Software can use this field to print board version identification. For example: printf("Board Version: %c", (get_pixis( VER ) & 0Fh) + 'A' - 1 ); QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 63: Qixis Version (Qver)

    4.7 Programming Model (MODEL) Address Register Offset MODEL 003h Function The MODEL register contains information about the software programming model version and PCB Bill Of Materials (BOM) information. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 64: Minor Revision (Minor)

    Qixis QTAG facility but more than the limited MINOR facility on other RDBs. Writes to MINOR select various pieces of information for subsequent read. On reset, the 'minor revision' field is returned, for backward-compatiblity. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 65 NAME not implemented. 0x30-7F reserved reserved Diagram Bits MINOR NONE Fields Field Function Read: Data to read from MINOR/MINTAG. MINOR Write: Address of data to read. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 66: Control And Status Registers

    Software Diagnostic LED Enable: 0= Diagnostic LEDs operate normally. 1= Software can directly control the M3:M0 monitoring LEDs using the LED register. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 67: Auxiliary (Aux)

    The AUX register may be used by software to store information. The AUX register is initialized to zero when the system is powered- up, and never altered by hardware again. Diagram Bits ARST 00000000 Fields Field Function User-defined value. 4.12 System Status (STAT_SYS) Address Register Offset STAT_SYS 009h QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 68: Alarm (Alarm)

    The ALARM register detects and reports any alarms raised in the QIXIS system. Write 1 to an ALARM register bit to prevent Qixis from recognizing that alarm condition. By default, all alarms are handled. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL...

  • Page 69: Presence Detect 1 (Stat_Pres1)

    NOTE: This signal may be asserted by either SA56004 thermal monitor. The temperature limits depend upon software programming. 4.14 Presence Detect 1 (STAT_PRES1) Address Register Offset STAT_PRES1 00Bh Function The STAT_PRES1 register detects the presence and type of processor installed. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 70: Presence Detect 2 (Stat_Pres2)

    4.15 Presence Detect 2 (STAT_PRES2) Address Register Offset STAT_PRES2 00Ch Function The STAT_PRES2 register detects the installation of cards in various PCI Express or SGMII slots. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 71: Led Control (Led)

    The LED register can be used to directly control the monitoring LEDs (M3-M0) for software debugging or other purposes. Direct control of the LEDs is possible only when CTL[LED] is set to 1; otherwise they are used to display general system activity. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...

  • Page 72: Reconfiguration Registers

    SYSCLK frequencies, boot device selections, or any other configuration controlled by a BRDCFG or DUTCFG register. 4.18 Reconfiguration Control (RCFG) Address Register Offset RCFG 010h Function The RCFG register is used to control the reconfiguration sequencer. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 73: Usb Control (Usb_Stat)

    1= On the 0-to-1 transition, the reconfiguration process begins. 4.19 USB Control (USB_STAT) Address Register Offset USB_STAT 01Dh Function The USB_STAT register reports USB 2 port status. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 74: Usb Control (Usb_Ctl)

    1= USB2 ID is high (UFP mode). 4.20 USB Control (USB_CTL) Address Register Offset USB_CTL 01Eh Function The USB_CTL register manages USB features, principally USB fault control and/or status. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 75: Watchdog (Watch)

    Note that the watchdog timer is not dependent upon a reconfiguration sequence being active. While it is typically enabled along with RCFG[GO] as part of a reconfiguration sequence; in fact, it is independent and can be enabled for any reason. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors...

  • Page 76: Power Control/Status Registers

    Other registers provide limited power control features (most power control is through the PMBus/I2C interface). 4.23 Power Control 2 (PWR_CTL2) Address Register Offset PWR_CTL2 021h Function The PWR_CTL2 register is used to control system power-on/power-off events. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 77: Power Status 0 (Pwr_Mstat)

    The PWR_MSTAT register monitors the overall power status of the board, including that of the main (ATX or other) power supply used to power all other rails. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 78: Power Status 1 (Pwr_Stat1)

    Note: If a device does not support hardware (i.e external) power savings modes, S3 is always reported. 4.25 Power Status 1 (PWR_STAT1) Address Register Offset PWR_STAT1 025h QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 79 0= Power supply is disabled or faulted. 1= Power supply is operating. VDD Power Supply Status: 0= Power supply is disabled or faulted. 1= Power supply is operating. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 80: Clock Control Registers

    I2C clock rates, and DDR memory timing. Diagram Bits SYSCLK NONE 0000 0010 Fields Field Function Reserved. SYSCLK Rate Selection: SYSCLK 0010= 100.00 MHz (fixed) Other values are Reserved. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 81: Clock Id/Status (Clk_Id)

    4.29 Reset Control Registers The reset control register group handles reset behavior configuration and general monitoring of resets. 4.30 Reset Control (RST_CTL) Address Register Offset RST_CTL 040h QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 82: Reset Status (Rst_Stat)

    Reset: 0= Reset sequencer operates normally. 1= Upon transition from 0 to 1, restart the reset sequence. 4.31 Reset Status (RST_STAT) Address Register Offset RST_STAT 041h QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 83 1= HRESET_B is asserted. PORESET_B status: PORST 0= PORESET_B is not asserted. 1= PORESET_B is asserted. RESET_REQ_B status: RREQ 0= RESET_REQ_B is not asserted. 1= RESET_REQ_B is asserted. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 84: Reset Event Trace (Rst_Reason)

    0100= Reset switch (chassis or on-board) was pushed. 0101= RCFG[GO] (that is, reconfiguration reset) was asserted. 0110= RESET_REQ_B assertion (from processor) was asserted. 1111= No event recorded yet. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 85: Reset Force 1 (Rst_Force1)

    EMMC CRST Fields Field Function 1= Assert RST_XSPI_B. XSPI Reserved. 1= Assert RST_I2CMUX_B. I2CMUX 1= Assert RST_EMMC _B EMMC Reserved. Reset DDR DIMM. 1= Assert RST_MEM_B QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 86: Reset Force 2 (Rst_Force2)

    1= Assert DUT_PORESET_B. PORST NOTE: This bit only asserts the signal to the DUT; it is not intended to be used as a general system reset. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 87: Reset Force 3 (Rst_Force3)

    M2_1 M2_2 M2_3 IEEE CRST 0000 Fields Field Function 1= Assert RST_PEXM2_1_B. M2_1 1= Assert RST_PEXM2_2_B. M2_2 1= Assert RST_SATAM2_3_B. M2_3 Reserved. 1= Force RST_IEEE1588_B. IEEE QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 88: Reset Mask 1 (Rst_Mask1)

    EMMC ARST Fields Field Function 1= Mask RST_XSPI_B. XSPI Reserved. 1= Mask RST_I2CMUX_B. I2CMUX 1= Mask RST_EMMC _B EMMC Reserved. Reset DDR DIMMs. 1= Mask RST_MEM_B QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 89: Reset Mask 2 (Rst_Mask2)

    Field Function 1= Mask RST_QSGMII_B. QSGMII 1= Mask RST_ETH_B for the RealTek PHY. Reserved. 1= Mask DUT_TRST_B. TRST 1= Mask DUT_HRESET_B. HRST 1= Mask DUT_PORESET_B. PORST QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 90: Reset Mask 2 (Rst_Mask3)

    This block of registers control the configuration of the board. BRDCFG registers are always static, driven at all times power is available. There are up to 16 registers providing up to 128 control options; however, not every platform implements all the registers. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL...

  • Page 91: Board Configuration 0 (Brdcfg0)

    XMAP controls how XSPI_A chip-selects are connected to devices/peripherals. XMAP XSPI_A_CS0 XSPI_A_CS1 ========== ========== 000= sNOR sNAND 001= sNAND sNOR 010= sNOR 011= EMU sNAND 100= sNOR Reserved. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 92: Board Configuration 1 (Brdcfg1)

    All other values are reserved. 4.42 Board Configuration 2 (BRDCFG2) Address Register Offset BRDCFG2 052h Function The BRDCFG2 register reporst SerDes clock speeds for SerDes blocks 1 and 2. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 93: Board Configuration 3 (Brdcfg3)

    SerDes1 Clock #2 Rate: SD1CK2 00= 100.000 MHz (fixed) Reserved. 4.43 Board Configuration 3 (BRDCFG3) Address Register Offset BRDCFG3 053h Function The BRDCFG3 register controls board routing. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...
  • Page 94 1= Test, TA_TMP_DETECT_B is driven with the logical-OR of GPIO3\[4:2\]. Reserved. Controls the SAI/IEEE multiplexer (MUXSEL_SAI_EN): 0= IEEE signals connect to the IEEE header. 1= IEEE signals connect to the SAI4 CODEC. Reserved. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 95: Board Configuration 4 (Brdcfg4)

    0= Clock is enabled (default). 1= Clock is disabled. DisplayPort Power Enable (net DP_PWR_EN): DPPWR 0= DP_PWR is disabled. 1= DP_PWR is enabled (default). Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 96: Board Configuration 5 (Brdcfg5)

    U1I reports the current 3.3V LVTTL level on the IRQ interrupt pin. U1R reports the current 3.3V LVTTL level on the RST pin. Reserved. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 97: Board Configuration 6 (Brdcfg6)

    Bits U2IRQ U2RST RRST Fields Field Function U2A reports the current 3.3V LVTTL level on the AN analog output pin. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 98: Dut Configuration Registers

    Refer to the device hardware specification for hardware pin-sampled timing parameters. 4.48 DUT Configuration 0 (DUTCFG0) Address Register Offset DUTCFG0 060h Function The DUTCFG0 register is used to the RCW location setting (cfg_rcw_src). QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 99: Dut Configuration 1 (Dutcfg1)

    4.49 DUT Configuration 1 (DUTCFG1) Address Register Offset DUTCFG1 061h Function The DUTCFG1 register specifies the type of DDR memory attached, and the operating voltages for it. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 100: Dut Configuration 2 (Dutcfg2)

    The DUTCFG2 register manages device selection (SVR) and internal-only device test features. Diagram Bits SVR01 TEST RRST 11111 SW_SVR Fields Field Function Reserved. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 101: Dut Configuration 11 (Dutcfg11)

    0= Processor uses differential SYSCLK_P/SYSCLK_N input (LS1043 only). 1= Reserved (default). Reserved. 4.52 GPIO Registers The GPIO registers provide an 8-bit general-purpose GPIO port. For the LS1028A RDB, the following connections are provided: QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 102: Gpio I/O (Gpio_Io)

    IO port values (if corresponding DIR.n is 1): 0= output pin driven to level 0. 1= output pin driven to level 1. Same as IO4. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 103: Gpio Direction (Gpio_Dir)

    If a GPIO_DIR register bit is 1, the corresponding GPIO port pin is in output mode, and GPIO1 port pins are set to the corresponding value in GPIO_IOn. Diagram Bits DIR3 DIR3 CRST Fields Field Function Reserved. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 104: Irq Status Registers

    IRQ_STATn registers report the current level of various IRQ/EVT signals. IRQ/EVT signals have programmable polarities, so no interpretation is made as to whether the signal is asserted or deasserted. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL...

  • Page 105: Interrupt Status 1 (Irqstat1)

    Interrupt input IRQ_UBUS1_B: UBUS1 0: Interrupt is asserted. 4.57 Interrupt Status 1 (IRQSTAT1) Address Register Offset IRQSTAT1 091h Function Additional IRQ_STAT reporting; see IRQSTAT0 for details. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 106: Interrupt Status 2 (Irqstat2)

    4.58 Interrupt Status 2 (IRQSTAT2) Address Register Offset IRQSTAT2 092h Function Additional IRQ_STAT reporting; see IRQSTAT0 for details. Diagram Bits NONE 11111111 Fields Field Function Reserved. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 107: Interrupt Drive 5 (Irqdrv5)

    The core management address/data registers allow access to internal Qixis control registers, primarily the direct switch access registers which allow easy reporting of board configuration. For RDB systems, only the following are defined: QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 108: Core Management Address (Cmsa)

    Offset CMSA 0D8h Function The CMSA register selects one of the internal core management registers within Qixis for subsequent read- or write-access via the CMSD register. QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...

  • Page 109: Core Management Data (Cmsd)

    CMSD contains the value of a CMS register selected by CMSA. See CMSA for details. Diagram Bits DATA ARST 00000000 Fields Field Function Read/write internal CMS registers selected with CMSA. DATA QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 NXP Semiconductors COMPANY CONFIDENTIAL...

  • Page 110: Appendix A Revision History

    Added detail about GPIO1_DAT[24] Adapter Added topic. Qixis Programming Model Updated Interrupt Status 0 (IRQSTAT0), Power Status 1 page 58 (PWR_STAT1) registers. Rev. A 02/2018 Initial NDA revision QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018 COMPANY CONFIDENTIAL NXP Semiconductors...
  • Page 112 How To Reach Us Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to Home Page: design or fabricate any integrated circuits based on the information in this document. NXP nxp.com reserves the right to make changes without further notice to any products herein.

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