(T1040, T1020) characteristics, as well as other design considerations QorIQ T1040 Reference Manual This document provides a detailed description on the QorIQ T1040 multicore processor, (T1040RM) and its features, such as memory map, serial interfaces, power supply, chip features, and clock information.
Serial Advanced Technology Attachment Secure Digital SerDes Serializer/Deserializer SGMII Serial Gigabit Media Independent Interface Serial Peripheral Interface SYSCLK System Clock UART Universal asynchronous receiver/transmitter Voltage for circuit Voltage for terminal QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
• SYSCLK at 100 MHz • DDRCLK at 66.66 MHz • USBCLK at 24 MHz • Single Oscillator Source reference clocking at 100 MHz • Power Supplies QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
The T1040RDB supports as many features of the T1040 as possible, as detailed in the following sections. The T1040RDB supports this by isolating OVDD-powered signals through external translation devices or the CPLD wherever required. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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• T1040RDB can access IR36021 via software to check the current and voltage values or to program the voltage changes • All power supplies are sequenced per hardware specifications The figure below shows an overview of the power supply. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
Figure 2-1. Power distribution 2.3 Clocks The clock circuitry provides clocks for the processor for: • SYSCLK (single-ended and differential) • DDRCLK • SerDes clocks (two independent options) QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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Clocks • Ethernet clocks • USB clock The architecture of the clock section is shown in the figure below. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
I/O power, and is routed so as to achieve maximum performance of the memory bus, as shown in the below figure. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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Freescale only supplies the device shown. Table 2-1. DDR3L UDIMM support Platform Type Speeds Ranks DIMM T1040RDB DDR3L 1600 MT/s Single Micron MT9KSF51272AZ-1G6 Table continues on the next page... QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
QSGMII PCIe PCIe PCIe SATA 0x66 To comply with T1040 specifications, multiplexers are used to re-route and group the SerDes lanes as shown in the figure below. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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CPLD PCle SLOT SD1_RXn/TXn_P/N(PEX[0]) Mini_PCle T1040 SLOT MPEX[1] SD1_RXn/TXn_P/N PI3PCIE3212 PEX[1] Mini_PCle SLOT MPEX[2] SD1_RXn/TXn_P/N PI3PCIE3212 PEX[2] SATA SATA SD1_RXn/TXn_P/N PI3PCIE3212 PEX[3] Figure 2-5. SerDes lane connections QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
2.6.3 QSGMII support The T1040RDB board supports evaluation of the QSGMII protocol using an F104S8A four-port Ethernet PHY. The figure below shows the connectivity of the QSGMII interface. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
RTL8211 PHYs. The T1040RDB board supports energy efficient Ethernet on EC1 and sleep mode on EC2. The figure below shows the connectivity of the EC1 and EC2 interfaces. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
2.8 Ethernet management interface The T1040 Ethernet management interface (EMI1) is used with the onboard RGMII, SGMII, and QSGMII PHYs. The figure below shows the EMI block. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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I2C bus into several sub-buses, called channels. The two mini-PCIe slots use channel 0-1, or I2C2_CH0-1, channel 2 is unused on the T1040RDB board. The PCIe slot uses channel 3. The figure below shows the I2C subsystem. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
Figure 2-10. I2C bus connection 2.10 SPI interface The T1040 serial peripheral interface (SPI) pins are used for the following purposes: • Onboard SPI device access to various SPI memory devices QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
8- or 16-bit data widths, for a variety of devices. IFC lets to manage all these resources effectively with maximum performance and flexibility. The figure below shows an overview of the IFC bus. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
If SW3.4 is OFF: Table 2-4. IFC bus address Memory Address Bus width NAND flash 0xff800000 8 bit NOR flash 0xe8000000 16 bit CPLD 0xffdf0000 8 bit 2.12 SDHC interface QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
A per port. The power-enable and power-fault-detect pins are connected directly to the T1040 for individual port management. The figure below shows the USB connectivity on the T1040RDB board. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
The serial connection is configured to run at 115.2 kbit/s, with 8 bits, no parity, and one stop bit. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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The table below shows the connection setting for the UART RJ45 and the DB9 female cable (Part number: 600-76847-000). Table 2-5. RJ45 and DB9 connection RJ45 pin number RS-232 signal DB9 female pin number QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
SLIC is connected to the TDM interface of T1040 device RJ11 FXS Port SLIC1 SPI1 RJ11 FXS Port T1040 RJ11 FXS Port SLIC2 RJ11 FXS Port SPI2 Control RJ11 FXO Port Relay Figure 2-16. TDM connection QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
The 16-pin generic header connector carries the COP/JTAG signals and the additional signals for system debugging. The pin-out of this connector is shown in the figure below. TRST_B VDD_SENSE CKSTP_IN SRESET_B HRESET_B CKSTP_OUT Figure 2-18. JTAG header QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
Table 2-7. Connector on board Reference Designators Used For Notes UDIMM COP/JTAG Used for debugging T1040 SD card J13(2 ports) UART Table continues on the next page... QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
Green FXS3 CPLD FXS4 LED Green FXS4 CPLD FXO LED Green CPLD T1040/T1020 Green Detects onboard device CPLD T2081 LED Green Detects onboard device CPLD 2.18 Temperature QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
In order to use the CPLD override option, software sets an override bit that allows the CPLD to override the switch setting during reset. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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TE assertion 1: IFC drives logic 0 for TE assertion SW2[3] cfg_pll_config_sel_b IFC_A18 Reserved Reserved SW2[4] cfg_por_ainit IFC_A19 Reserved Reserved Table continues on the next page... QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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U-Boot image can be selected to boot up the board, by setting SW3[5:7]. For other boot sources configured by the DIP switch, see the QorIQ T1040 Reference Manual (T1040RM). QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015...
3.1 CPLD programming To program CPLD: 1. Connect Altera USB-blaster to the CPLD header. 2. Run to open Quartus II. altera\61\quartus\bin\quartus.exe 3. Select Tools->Programmer from the menu bar. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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CPLD programming 4. Click the Hardware Setup button to find the USB-blaster connected to the PC. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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5. Switch on the board, click Auto Detect to detect EPM240. 6. Right-click EPM240, select Change File from the context menu and find the *.pof file. 7. Select Program/Configure, Verify, Blank-Check checkboxes. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
1: Write a logic 1 produces RGMII PHY1(RTL82111E-VB) reset# signal, this bit can auto clear. 0: No reset occurs. EC2_RST 1: Writing logic 1 produces RGMII PHY2(RTL82111E-VB) reset# signal, this bit can auto clear. Table continues on the next page... QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
1: Writing logic 1 produces miniPCIe card1 reset# signal, this bit can auto clear. 0: No reset occurs MPEX2_RST 1: Writing logic 1 produces miniPCIe card2 reset# signal, this bit can auto clear. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
1: NOR flash bank select bit2 set 1. 3.2.9 Fan control and status register (FANCSR) Address: 0h base + 14h offset = 14h Read Reserved FAN_PWM Write Reset QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
0: Panel XG RX LED off when SFP+ not present or RX los. XG_LED2 1: Panel XG RX LED on when SFP+ present and RX optical received QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
PCIe card present in x4 slot. 0: T1040 on board T2081_DET 1: T2081 on board 0: TEST_SEL_N pin status is 0 TEST_SEL_N 1: TEST_SEL_N pin status is 1 QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
Reset BOOTCFG1 field descriptions Field Description 0–7 cfg_rcw_src[0:7] NOTE: For more information, see QorIQ T1040, T1020 Data Sheet. 3.2.15 Boot configuration register 2 (BOOTCFG2) NOTE For more information, refer T1040 datasheet. Address: 0h base + 1Ah offset = 1Ah Read...
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RCW source bit 8. cfg_rcw_src8 This field is reserved. 2–3 cfg_svr bit for T1040 Power-on-reset use cfg_svr[0:1] This field is reserved. 5–7 cfg_eng_use bit for T1040 Power-on-reset use. cfg_eng_use[0:2] QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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CPLD memory map QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
3. Configure the host computer's serial port with the following settings: • Data rate: 115200 bps • Number of data bits: 8 • Parity: None • Number of stop bits: 1 • Flow control: Hardware/None QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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68:05:ca:04:d5:6a Address in environment is 00:04:9f:ef:00:00 Hit any key to stop autoboot: The system auto boots and shows the following Linux login screen. t1040rdb login: root root@t1040rdb:~# QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
NOR flash can be divided into two flash banks (0 and 4) to store a main image and an alternative backup image. This is shown in the below table. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
4.4.1 Switch default settings (NOR flash boot) This section defines the default switch settings for NOR flash boot. NOTE ON and OFF are being represented as 0 and 1 respectively, on the board. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
0010 0010 ON 1011 1011 OFF 1110 0001 OFF SD boot settings: Switch binary value 0010 0000 ON 0011 1011 ON 1110 0001 OFF 4.4.3 Switch detailed description QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
4.6.2 Flashing eSPI boot images The steps for flashing and updating images for eSPI are as follows: 1. Write (created using QCS tool) at offset 0: PBL1.bin QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
<serverip> • From U-Boot prompt, for booting Linux with 32-bit configuration on T1040RDB: => setenv my_kern 'tftp 0x1000000 <uImage>’ => setenv my_fs 'tftp 0x2000000 <rfs_e5500.bin>' QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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<rfs_e5500.bin>' => setenv my_dtb 'tftp 0x00c00000 <t1040rdb.dtb>' => setenv my_boot bootm 0x1000000 0x2000000 0x0c00000 => setenv boot run my_dtb my_fs my_kern my_boot => save => run boot QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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Appendix A Revision History Table A-1 summarizes revisions to this document. Table A-1. Revision history Revision Date Description 06/2015 Initial release. QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 Freescale Semiconductor, Inc.
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