Hitachi Hidic EH-150 Applications Manual page 79

Preliminary Rev.03
Ready/Event send Control Register (RECR)
Bit
+3
Bit 15-6: Reserved
These bits are reserved. Please set "0" always.
Bit 5-0: Send ready/Event send request bit (ASE[6:1])
The function of this bit is different with send mode of each connection. Send mode is specified by Automatic
Sending/Receiving configuration table. Please refer "chapter 5.7 Automatic Sending/Receiving configuration table
" for the detail operation.
This bit works as Send ready bit when the connection is used for Cyclic send. When it is used for the Event send,
this bit works as an Event send request bit.
The function of this bit is listed in table 5.1.
Sending/Receiving mode
(1) Send Ready bit
Bit5-0: ASE[6:1]
0
1
(2) Event send bit
Bit5-0: ASE[6:1]
0
1
The contents of this manual might be changed without notice.
15 14 13 12 11
- - - - -
Table 8.1 Definition of each bit
Exclusive control
Cyclic Send
Cyclic Send
Event Send
(1) Request to clear Transmit complete bit (TXC) of Connection n
communication status (CnCSR).
(2) The data of send area is not sent. (Previous sent data is sent again.)
Allow "Automatic Sending/Receiving function" to send data on send area.
(1) Request to clear Transmit complete bit (TXC) of Connection n
communication status (CnCSR).
(2) Event send is not done.
Request to execute Event sent to this module.
10 9 8 7 6
- - - - -
Function
Disable Unnecessary to set
Send Ready bit shown as
Enable
following(1)
Event send bit shown as
-
following(2)
Description
Description
8-10
Chapter 8 Register Structure
5 4 3 2 1
ASE6 ASE5 ASE4 ASE3 ASE2 ASE1
(Initial set)
(Initial set)
0