Sony SAT-W60 Service Manual page 20

8 7
CPU_CLK\I
CPU_CRESET_N\I CPU_CRESET_N\I
CPU_SRESET_N\I CPU_SRESET_N\I
D
+ 3 _ 3 V
C
1 R0301
R0311
4.7K
4.7K 5 %
5 %
6 0 3
6 0 3
2
3
POWER_OK\I
CPU_WRRDY_N\I
CPU_EXTRQST_N\I
CPU_VALIDIN_N\I
CPU_MODEIN\I
B
CPU_INT_N\I
FUD_INT_N\I
DIAG_INT_N\I
CPU_VCCOK\I
INT<5> IS RESERVED
FOR TIMER
+ 3 _ 3 V
R 0 3 0 2
4.7 5 %
6 0 3
C 0 3 0 5 C 0 3 0 6 C 0 3 0 7
0.1UF 10UF 1.5NF
2 0 % 2 0 % 2 0 %
50V 10V 50V
C E R M C E R M C E R M
8 0 5 1210 8 0 5
R 0 3 0 3
A
4.7 5 %
6 0 3
8 7
6
CPU_CLK\I
41 M A S T E R C L O C K
68
COLDRESET_N
67
RESET_N
70 BIGENDIAN
R0312
R0310
4.7K
4.7K
5 %
5 %
6 0 3
6 0 3
34
R D R D Y _ N
35
W R R D Y _ N
66
EXTRQST_N
36
VALIDIN_N
33 MODEIN
65 NMI_N
59
INT_N<0>
60
INT_N<1>
61 INT_N<2>
62 INT_N<3>
63 INT_N<4>
64 INT_N<5>
69 V C C O K
C P U _ V C C P 39
V C C P
C P U _ V S S P
40 VSSP
+ 3 _ 3 V + 2 _ 5 V
6
5 4
U0301
S Y S _ A D < 3 1 >
S Y S _ A D < 3 0 >
S Y S _ A D < 2 9 >
S Y S _ A D < 2 8 >
S Y S _ A D < 2 7 >
R M 5 2 3 1
S Y S _ A D < 2 6 >
S Y S _ A D < 2 5 >
S Y S _ A D < 2 4 >
S Y S _ A D < 2 3 >
S Y S _ A D < 2 2 >
S Y S _ A D < 2 1 >
S Y S _ A D < 2 0 >
S Y S _ A D < 1 9 >
S Y S _ A D < 1 8 >
S Y S _ A D < 1 7 >
S Y S _ A D < 1 6 >
S Y S _ A D < 1 5 >
S Y S _ A D < 1 4 >
S Y S _ A D < 1 3 >
S Y S _ A D < 1 2 >
S Y S _ A D < 1 1 >
S Y S _ A D < 1 0 >
S Y S _ A D C < 3 >
S Y S _ A D C < 2 >
S Y S _ A D C < 1 >
S Y S _ A D C < 0 >
S Y S _ C M D < 8 >
S Y S _ C M D < 7 >
S Y S _ C M D < 6 >
S Y S _ C M D < 5 >
S Y S _ C M D < 4 >
S Y S _ C M D < 3 >
S Y S _ C M D < 2 >
S Y S _ C M D < 1 >
S Y S _ C M D < 0 >
BUS INTERFACE
M O D E C L O C K
INTERRUPTS JTAG
NC_PIN<10>
P O W E R & G R O U N D
This document contains privileged or otherwise legally protected
information.
than the recipient is not authorized.
or otherwise use this document unless you are an authorized
representative of a named recipient.
DRAWING
SET:
TITLE=BLK_CPU
A B B R E V = B C P U
LAST_MODIFIED=Tue Mar 21 17:56:15 2000 ENGINEER:
5 4
3 2
CPU_AD<31..0>\I
108 31
107 3 0
104 2 9
103 2 8
92 2 7
2 6
91
2 5
88
87 2 4
86 2 3
85 2 2
82 21
81 2 0
19
78
77 18
76 17
73 16
24 15
21 14
13
20
12
19
16 11
15 10
12 9
S Y S _ A D < 9 >
11 8
S Y S _ A D < 8 >
7
S Y S _ A D < 7 > 10
6
S Y S _ A D < 6 > 9
S Y S _ A D < 5 > 6 5
S Y S _ A D < 4 > 5 4
122 3
S Y S _ A D < 3 > R 0 3 0 4 R 0 3 0 5 R 0 3 0 6 R 0 3 0 7
121 2
S Y S _ A D < 2 >
118 1
S Y S _ A D < 1 > 4.7K 4.7K 4.7K 4.7K
0
S Y S _ A D < 0 > 117 5 % 5 % 5 % 5 %
6 0 3 6 0 3 6 0 3 6 0 3
S Y S _ A D C < 3 >
112
S Y S _ A D C < 2 >
109
116 S Y S _ A D C < 1 >
115 S Y S _ A D C < 0 >
8
55
54 7
53 6
C P U _ C M D < 4 > \ I
51 5
C P U _ C M D < 2 > \ I
50 4
C P U _ C M D < 8 > \ I
47 3
46 2
1
45
44 0
S Y S _ C M D P 56
38
RELEASE_N + 3 _ 3 V + 3 _ 3 V + 3 _ 3 V + 3 _ 3 V
37
VALIDOUT_N
27
R 0 3 0 8 R0313 R0314 R0315
10K
28
JTDO 5 % 4.7K 4.7K 4.7K
1/16W 5 % 5 % 5 %
29
JTDI TK 6 0 3 6 0 3 6 0 3
6 0 3
JTCK 30
C P U _ C M D < 0 > \ I
CPU_CMD<1>\I
JTMS 31
C P U _ C M D < 3 > \ I
128 C P U _ C M D < 5 > \ I
NC_PIN<11>
127 C P U _ C M D < 6 > \ I
C P U _ C M D < 7 > \ I
N C _ P I N < 9 > 126
N C _ P I N < 8 > 125
N C _ P I N < 7 > 100
N C _ P I N < 6 > 99
98
N C _ P I N < 5 >
97
N C _ P I N < 4 >
96
N C _ P I N < 3 >
N C _ P I N < 2 > 95
NC_PIN<1> 2
N C _ P I N < 0 > 1
Q F P
C WEBTV NETWORKS, INC. 1999
Disclosure of this information to anyone other
You may not read, copy,
E L M E R C P U
BLOCK: DATE:
SLEATOR/FULLER APPROVED:
3 2
1
CPU_AD<31..0>\I
D
+ 3 _ 3 V
R0317 R0318 R0319 C
4.7K 4.7K 4.7K
5 % 5 % 5 %
6 0 3 6 0 3 6 0 3
CPU_CMD<8..0>\I
+ 3 _ 3 V + 3 _ 3 V + 3 _ 3 V
B
R0316 R 0 3 2 0 R0321
4.7K 4.7K 4.7K
5 % 5 % 5 %
6 0 3 6 0 3 6 0 3
A
CPU_RELEASE_N\I
CPU_VALIDOUT_N\I
CPU_MODECLK\I
REVISION: 0.0
B L O C K
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REVISION:
PVT
SET
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