Sony SAT-W60 Service Manual page 18
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Also See for SAT-W60:
- Service manual (60 pages) ,
- User manual (55 pages) ,
- Installation manual (32 pages)
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8
7
+ 3 _ 3 V
GPIO<19..0>\I
R0219
19
4.7K
5 %
6 0 3
+ 3 _ 3 V
RIO_DINT<7..0>\I
R0218
18
4.7K
5 %
R 0 2 2 7
7
6 0 3
D
10K
5 %
R0217
17
6 0 3
4.7K
5 %
R 0 2 2 6
6 0 3
6
10K
5 %
R0216
16
6 0 3
4.7K
5 %
R 0 2 2 5
6 0 3
5
10K
5 %
REMOVED R0215
6 0 3
R 0 2 2 4
4
10K
5 %
REMOVED R0214
6 0 3
R 0 2 2 3
3
10K
5 %
R0213
13
6 0 3
10K
5 %
R 0 2 2 2
6 0 3
2
10K
5 %
R0212
12
6 0 3
10K
5 %
R0221
6 0 3
1
C
5.62K
1 %
R0211
11
6 0 3
10K
5 %
R 0 2 2 0
6 0 3
0
10K
5 %
R0210
10
6 0 3
10K
5 %
6 0 3
R E M O V E D R 0 2 0 9
SERPENTINE LENGTH FOR
750 PS DELAY: ~4.5 INCH
SYS_2XCLKIN\I
R E M O V E D R 0 2 0 8
R E M O V E D R 0 2 0 7
+ 3 _ 3 V
R 0 2 0 6
6
B
10K
5 %
1
6 0 3
R 0 2 9 9
0
R E M O V E D R 0 2 0 5
5 %
6 0 3
2
PLL_BYPASS
R 0 2 0 4
4
10K
5 %
6 0 3
3
R 0 2 0 3
3
10K
5 %
PLL_DVD
6 0 3
Y3
PLL_DVD
PLL_DGN
AB1
PLL_DGN
R E M O V E D R 0 2 0 2
N C
DAC_NC<1..0>
SOLO_VSS \R 17
VSS3<16..0>
SOLO_VSS \R 29
VSS2<28..0>
SOLO_VSS \R 37
VSS<36..0>
SOLO_VDD \R 17
REMOVED R0201
VDD3<16..0>
SOLO_VDD \R 29
VDD<28..0>
PLL_VAA
V6
PLL_VAA
PLL_AGD
AB2
PLL_AGD
R E M O V E D R 0 2 0 0
A
CPU_CMD<8..0>\I
NOTES:
SOLO2 POWER PARTITIONS
VSS
= OUTPUT BUFFER GROUNDS
VSS2 = CORE LOGIC GROUNDS
VSS3 = INPUT BUFFER GROUNDS
VDD
= CORE LOGIC AND OUTPUT BUFFER POWERS
VDD3 = INPUT BUFFER POWERS (IN SOLO2.5,
THESE PINS WILL BE NAMED VDD2
AND WILL BECOME CORE LOGIC POWERS)
8
7
6
TEST_MODE<3..0>
R 0 2 3 3
3
10K
5 %
6 0 3
R 0 2 3 2
2
10K
5 %
6 0 3
R 0 2 8 0
R0231
RIO_DRQ<0>\I
1
10K
5 %
10K
5 %
6 0 3
6 0 3
R0281
R 0 2 3 0
RIO_DRQ<1>\I
0
10K
5 %
10K
5 %
6 0 3
6 0 3
SOLO_VSS
TP0204
TP0205
TP_75
TP_75
TH
TH
TP0202
TP0203
TP_75
TP_75
TH
TH
TEST_SCANEN
E11
TEST_SCANEN
TEST_MODE<3..0>
TEST_MODE<3..0>
SYS_RSWTCH_N\I
B 3
S Y S _ R S W T C H _ N
SYS_PWROK\I
AA1
S Y S _ P W R O K
SYS_DPWROK\I
AA2
S Y S _ D P W R O K
AC2
SYS_2XCLKIN
RIO_DRQ<1..0>\I
RIO_DRQ<1..0>
RIO_DINT<7..0>\I
RIO_DINT<7..0>
RIO_DEVIORDY\I
A26
RIO_DEVIORDY
PP_SELECT\I
B17
PP_SELECT
PP_FAULT_N\I
D15
PP_FAULT_N
PP_ERROR\I
C16
P P _ E R R O R
PP_BUSY\I
B16
P P _ B U S Y
PP_ACK_N\I
A16
P P _ A C K _ N
POT_CLK\I
D12
POT_CLK
PLL_BYPASS
AA3
PLL_BYPASS
MOD_SDATAIN\I
A20
MOD_SDATAIN
MOD_CLK\I
B 2 0
M O D _ C L K
IR_IN\I
R 2 6
IR_IN
DIV_LLC\I
B 2
DIV_LLC
DAC_YVBS
A6
DAC_YVBS
DAC_VREF
C 6
DAC_VREF
D A C _ C R C B V B S
B 6
D A C _ C R C B V B S
D A C _ C O M P V B S
D 9
D A C _ C O M P V B S
CPU_VALOUT_N\I
Y4
C P U _ V A L O _ N
CPU_MODECLK\I
J3
C P U _ M O D E C L K
CPU_EWRRDY_N\I
H 4
C P U _ E W R R D Y _ N
CPU_EVALO_N\I
J4
C P U _ E V A L O _ N
AUD_SDATAIN\I
A11
AUD_SDATAIN
AUD_CLK\I
C12
A U D _ C L K
CMD_TWIZZLE<6..0>
8
6
7
5
6
4
5
3
3
2
PRESERVES HISTORIC SIGNAL FLOW
1
1
WHILE MAKING IT EASY TO CONNECT
FUD TO THE CPU
0
0
6
5
5
4
+ 5 V
+ 3 _ 3 V
AUD_BITCLK\I
AUD_LRCLK\I
R 0 2 2 8
SYS_RESET_N\I
1K
5 %
6 0 3
AUD_SDATA\I
R 0 2 4 0
SYS_5VRESET_N\I
10K
5 %
6 0 3
R 0 2 3 7
MOD_SDATAIN\I
10K
5 %
6 0 3
EMPTY
R 0 2 3 8
MOD_CLK\I
10K
5 %
6 0 3
EMPTY
+ 3 _ 3 V
L0203
PLL_DVD
BK2125HS601
S M
C 0 2 2 4
C 0 2 2 5
0.1UF
10UF
2 0 %
2 0 %
50V
10V
C E R M
C E R M
L0202
8 0 5
1210
PLL_DGN
BK2125HS601
S M
A8
VID_VSYNC_N\I
C S Y N C
VID_VSYNC_N
VID_HSYNC_N\I
F S W
VID_HSYNC_N
A9
VID_DATA<7..0>
VID_DATA<7..0>\I
UART_TXD
C17
UART_TXD\I
UART_RXD
D18
UART_RXD\I
B18
UART_RTS_N\I
UART_RTS_N
A18
UART_DTR_N\I
UART_DTR_N
C18
UART_DCD_N\I
U A R T _ D C D _ N
UART_CTS_N\I
UART_CTS_N
D17
S M C _ R E S E T _ N
AE1
SMC_RESET_N\I
S M C _ P E N _ N
AD2
SMC_PEN_N\I
SMC_INSERT_N
AD3
SMC_INSERT_N\I
AF1
SMC_FIT\I
SMC_FIT
AF3
SMC_DATA\I
SMC_DATA
AC3
SMC_CLK\I
S M C _ C L K
RIO_DATA<15..0>\I
RIO_DATA<15..0>
RIO_CE_N<3..0>\I
RIO_CE_N<3..0>
RIO_ADDR<21..0>\I
RIO_ADDR<21..0>
B15
PP_STROBE_N\I
P P _ S T R O B E _ N
D16
PP_SELIN_N\I
PP_SELIN_N
PP_DATA<7..0>\I
PP_DATA<7..0>
PP_AUTOFD_N\I
P P _ A U T O F D _ N
C15
MC1_DATA<31..0>\I
MC1_DATA<31..0>
MC0_DATA<31..0>
MC0_DATA<31..0>\I
A19
IR_OUT\I
IR_OUT
R 2 5
IR_CLK\I
IR_CLK
A3
IIC_DATA\I
IIC_DATA
IIC_CLK\I
IIC_CLK
A2
ID_DATA
AC4
ID_DATA\I
GPIO<19..0>
GPIO<19..0>\I
DIV_VS
E3
DIV_VS\I
G 4
DIV_SDATA\I
DIV_SDATA
G 2
DIV_LRCLK\I
DIV_LRCLK
F2
DIV_HS\I
DIV_HS
DIV_DATA<7..0>\I
DIV_DATA<7..0>
DIV_BCLK
F3
DIV_BCLK\I
CPU_CMD<6..0>
CMD_TWIZZLE<6..0>
CPU_AD<31..0>
CPU_AD<31..0>\I
$Id: solo.mpl,v 1.30 1997/05/21 10:31:53 lyang Exp $
+ 3 _ 3 V
R0261
RIO_DEVIORDY\I
This document contains privileged or otherwise legally protected
10K
5 %
information.
6 0 3
than the recipient is not authorized.
or otherwise use this document unless you are an authorized
representative of a named recipient.
DRAWING
SET:
TITLE=BLK_SOLO2
A B B R E V = B S L 2
LAST_MODIFIED=Mon Apr 10 12:33:20 2000
ENGINEER:
4
3
2
VID_VDD
PRESERVES HISTORIC SIGNAL FLOW
DIV_BCLK\I
R 0 2 9 8
1.62K
1 %
6 0 3
DIV_LRCLK\I
DIV_SDATA\I
C0214
R 0 2 9 7
0.1UF
2 K
1 %
2 0 %
6 0 3
50V
C E R M
8 0 5
VID_VSS
U0201
PADS_ONLY
R 0 2 6 2
SYS_RESET_N\I
B G A
47
5 %
6 0 3
SYS_RESET_N
A1
R 0 2 8 2
SYS_5VRESET_N\I
SYS_5VRST_N
AE2
SPD_SDATA\I
SPD_SDATA
A12
47
5 %
B 2 5
RIO_WE_N\I
6 0 3
RIO_WE_N
C 2 4
RIO_OE_N\I
RIO_OE_N
RIO_DEN_N<7..0>\I
RIO_DEN_N<7..0>
RIO_DAK_N<1..0>\I
RIO_DAK_N<1..0>
PP_INIT_N
A15
PP_INIT_N\I
PP_DIR
A17
PP_DIR\I
P L L _ M P O
P L L _ M P O
AC1
PLL_LP
V5
PLL_LP
B21
MOD_SDATA\I
M O D _ S D A T A
C21
MOD_LRCLK\I
M O D _ L R C L K
MOD_BITCLK\I
MOD_BITCLK
A21
MISC_LED<2..0>
MISC_LED<2..0>\I
M C 1 _ W E _ N
AD23
MC1_WE_N\I
M C 1 _ R A S _ N
AE24
MC1_RAS_N\I
MC1_DQM<3..0>\I
MC1_DQM<3..0>
MC1_CS_N<1..0>\I
MC1_CS_N<1..0>
AA25
MC1_CKE\I
M C 1 _ C K E
MC1_CAS_N\I
M C 1 _ C A S _ N
AC23
M C 1 _ B S
AF24
MC1_BS\I
MC1_ADDR<10..0>
MC1_ADDR<10..0>\I
M C 0 _ W E _ N
AD8
MC0_WE_N\I
AE9
MC0_RAS_N\I
M C 0 _ R A S _ N
MC0_DQM<3..0>\I
D A C _ C R C B V B S
MC0_DQM<3..0>
MC0_CS_N<1..0>\I
MC0_CS_N<1..0>
MC0_CKE\I
M C 0 _ C K E
AD13
M C 0 _ C A S _ N
AD9
MC0_CAS_N\I
AD10
MC0_BS\I
M C 0 _ B S
MC0_ADDR<10..0>\I
MC0_ADDR<10..0>
C 8
VID_VSS
D A C _ C O M P V B S
DAC_YAPVS
A5
DAC_YAOUT\I
DAC_YAOUT
VID_VSS
D A C _ C R C B A P V S
B 5
DAC_CRCBAOUT\I
D A C _ C R C B A O U T
E9
D A C _ C O M P A P V S
F9
VID_VSS
C 7
DAC_COMPAOUT\I
D A C _ C O M P A O U T
B 4
VID_VDD
DAC_APVD1
A4
VID_VDD
DAC_APVD0
CPU_WRRDY_N\I
C P U _ W R R D Y _ N
H 3
C P U _ V C C O K
R 3
CPU_VCCOK\I
CPU_VALI_N
W 1
CPU_VALIN_N\I
C P U _ S R E S E T _ N
V1
CPU_SRESET_N\I
Y2
CPU_MODEIN\I
C P U _ M O D E I N
R 2
CPU_INT_N\I
CPU_INT_N
F1
CPU_EVALI_N\I
CPU_EVALI_N
CPU_CRESET_N\I
C P U _ C R E S E T _ N
U 3
AUD_SDATA
B12
AUD_SDATA\I
AUD_LRCLK
B11
AUD_LRCLK\I
AUD_BITCLK
C11
AUD_BITCLK\I
C WEBTV NETWORKS, INC. 1999
Disclosure of this information to anyone other
You may not read, copy,
E L M E R
S O L O 2
BLOCK:
DATE:
SLEATOR/FULLER
APPROVED:
3
2
1
DAC_VREF
C0219
C0213
EMPTY
D
10UF
0.1UF
2 0 %
2 0 %
16V
50V
C E R M
C E R M
1210
8 0 5
C
TP0206
TP_75
TP0207
TH
TP_75
EMPTY
TH
R 0 2 2 9
1 0 M
5 % 1/16W
6 0 3
TK
VID_VDD
C0215
DAC_YVBS
220PF
5 %
50V
C E R M
EMPTY
C0216
B
220PF
5 %
50V
C E R M
C0217
220PF
5 %
50V
C E R M
+ 5 V
R 0 2 3 5
IIC_CLK\I
2.2K
5 %
A
6 0 3
R 0 2 3 6
IIC_DATA\I
4.7K
5 %
6 0 3
REVISION:
0.0
B L O C K
PAGE:
1
of
2
REVISION:
PVT
SET
4
3 7
PAGE:
of
1
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