GigaDevice Semiconductor GD32F20 Series User Manual page 454

Channel 1 capture/compare value register (TIMERx_CH1CV)
Address offset: 0x38
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit).
31 30 29 28
15 14 13 12
Bits Fields
31:16 Reserved
15:0 CH1VAL[15:0]
When channel 0 is configured in output mode, this bit-filed contains value to be
compared to the counter. When the corresponding shadow register is enabled, the
shadow register updates every update event.
27 26 25 24
Reserved
11 10 9 8
CH1VAL[15:0]
Descriptions
Must be kept at reset value.
Capture or compare value of channel1
When channel 1 is configured in input mode, this bit-filed indicates the counter
value corresponding to the last capture event. And this bit-filed is read-only.
When channel 1 is configured in output mode, this bit-filed contains value to be
compared to the counter. When the corresponding shadow register is enabled, the
shadow register updates every update event.
GD32F20x User Manual
23 22 21
7 6 5
rw
20 19 18 17
4 3 2 1
16
0
454