Toshiba TLCS-900/H1 Series Manual page 83

P7 Bit symbol
(001CH)
Read/Write
Reset State
P7CR Bit symbol
(001EH)
Read/Write
Reset State
Function
P7FC Bit symbol
(001FH)
Read/Write
Reset State
Function
P7DR Bit symbol
(0087H)
Read/Write
Reset State
Function
P72 Setting
<P72F>
P76 Setting
<P76F>
Note 1: Read-modify-write is prohibited for P7CR and P7FC.
Note 2: It is set to "Port" or "
Note 3: When NDRE and NDWE are used, set registers in the following order to avoid outputting a negative glitch.
Order Register
(1) P7
(2) P7FC
(3) P7CR
Port 7 register
7 6 5
P76 P75
Data from external port
(Output latch register is
set to "1")
Port 7 Control register
7 6 5
P76C P75C
W
0 0
0: Input port, 0: Input port,
WAIT NDR/ B
1:Output port 1:Output port,
R/ W
Port 7 Function register
7 6 5
P76F P75F
0 0
Refer to following table
Port 7 Drive register
7 6 5
P76D P75D
1 1
<P72C>
0
0 Output port
Input port
NDWE
(at <P72> = 0)
1 (Reserved)
WRLH
(at <P72> = 1)
<P76C>
0
0 Input port Output port
1 input (Reserved)
WAIT
" by AM pin setting.
RD
Bit2 Bit1
0 0
1 1
1 1
Figure 3.5.15 Register for Port 7
92CH21-81
4 3
P74 P73
R/W
0 0
4 3
4 3
P74F P73F
W
0 0
0: port 0: port
1: EA25 1: EA24
4 3
P94D P73D
R/W
1 1
Input/Output buffer drive register for standby mode
P71 Setting
<P71C>
1
<P71F>
0
output
1
output
P75 Setting
<P75C>
1
<P75F>
0
1
TMP92CH21
2 1
P72 P71
Data from external port
(Output latch register is
set to "1")
2 1
P72C P71C
W
0 0
Refer to following table
2 1
P72F P71F
0 0 0/1 Note 2
Refer to following table 0: port
1:
2 1
P72D P71D
1 1
0 1
Input port Output port
output
NDRE
at (<P71> = 0)
(Reserved)
output
WRLL
(at <P71> = 1)
0 1
Input port Output port
NDR/ B input R/ output
W
2009-06-19
0
P70
1
0
0
P70F
RD
0
P70D
1