Toshiba TMP92CM22FG TLCS-900/H1 Series Manual
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Toshiba TMP92CM22FG TLCS-900/H1 Series Manual

Toshiba TMP92CM22FG TLCS-900/H1 Series Manual

Toshiba original cmos 32-bit microcontroller
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TOSHIBA Original CMOS 32-Bit Microcontroller
TLCS-900/H1 Series
TMP92CM22FG
Semiconductor Company

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Summary of Contents for Toshiba TMP92CM22FG TLCS-900/H1 Series

  • Page 1 TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CM22FG Semiconductor Company...
  • Page 2 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”.
  • Page 3 • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use.

  • Page 4: Memory Controller

    TMP92CM22 (4) External memory expansion • Expandable up to 16 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus ･･･Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output: 4 channels (6) 8-bit timers: 4 channels (7) 16-bit timers: 2 channels (8) General-purpose serial interface: 2 channels...
  • Page 5 TMP92CM22 PG0 to PG7 DVCC [3] (AN0 to AN7) DVSS [4] PG3 ( ADTRG 900/H1 CPU 10-bit 8-ch AVCC AVSS converter VREFH H-OSC VREFL Clock gear PF0 (TXD0) Serial I/O PF1 (RXD0) SIO0 PF2 (SCLK0/ RESET CTS0 Mode controller PF3 (TXD1) Serial I/O PF4 (RXD1) SIO1...

  • Page 6: Pin Assignment

    TMP92CM22 Pin Assignment and Functions The assignment of input/output pins for the TMP92CM22FG, their names and functions are as follows. Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92CM22FG. VREFL P66/A22 VREFH P65/A21 PG0/AN0 P64/A20 PG1/AN1 DVCC3 PG2/AN2 P63/A19 PG3/AN3/ P62/A18...

  • Page 7: Pin Names And Functions

    TMP92CM22 Pin Names and Functions The following tables show the names and functions of the input/output pins. Table 2.2.1 Pin Names and Functions (1/2) Number Pin Names Functions of Pins D0 to D7 Data (Lower): Data bus D0 to D7. P10 to P17 Port 1: I/O port that allows I/O to be selected at the bit level.
  • Page 8 TMP92CM22 Table 2.2.2 Pin Names and Functions (2/2) Number Pin Names Functions of Pins Port C0: I/O port. TA0IN Input Timer input: 8-bit timer A0 input. Port C1: I/O port. INT1 Input Interrupt request pin 1: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 8-bit timer A0 or timer A1 output.

  • Page 9: Operation

    TMP92CM22 Operation This section describes the basic components, functions and operation of the TMP92CM22. The TMP92CM22 incorporates a high-performance 32-bit CPU (The TLCS-900/H1 CPU). For a description of this CPU’s operation, please refer to the section of this data book which describes the TLCS-900/H1 CPU.

  • Page 10: Reset Operation

    TMP92CM22 3.1.2 Reset Operation When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low for at least 20 system clocks (16 μs at fc = 40 MHz).
  • Page 11 TMP92CM22 3.3 V RESET 0 [s] (Min) Oscillator operation time + 20 system clocks Figure 3.1.1 Reset Timing Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to “10” to use 8-bit external bus, or set it to “01” to use 16-bit external bus.

  • Page 12: Memory Map

    TMP92CM22 Memory Map Figure 3.2.1 shows memory map of TMP92CM22. 000000H Internal I/O Direct area(n) (8 Kbytes) 000100H 001FE0H 002000H 64-Kbyte area Internal RAM (nn) (32 Kbytes) 00A000H 010000H External memory F00000H Provisinal emulator control area (64 Kbytes) F10000H External memory 16-Mbyte area ( −...
  • Page 13 TMP92CM22 Clock Function and Standby Function TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reducing circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 System Clock Controller 3.3.4 Clock Doubler (PLL) 3.3.5 Noise Reduction Circuits 3.3.6 Standby Controller...
  • Page 14 TMP92CM22 The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset /32) OSCH Release reset Instruction IDLE2 mode Interrupt Instruction (I/O operation)
  • Page 15 TMP92CM22 3.3.1 Block Diagram of System Clock SYSCR2<WUPTM1:0> PLLCR<PLUPFG> Warm-up timer (for high-frequency oscillator)/lockup (for PLL) timer φT φT0 ÷4 ÷8 × 4 OSCH fc/2 fc/4 ÷2 PLLCR<PLLON> fc/8 ÷2 fc/16 SYSCR1<GEAR2:0> (Clock doubler) ÷2 ÷4 ÷8 ÷16 High- frequency Clock gear oscillator OSCH...
  • Page 16 TMP92CM22 3.3.2 SFRs − − SYSCR0 Bit symbol (10E0H) Read/Write After reset Function Always Always write “1”. write “0”. − SYSCR1 Bit symbol GEAR2 GEAR1 GEAR0 (10E1H) Read/Write After reset Function Always Select gear value of high- write “0”. frequency oscillator 000: High-frequency oscillator 001: High-frequency oscillator/2 010: High-frequency oscillator/4...
  • Page 17 TMP92CM22 Bit symbol PLLON FCSEL LWUPFG PLLCR (10E8H) Read/Write After reset 0: fc = Function 0: PLL warm-up stop OSCH flag 1: fc = 1: PLL 0: Don’t PLL (× 4) end up or stop 1: End up Note: Logic of PLLCR<LWUPFG> is different DFM of 900/L1. Figure 3.3.4 SFR for PLL −...
  • Page 18 TMP92CM22 3.3.3 System Clock Controller The system clock controller generates the system clock signal (f ) for the CPU core and internal I/O. It is used as input that fc outputted from high-frequency oscillation circuit and PLL (Clock doubler) SYSCR1<GEAR2:0>, SYSCR1<GEAR2:0> sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16).
  • Page 19 TMP92CM22 3.3.4 Clock Doubler (PLL) PLL outputs the f clock signal, which is four times as fast as f . A reset initializes OSCH PLL to stop status, setting to PLLCR register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lockup time. Note 1: Input frequency limitation for PLL The limitation of input frequency (High-frequency oscillation) for PLL is the following.
  • Page 20 TMP92CM22 Example 2: PLL stopping PLLCR 10E8H (PLLCR), 10XXXXXXB Changes fc from 40 MHz to10 MHz. (PLLCR), 00XXXXXXB Stop PLL. X: Don’t care <FCSEL> <PLLON> PLL output: f System clock f Changes from 40 MHz to 10 MHz. Stops PLL operation.
  • Page 21 TMP92CM22 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in for reduction EMI (Unnecessary radius noise) and reinforcement EMS (Measure of endure noise), allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Single drive for high-frequency oscillator (3) SFR protection of register contents These functions need setting by EMCCR0 to EMCCR2.
  • Page 22 TMP92CM22 (2) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) OSCH X1 pin < > Oscillation enable ( STOP EMCCR0 EXTIN EMCCR0<DRVOSCH>...
  • Page 23 TMP92CM22 (3) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that is in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller) is changed.
  • Page 24 TMP92CM22 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1, or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: IDLE2: Only the CPU halts.
  • Page 25 TMP92CM22 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. The details for release the halt status are shown in Table 3.3.3.
  • Page 26 TMP92CM22 Table 3.3.3 Source of Halt State Release and Halt Release Operation Interrupt Enable Interrupt Disable Status of Received Interrupt (Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask) HALT Mode IDLE1 STOP IDLE1 STOP Programmable IDLE2 Programmable IDLE2 ♦...

  • Page 27: Operation

    TMP92CM22 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt.
  • Page 28 TMP92CM22 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<SELDRV, DRVE> register. Table 3.3.5, Table 3.3.6 shows the state of these pins in STOP mode. After STOP mode has been released system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize.
  • Page 29 TMP92CM22 Table 3.3.5 Input Buffer State Table Input Buffer State In HALT mode (IDLE1/STOP) Input Buffer State Input Buffer State Input Condition A (Note) Condition B (Note) Port Function During Name When When When When When When When When Name Reset Used as Used as...
  • Page 30 TMP92CM22 Table 3.3.6 Output Buffer State Table Output Buffer State In HALT mode (IDLE1/STOP) When the CPU is In HALT Output Operating mode(IDLE2) Condition A (Note) Condition B (Note) Port Function During Name When When When When When When When When Name Reset...
  • Page 31 TMP92CM22 Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and by the built-in interrupt controller. The TMP92CM22 has a total of 41 interrupts divided into the following types: Interrupts generated by CPU: 9 sources (Software interrupts: 8 sources, illegal instruction interrupt: 1 source) External interrupts ( and INT0 to INT5): 7 sources Internal I/O interrupts: 17 sources...
  • Page 32 TMP92CM22 Interrupt processing Interrupt Micro DMA specified by soft start request micro DMA start vector? Clear interrupt request flag Interrupt vector “V” read Data transfer by Interrupt request F/F clear micro DMA Micro DMA processing General-purpose interrupt COUNT ← COUNT − 1 PUSH PC processing PUSH SR...
  • Page 33 TMP92CM22 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L, TLCS-900/H, and TLCS-900/L1. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request.
  • Page 34 TMP92CM22 Table 3.4.1 TMP92CM22 Interrupt Vectors and Micro DMA Start Vectors Address Vector Micro DMA Default Priority Type Interrupt Source Refer to Value Start Vector Vector Reset or “SWI0” instruction 0000H FFFF00H “SWI1” instruction 0004H FFFF04H “Illegal instruction” or “SWI2” instruction 0008H FFFF08H “SWI3”...
  • Page 35 TMP92CM22 Address Vector Micro DMA Default Priority Type Interrupt Source Refer to Value Start Vector Vector INTAD: AD conversion end 00CCH FFFFCCH INTTC0: Micro DMA end (Channel 0) 00D0H FFFFD0H INTTC1: Micro DMA end (Channel 1) 00D4H FFFFD4H INTTC2: Micro DMA end (Channel 2) 00D8H FFFFD8H INTTC3: Micro DMA end (Channel 3)
  • Page 36 TMP92CM22 3.4.2 Micro DMA In addition to general-purpose interrupt processing, the TMP92CM22 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source.
  • Page 37 TMP92CM22 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid).
  • Page 38 TMP92CM22 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP92CM22 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing “1” to each bit of DMAR register causes micro DMA once (If write “0” to each bit, micro DMA doesn’t operate).
  • Page 39 TMP92CM22 (4) Detailed description of the transfer mode register Mode DMAM0 to DMAM7 DMAM [4:0] Operation Execution Time Destination address INC mode 000 zz (DMADn +) ← (DMASn) 5 states ← DMACn − 1 DMACn If DMACn = 0 then INTTC Source address DEC mode 001 zz (DMADn −) ←...
  • Page 40 TMP92CM22 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 33 interrupts channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register.
  • Page 41 TMP92CM22 Figure 3.4.3 Block Diagram of Interrupt Controller 2007-02-16 92CM22-39...
  • Page 42 TMP92CM22 (1) Interrupt priority setting registers Symbol Name Address INT2 INT1 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INT1&INT2 INTE12 enable − INT3 − − − − I3M2 I3M1 I3M0 INT3 INTE3 − − enable Note: Always write “0”. INTTA1 (TMRA1) INTTA0 (TMRA0) INTTA0&...
  • Page 43 TMP92CM22 Symbol Name Address INTAD INT0 IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INT0&INTAD INTE0AD enable INTTC1 (DMA1) INTTC0 (DMA0) INTTC0& ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 INTETC01 INTTC1 enable INTTC3 (DMA3) INTTC2 (DMA2) INTTC2& ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2...
  • Page 44 TMP92CM22 (2) External interrupt control Symbol Name Address I3EDGE I2EDGE I1EDGE I0EDGE I0LE NMIREE Interrupt INT3EDGE INT2EDGE INT1EDGE INT0EDGE 00F6H INT0 input IIMC (Prohibit 0: Rising/ 0: Rising/ 0: Rising/ 0: Rising/ 0: Edge 0: Falling mode RMW) high high high high 1: Level...

  • Page 45: Setting Method

    TMP92CM22 Table 3.4.2 Function Setting of External Interrupt Pin Interrupt Pin Shared Pin Mode Setting Method IIMC<I0LE> = 0, INT0EDGE = 0 Rising edge IIMC<I0LE> = 0, INT0EDGE = 1 Falling edge INT0 IIMC<I0LE> = 1, INT0EDGE = 0 High level IIMC<I0LE>...
  • Page 46 TMP92CM22 (3) SIO receive interrupt control Symbol Name Address IR1LE IR0LE Interrupt SIMC (Prohibit 0: INTRX1 0: INTRX0 mode RMW) edge mode edge mode control 1: INTRX1 1: INTRX0 level mode level mode *INTRX1 level enables Detect edge INTRX1 “H” level INTRX1 *INTRX0 rising edge enable Detect edge INTRX0 “H”...
  • Page 47 TMP92CM22 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction.
  • Page 48 TMP92CM22 Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0 DMA0V start 100H vector DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1 DMA1V start 101H vector DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2 DMA2V start 102H vector...
  • Page 49 TMP92CM22 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer.
  • Page 50 TMP92CM22 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector.

  • Page 51: Port Function

    TMP92CM22 Port Function The TMP92CM22 features 50-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2 and Table 3.5.3 lists I/O registers and their specifications.

  • Page 52: Specification

    TMP92CM22 Table 3.5.2 I/O Port Setting List (1/2) I/O Register Setting Value Ports Input Pins Specification PnCR PnFC PnODE × Port 1 P10 to P17 Input port × None Output port × × D8 to D15 bus × Port 4 P40 to P47 Input port* ×...
  • Page 53 TMP92CM22 Table 3.5.3 I/O Port Setting List (2/2) I/O Register Setting Value Ports Input Pins Specification PnCR PnFC PnODE Port A PA0, PA1, Input port × None None None PA2, PA7 × Port C PC0, PC1, Input port PC3, PC5, Output port ×...
  • Page 54 TMP92CM22 3.5.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15).
  • Page 55 TMP92CM22 Port 1 Register Bit symbol (0004H) Read/Write After reset Data from external port (Output latch register is clear to “0”.) Port 1 Control Register P1CR (0006H) Bit symbol P17C P16C P15C P14C P13C P12C P11C P10C Read/Write After reset Function Refer to port 1 function setting Port 1 Function Register...
  • Page 56 TMP92CM22 3.5.2 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC*. In addition to functioning as a general-purpose I/O port, port 4 can also function as a address bus (A0 to A7).
  • Page 57 TMP92CM22 Port 4 Register Bit symbol (0010H) Read/Write After reset Data from external port (Output latch register is cleared to “0”.) Port 4 Control Register Bit symbol P47C P46C P45C P44C P43C P42C P41C P40C P4CR (0012H) Read/Write After reset Function 0: Input 1: Output (Note2) Port 4 Function Register...
  • Page 58 TMP92CM22 3.5.3 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC*. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15).
  • Page 59 TMP92CM22 Port 5 Register Bit symbol (0014H) Read/Write After reset Data from external port (Output latch register is cleared to “0”.) Port 5 Control Register Bit symbol P57C P56C P55C P54C P53C P52C P51C P50C P5CR (0016H) Read/Write After reset Function 0: Input 1: Output (Note2) Port 5 Function Register...
  • Page 60 TMP92CM22 3.5.4 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC*. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23).
  • Page 61 TMP92CM22 Port 6 Register Bit symbol (0018H) Read/Write After reset Data from external port (Output latch register is cleared to “0”.) Port 6 Control Register Bit symbol P67C P66C P65C P64C P63C P62C P61C P60C P6CR (001AH) Read/Write After reset Function 0: Input 1: Output (Note2) Port 6 Function Register...
  • Page 62 TMP92CM22 3.5.5 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P73 pins can also function as output pin of read/write strobe signals to connect with an external memory.
  • Page 63 TMP92CM22 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Port P7 Output latch P76 ( WAIT Output buffer P7 write P7 read Internal WAIT signal Figure 3.5.10 Port 7 (P76) Port 7 Register Bit symbol (001CH) Read/Write...
  • Page 64 TMP92CM22 3.5.6 Port 8 (P80 to P83) Port 8 is 4-bit output port. Resetting sets output latch of P82 to “0” and set output latches of P80, P81, and P83 to “1”. In addition to functioning as a output port, port 8 can also function as a output chip select signal ( These settings operate by programming “1”...
  • Page 65 TMP92CM22 3.5.7 Port 9 (P90 to P92) Port 9 is 3-bit general-purpose I/O port. Each bit can be set individually for input or output. In addition to functioning as a general-purpose I/O port, port 9 can also function as a serial bus interface input (SCK (Clock signal in SIO mode), SO (Data output signal in SIO mode), SDA (Data signal in I C bus mode), SI (Data input signal in SIO mode) and SCL...
  • Page 66 TMP92CM22 Port 9 Register Bit symbol (0024H) Read/Write After reset Data from external port (Output latch register is set to 1) Port 9 Control Register Bit symbol P92C P91C P90C P9CR P9CR (0026H) (0026H) Read/Write After reset Function 0: Input 1: Output Port 9 Function Register Bit symbol...
  • Page 67 TMP92CM22 3.5.8 Port A (PA0 to PA2, PA7) Port A is 4-bit general-purpose input port with pull-up resistor. Pull-up resistor PA0, PA1, PA2, PA7 PA read Figure 3.5.16 Port A Port A Register Bit symbol (0028H) Read/Write After reset Data from external port Data from external port Figure 3.5.17 Register for Port A...
  • Page 68 TMP92CM22 3.5.9 Port C (PC0, PC1, PC3, PC5, and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port C to input port. In addition to functioning as a general-purpose I/O port, port C can also function as a input/output pin (TA0IN, TA1OUT, TA3OUT, and TB0OUT0) and external interrupt pin (INT0 to INT3).
  • Page 69 TMP92CM22 (2) PC1 (INT1, TA1OUT), PC5 (INT2, TA3OUT), PC6 (INT3, TB0OUT0) In addition to function as I/O port, port PC1, PC5, and PC6 can also function as external interrupt input pin INT1 to INT3 and output pin of timer channel TA1OUT, TA3OUT, and TB0OUT0.
  • Page 70 TMP92CM22 (3) PC3 (INT0) In addition to function as I/O port, port PC3 can also function as external interrupt pin INT0. Reset Direction control (on bit basis) PCCR write Function control (on bit basis) PCFC write PC3 (INT0) Output latch PC read Selector PC read...
  • Page 71 TMP92CM22 Port C Register Bit symbol (0030H) Read/Write After reset Data from external Data from external Data from port (Note) port (Note) external port (Note) Note: Output latch register is set to 1. Port C Control Register Bit symbol PC6C PC5C PC3C PC1C...
  • Page 72 TMP92CM22 3.5.10 Port D (PD0 to PD3) Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port D to input port. In addition to functioning as a general-purpose I/O port, port D can also function as an input pin (INT4 and INT5)/output pin (TB0IN, TB1OUT, TB3OUT, and TB1OUT1).
  • Page 73 TMP92CM22 (2) PD2 (TB1OUT0) and PD3 (TB1OUT1) In addition to function as I/O port, port PD0 and PD1 can also function as timer channel output pins TB1OUT0 and TB1OUT1. Reset Direction control (on bit basis) PDCR write Function control (on bit basis) PDFC write PD2 (TB1OUT0) Output latch...
  • Page 74 TMP92CM22 Port D Register Bit symbol (0034H) Read/Write After reset Data from external port (Output latch register is set to 1) Port D Control Register Bit symbol PD3C PD2C PD1C PD0C PDCR (0036H) Read/Write After reset Function 0: Input 0: Input 0: Input 0: Input 1: Output...
  • Page 75 TMP92CM22 3.5.11 Port F (PF0 to PF7) Port F is 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting resets the PFCR and PFFC to “0”, and sets all bits to input port. And all bits of output latch register to “1”.
  • Page 76 TMP92CM22 (2) Ports PF1 and PF4 (RXD0 and XD1) In addition to function as I/O port, port PF1 and PF4 can also function as RXD input pin of serial channel. Reset Direction control (on bit basis) PFCR write PF1 (RXD0) Output latch PF4 (RXD1) PF write...
  • Page 77 TMP92CM22 (3) Port PF2 ( , SCLK0) and port PF5 ( , SCLK1) CTS0 CTS1 In addition to function as I/O port, port PF2 and PF5 can also function as input pin of serial channel or SCLK I/O pin. Reset Direction control (on bit basis) PFCR write...
  • Page 78 TMP92CM22 Port F Register Bit symbol (003CH) Read/Write After reset Data from external port (Output latch register is set to 1) Port F Control Register Bit symbol PF7C PF6C PF5C PF4C PF3C PF2C PF1C PF0C PFCR PFCR (003EH) (003EH) Read/Write After reset Function 0: Input...

  • Page 79: Port G Register

    TMP92CM22 3.5.12 Port G (PG0 to PG7) Port G is 8-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. Port G PG0 to PG7 PG read...

  • Page 80: Memory Controller

    TMP92CM22 Memory Controller 3.6.1 Function TMP92CM22 has a memory controller with a variable 4-block address area that controls as follows. 4-block address area support Specifies a start address and a block size for 4-block address area. Connecting memory specifications Specifies SRAM and ROM as memories to connect with the selected address areas. Data bus size selection Whether 8-bit or 16-bit is selected as the data bus size of the respective block address areas.

  • Page 81: Control Register

    TMP92CM22 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. •...
  • Page 82 TMP92CM22 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSAR) sets the start address of the block address areas.
  • Page 83 TMP92CM22 (iii) Example of register setting To set the block address area 1 to 512 bytes from address 110000H, set the register as follows. MSAR1 Register Bit symbol M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 Setting value M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16.
  • Page 84 TMP92CM22 (2) Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows. TMP92CM22 prohibit changing default (SRAM/ROM).
  • Page 85 TMP92CM22 CPU Data Data Size Start Data Width in (Bit) Address Memory Side (Bit) Address D15 to D8 D7 to D0 4n + 0 4n + 0 8/16 xxxxx b7 to b0 4n + 1 4n + 1 xxxxx b7 to b0 4n + 1 b7 to b0 xxxxx...

  • Page 86: Wait Control

    TMP92CM22 (4) Wait control = 20 The external bus cycle completes a wait of two states at least (100 ns at f MHz). Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as BnWR. BnWW/BnWR Bit (BnCSL Register) BnWW2 BnWR1...
  • Page 87 TMP92CM22 • When not inserting a dummy (0 waits) CLKOUT Address • When inserting a dummy cycle (0 waits) Dummy CLKOUT Address 92CM22-85 2007-02-16...
  • Page 88 TMP92CM22 (5) Bus access timing • External read/write bus cycle (0 waits) CLKOUT (20 MHz) Address Read D7 to D0 input Write D7 to D0 output • External read/write bus cycle (1 wait) CLKOUT (20 MHz) Address Read D7 to D0 Inpu Write D7 to D0...
  • Page 89 TMP92CM22 • External read/write bus cycle (0 waits at pin input mode) WAIT CLKOUT (20 MHz) Address Read D7 to D0 Input Write D7 to D0 Output WAIT Sampling • External read/write bus cycle (n waits at pin input mode) WAIT CLKOUT (20 MHz)
  • Page 90 TMP92CM22 Example of input cycle (5 waits) WAIT WAIT CLKOUT WRLL WRLU CLKOUT (20 MHz) FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT 92CM22-88 2007-02-16...
  • Page 91 TMP92CM22 (6) Connecting external memory Figure 3.6.1 shows an example of how to connect external memory to the TMP92CM22. This example connects ROM and SRAM in 16-bit width. TMP92CM22 16-bit SRAM WRLL WRLU D [15:0] I/O [16:1] Not connetion 16-bit ROM DQ [15:0] Figure 3.6.1 Example of External Memory By resetting, TMP92CM22 function as output port.
  • Page 92 TMP92CM22 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CM22 supports ROM access of the page mode. ROM access of the page mode is specified only in block address area 2.

  • Page 93: List Of Registers

    TMP92CM22 3.6.5 List of Registers The memory control registers and the settings are described as follows. For the addresses of the registers, see list of special function registers in section 5. (1) Control registers The control register is a pair of BnCSL and BnCSH. (“n” is a number of the block address area.) BnCSL has the same configuration regardless of the block address areas.
  • Page 94 TMP92CM22 B2REC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle B2OM[1:0] 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS[1:0] Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = (Reserved)
  • Page 95 TMP92CM22 BEXCSL Bit symbol BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 Read/Write After reset BEXWW[2:0] Specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 =...
  • Page 96 TMP92CM22 (1) Block address area specification register A start address and range in the block address are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start address similarly regardless of the block address areas.
  • Page 97 TMP92CM22 (2) Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in block address area 2. PMEMCR Bit symbol OPGE OPWR1 OPWR0 Read/Write After reset OPGE Enable bit. 0 = No ROM page mode accessing (Default) 1 = ROM page mode accessing OPWR [1:0] Specifies the number of waits.
  • Page 98 TMP92CM22 Table 3.6.1 Control Register B0CSL Bit symbol B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 (0140H) Read/Write After reset − − B0CSH Bit symbol B0REC B0OM1 B0OM0 B0BUS1 B0BUS0 (0141H) Read/Write After reset 0 (Note) 0 (Note) MAMR0 Bit symbol M0V20 M0V19 M0V18 M0V17...
  • Page 99 TMP92CM22 3.6.6 Caution If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip select signal, it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6.3 CLKOUT (20 MHz)
  • Page 100 TMP92CM22 (2) The cautions at the time of the functional change of a A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output (“1”...
  • Page 101 TMP92CM22 8-Bit Timers (TMRA) The TMP92CM22 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • 8-bit interval timer mode •...
  • Page 102 TMP92CM22 3.7.1 Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 2007-02-16 92CM22-100...
  • Page 103 TMP92CM22 Figure 3.7.2 TMRA23 Block Diagram 2007-02-16 92CM22-101...
  • Page 104 TMP92CM22 3.7.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The prescaler’s operation can be controlled using TA01RUN<TA0PRUN> in the timer control register. Setting <TA0PRUN> to “1” starts the count; setting <TA0PRUN> to “0” clears the prescaler to “0” and stops operation. Table 3.7.2 shows the various prescaler output clock resolutions.
  • Page 105 TMP92CM22 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes Active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows.
  • Page 106 TMP92CM22 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
  • Page 107 TMP92CM22 3.7.3 SFRs TMRA01 Run Register TA01RUN Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN (1100H) Read/Write After reset Function Double IDLE2 TMRA01 counter counter buffer 0: Stop prescaler (UC0) (UC1) 0: Disable 1: Operate 1: Enable 0: Stop and clear 1: Run (Count up) TA0REG double buffer control Count operation...
  • Page 108 TMP92CM22 TMRA01 Mode Register Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 TA01MOD (1104H) Read/Write After reset Function Operation mode PWM cycle TMRA1 source clock TMRA0 source clock 00: 8-bit timer mode 00: Reserved 00: TA0TRG 00: TA0IN pin input (Note) 01: φT1 01: φT1...
  • Page 109 TMP92CM22 TMRA23 Mode Register TA23MOD Bit symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 (110CH) Read/Write After reset Function Operation mode PWM cycle TMRA3 source clock TMRA2 source clock 00: 8-bit timer mode 00: Reserved 00: TA2TRG 00: Reserved 01: φT1 01: φT1 01: 16-bit timer mode...
  • Page 110 TMP92CM22 TMRA1 Flip Flop Control Register TA1FFCR Bit symbol TA1FFC1 TA1FFC0 TA1FFCIE TA1FFCIS (1105H) Read/Write After reset Function 00: Invert TA1FF TA1FF TA1FF Read-modify -write 01: Set TA1FF to “1” Inversion control for instruction is signal select 10: Clear TA1FF to “0” inversion prohibited.
  • Page 111 TMP92CM22 TMRA3 Flip-Flop Control Register TA3FFCR Bit symbol TA3FFC1 TA3FFC0 TA3FFCIE TA3FFCIS (110DH) Read/Write After reset Function 00: Invert TA3FF TA3FF TA3FF Read-modify -write control for inversion 01: Set TA3FF to “1” instruction is inversion select 10: Clear TA3FF to “0” prohibited.
  • Page 112 TMP92CM22 Timer Register (TA0REG to TA3REG) Symbol Address − TA0REG 1102H Undefined − TA1REG 1103H Undefined − TA2REG 110AH Undefined − TA3REG 110BH Undefined Note: Read-modify-write instruction is prohibited for above registers. Figure 3.7.9 Register for TMRA 2007-02-16 92CM22-110...
  • Page 113 TMP92CM22 Operation in Each Mode 3.7.4 (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. When set function and count data, TMRA0 and TMRA1 should be stopped. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively.
  • Page 114 TMP92CM22 Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4 μs square wave pulse from the TA1OUT pin at f = 40 MHz, use the following procedure to make the appropriate register settings.
  • Page 115 TMP92CM22 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator (Match output forTMRA0) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) Match output for TMRA1...
  • Page 116 TMP92CM22 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up-counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated.
  • Page 117 TMP92CM22 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>...
  • Page 118 TMP92CM22 = 40 MHz): Example: To generate 1/4 duty 62.5 kHz pulses (at f 16 μs Calculate the value that should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 μs φT1 (= (16/fc)s (at f = 40MHz);...
  • Page 119 TMP92CM22 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as PC1).
  • Page 120 TMP92CM22 In this mode, the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q Up counter = Q...

  • Page 121: Mode Settings

    TMP92CM22 Table 3.7.4 Relationship of PWM Cycle and 2 Counter PWM cycle TAxxMOD<PWMx1:0> Clock gear System clock − (x64) (x128) (x256) SYSCR1 SYSCR0 <GEAR2:0> <SYSCK> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) 000(x1) 1024/fc 4096/fc 16384/fc 2048/fc 8192/fc...
  • Page 122 TMP92CM22 16-Bit Timer/Event Counters (TMRB) The TMP92CM22 contains 2 channels 16-bit timer/event counter (TMRB) which have the following operation modes: • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) Can be used following operation modes by capture function: •...
  • Page 123 TMP92CM22 3.8.1 Block Diagram Figure 3.8.1 Block Diagram of TMRB0 2007-02-16 92CM22-121...
  • Page 124 TMP92CM22 Figure 3.8.2 Block Diagram of TMRB1 2007-02-16 92CM22-122...
  • Page 125 TMP92CM22 3.8.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) is a divided clock (Divided by 8) from selected clock by the register SYSCR1<GEAR1:0> of clock gear. This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting starts when <TB0PRUN>...
  • Page 126 TMP92CM22 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers TB0RG0H/L and TB0RG1H/L is always needed.
  • Page 127 TMP92CM22 (4) Capture registers (TB0CP0H/L, TB0CP1H/L, TB1CP0H/L and TB1CP1H/L) These 16-bit registers are used to latch the values in the up counters UC10. Data in the capture registers should be read both upper and lower all 16 bits. For example, using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order.
  • Page 128 TMP92CM22 (6) Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively).
  • Page 129 TMP92CM22 3.8.3 SFRs TMRB0 Run Register − TB0RUN Bit symbol TB0RDE I2TB0 TB0PRUN TB0RUN (1180H) Read/Write After reset Function Double Always IDLE2 TMRB0 Up counter buffer write “0”. UC10 0: Stop Prescaler 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count) Count operation...
  • Page 130 TMP92CM22 TMRB0 Mode Register − − TB0MOD Bit symbol TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 (1182H) Read/Write After reset Read-modify Function Always Always Software Capture timing Up counter TMRB0 source clock -write write “0”. write “0”. capture control 00: (Reserved) 00: Disable control instruction is...
  • Page 131 TMP92CM22 TMRB1 Mode Register TB1MOD Bit symbol TB1CT1 TB1ET1 TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0 (1192H) Read/Write After reset Function TB1FF1 Inversion trigger Software Capture timing Up counter TMRB1 source clock Read-modify capture control 00: TB1IN0 pin input 00: Disable -write 0: Trigger disable control...
  • Page 132 TMP92CM22 TMRB0 Flip-flop Control Register − − TB0FFCR Bit symbol TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FFC1 TB0FFC0 (1183H) Read/Write After reset Function Always write “11”. TB0FF0 inversion trigger TB0FF0 control Read-modify 0: Trigger disable 00: Invert -write 1: Trigger enable 01: Set instruction is 10: Clear Invert when...
  • Page 133 TMP92CM22 TMRB1 Flip-flop Control Register TB1FFCR Bit symbol TB1FF1C1 TB1FF1C0 TB1C1T1 TB1C0T1 TB1E1T1 TB1E0T1 TB1FFC1 TB1FFC0 (1193H) Read/Write After reset Function TB1FF1 control TB1FF0 inversion trigger TB1FF0 control Read-modify 00: Invert 0: Trigger disable 00: Invert -write 01: Set 1: Trigger enable 01: Set instruction is 10: Clear...
  • Page 134 TMP92CM22 TMRB0 register − TB0RG0L bit Symbol (1188H) Read/Write After reset Undefined − TB0RG0H bit Symbol (1189H) Read/Write After reset Undefined − TB0RG1L bit Symbol (118AH) Read/Write After reset Undefined − TB0RG1H bit Symbol (118BH) Read/Write After reset Undefined − TB0CP0L bit Symbol (118CH)
  • Page 135 TMP92CM22 3.8.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals in this example, the interval time is set the timer register TB0RG1H/L to generate the interrupt INTTB01. 7 6 5 4 3 2 1 0 ←...
  • Page 136 TMP92CM22 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and to be output to TB0OUT0.
  • Page 137 TMP92CM22 The following block diagram illustrates this mode. TB0OUT0 (PPG output) TB0RUN<TB0RUN> Selector TB0IN0 φT1 16-bit up counter φT4 Clear (TB0FF0) UC10 φT16 Matching 16-bit comparator 16-bit comparator TB0RG0H/L Selector TB0RG0-WR Register buffer 10 TB0REG1H/L TB0RUN<TB0RDE> Internal data bus Figure 3.8.11 Block Diagram of 16-Bit PPG Mode The following example shows how to set 16-bit PPG output mode: 7 6 5 4 3 2 1 0 ←...
  • Page 138 TMP92CM22 (4) Capture function examples Used capture function, they can be applicable in many ways, for example: One-shot pulse output from external trigger pulse Frequency measurement Pulse width measurement Measurement of difference time One-shot pulse output from external trigger pulse Set the up counter UC12 in free-running mode with the internal input clock, input the external trigger pulse from TB1IN0 pin, and load the value of up counter into capture register TB1CP0H/L at the rise edge of external trigger...
  • Page 139 TMP92CM22 Example: To output a 2 [ms] one-shot pulse with a 3 [ms] delay to the external trigger pulse via the TB1IN0 pin. * Clock state : Clock gear 1/1 (fc) Setting in Main Set free running. Count using φT1. ←...
  • Page 140 TMP92CM22 Count clock (Prescaler output clock) c + p TB1IN0 input Load into capture register TB1CP0H/L (External trigger pulse) Load into capture register 1 generate INT4. TB1CP1H/L. Generate INTTB11. Match with TB1RG1H/L Inversion enable Timer output TB1OUT0 pin Pulse width Set it to disable that inversion caused by loading into TB1CP1H/L.
  • Page 141 TMP92CM22 Pulse width measurement This mode allows measuring the high level width of an external pulse. While keeping the 16-bit timer/event counter counting (Free running) with the prescaler output clock input, external pulse is input through the TB1IN0 pin. Then the capture function is used to load the UC12 values into TB1CP0H/L and TB1CP1H/L at the rising edge and falling edge of the external trigger pulse respectively.
  • Page 142 TMP92CM22 Measurement of difference time This mode is used to measure the difference in time between the rising edges of external pulses input through TB1IN0 and TB1IN1. Keep the 16-bit timer/event counter (TMRB1) counting (Free running) with the prescaler output clock, and load the UC12 value into TB1CP0H/L at the rising edge of the input pulse to TB1IN0.
  • Page 143 TMP92CM22 Serial Channels (SIO) The TMP92CM22 includes 2 serial I/O channels. Each channel is called SIO0 and SIO1. For both channels either UART Mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. • I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O.
  • Page 144 TMP92CM22 • Mode 0 (I/O interface mode) Bit0 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 Stop Parity Start Bit0 Parity Stop • Mode 2 (8-bit UART mode) No parity Start Bit0 Stop Parity Start Bit0 Parity Stop •...

  • Page 145: Block Diagram

    TMP92CM22 3.9.1 Block Diagram Prescaler φT0 4 8 16 32 φT2 φT8 φT32 Serial clock generation circuit BR0CR<BR0CK1:0> BR0CR BR0ADD TA0TRG <BR0S3:0> <BR0K3:0> (from TMRA0) φT0 φT2 UART φT8 mode SIOCLK φT32 BR0CR <BR0ADDE> SC0MOD0 Baud rate generater <SC1:0> SC0MOD0 <SM1:0>...
  • Page 146 TMP92CM22 Prescaler φT0 4 8 16 32 φT2 φT8 φT32 Serial clock generation circuit BR1CR<BR1CK1:0> BR1CR BR1ADD TA0TRG <BR1S3:0> <BR1K3:0> (from TMRA0) φT0 φT2 UART φT8 mode SIOCLK φT32 BR1CR <BR1ADDE> SC1MOD0 Baud rate generater <SC1:0> SC1MOD0 <SM1:0> ÷ 2 I/O interface mode SCLK1 input (Shared...
  • Page 147 TMP92CM22 3.9.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR1<GEAR2:0> is divided by 8 and input to the prescaler as φT0. The prescaler can be run only case of selecting the baud rate generator as the serial transfer clock. Table 3.9.2 shows prescaler clock resolution into the baud rate generator.
  • Page 148 TMP92CM22 (2) Baud rate generator The baud rate generator is a circuit that generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8, or φT32, is generated by the 6-bit prescaler which is shared by the timers.
  • Page 149 TMP92CM22 • Integer divider (N divider) For example, when the f = 39.3216 MHz, the input clock frequency = φT2, the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows: ∗...
  • Page 150 TMP92CM22 Table 3.9.3 UART Baud Rate Selection (when using baud rate generater and BR0CR<BR0ADDE> = 0) Unit (kbps) Input Clock φT0 φT2 φT8 φT32 [MHz] /16) /64) /256) Frequency Divider 9.8304 76.800 19.200 4.800 1.200 ↑ 38.400 9.600 2.400 0.600 ↑...
  • Page 151 TMP92CM22 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously.
  • Page 152 TMP92CM22 (6) The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF);...
  • Page 153 TMP92CM22 Handshake function Use of pin allows data to be sent in units of one data format; thus, overrun CTS0 errors can be avoided. The handshake function is enabled or disabled by the SC0MOD0<CTSE> setting. When the pin condition is high level, after completed the current data CTS0 transmission, data transmission is halted until the pin state is low again.
  • Page 154 TMP92CM22 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt.

  • Page 155: Parity Error

    TMP92CM22 Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. Framing error <FERR> The stop bit for the received data is sampled three times around the center.
  • Page 156 TMP92CM22 3.9.3 SFRs SC0MOD0 Bit symbol CTSE (1202H) Read/Write After reset Function Transfer Handshake Receive Wakeup Serial transmission Serial transmission clock data bit8 function control function mode (UART) control 0: Receive 0: Disable 00: I/O interface mode 00: Timer A0 trigger 0: CTS disable 1: Enable...
  • Page 157 TMP92CM22 SC1MOD0 Bit symbol CTSE (120AH) Read/Write After reset Function Transfer Handshake Receive Wakeup Serial transmission Serial transmission clock data bit8 function control function mode (UART) control 0: Receive 0: Disable 00: I/O interface mode 00: Timer A0 trigger 0: CTS disable 1: Enable 01: 7-bit UART mode...
  • Page 158 TMP92CM22 SC0CR Bit symbol EVEN OERR PERR FERR SCLKS (1201H) Read/Write R (Cleared to 0 when read) After reset Undefined Function Received 1: Error 0: SCLK0 Parity Parity 0: Baud rate data bit8 0: Odd addition generator Overrun Parity Framing 1: Even 1: SCLK0 1: SCLK0...
  • Page 159 TMP92CM22 SC1CR Bit symbol EVEN OERR PERR FERR SCLKS (1209H) Read/Write R (Cleared to 0 when read) After reset Undefined Function Received 1: Error 0: SCLK1 Parity Parity 0: Baud rate data bit8 0: Odd addition generator Overrun Parity Framing 1: Even 1: SCLK1 1: SCLK1...
  • Page 160 TMP92CM22 − BR0CR Bit symbol BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 (1203H) Read/Write After reset + (16 − K)/16 00: φT0 Function Always write “0”. division 01: φT2 Divided frequency setting 0: Disable 10: φT8 1: Enable 11: φT32 + (16 −...
  • Page 161 TMP92CM22 − BR1CR Bit symbol BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 (120BH) Read/Write After reset + (16 − K)/16 00: φT0 Function Always write “0”. division 01: φT2 Divided frequency setting 10: φT8 0: Disable 11: φT32 1: Enable + (16 −...
  • Page 162 TMP92CM22 TB0 (for transmission) SC0BUF (1200H) RB0 (for receiving) Note: Prohibit read-modify-write for SC0BUF Figure 3.9.13 Serial Transmission/Receiving Buffer Register (for SIO0 and SC0BUF) SC0MOD1 Bit symbol I2S0 FDPX0 (1205H) Read/Write After reset Function IDLE2 Duplex 0: Stop 0: Half 1:Run 1: Full Figure 3.9.14 Serial Mode Control Regsiter (for SIO and SC0MOD1)
  • Page 163 TMP92CM22 3.9.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK.
  • Page 164 TMP92CM22 Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all data is outputted, INTES0<ITX0C> will be set to generate the INTTX0 interrupt.
  • Page 165 TMP92CM22 Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are received, the data will be transferred to receiving buffer 2 (SC0BUF according to the timing shown below) and INTES0<IRX0C>...
  • Page 166 TMP92CM22 Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to “0” and set enable the interrupt level (1 to 6) to the transfer interrupts. In the transfer interrupt program, the receiving operation should be done like the below example before setting the next transfer data.
  • Page 167 TMP92CM22 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting serial channel mode register SC0MOD0<SM1:0> to 01. In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR<PE>...
  • Page 168 TMP92CM22 (4) Mode 3 (9-bit UART mode) 9-bit UART mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is programmed to SC0MOD0<TB8>. In the case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read, the MSB is read or written first, before the rest of the SC0BUF data.
  • Page 169 TMP92CM22 Protocol Select 9-bit UART mode on the master and slave controllers. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (Bit8) <TB8> is set to “1”. Start Bit0 Stop...
  • Page 170 TMP92CM22 Example: To link two slave controllers serially with the master controller using the system clock f as the transfer clock. Master Slave 1 Slave 2 Select code Select code 00000001 00001010 • Master controller setting Main routine ← − − − − − − 0 1 PFCR Set PF0 to TXD0, and set PF1 to RXD0 pin.
  • Page 171 TMP92CM22 3.9.5 Support for IrDA Mode SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. TXD0 Transmission IR modulator IR transmitter & LED data IR output SIO0 Modem IR module RXD0 Receive IR receiver demodulator data...
  • Page 172 TMP92CM22 (3) Data format Format of transmission/receiving must set to data length 8-bit, without parity bit, 1 bit of stop bit. Any other settings don’t guarantee the normal operation. (4) SFR Figure 3.9.27 shows the control register SIRCR. If change setting this register, must set it after set operation of transmission/receiving to disable (Both <TXEN>...
  • Page 173 TMP92CM22 As the same reason, + (16 − K)/16 division function in the baud rate generator of SIO0 cannot be used to generate 115.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 division function cannot be used.
  • Page 174 TMP92CM22 3.10 Serial Bus Interface (SBI) The TMP92CM22 has a 1-channel serial bus interface. Serial bus interface (SBI0) include following 2 operation modes. • C bus mode (Multi master) • Clocked-synchronous 8-bit SIO mode The serial bus interface is connected to an external device through P91 (SDA) and P92 (SCL) in the I C bus mode;...
  • Page 175 TMP92CM22 3.10.2 Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface 0 control register 1 (SBI0CR1) • Serial bus interface 0 control register 2 (SBI0CR2) • Serial bus interface 0 data buffer register (SBI0DBR) •...
  • Page 176 TMP92CM22 3.10.4 C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I C bus mode. Serial Bus Interface Control Register 1 SBI0CR1 SCK0/ Bit symbol SCK2 SCK1...
  • Page 177 TMP92CM22 Serial Bus Interface Control Register 2 SBI0CR2 Bit symbol SBIM1 SBIM0 SWRST1 SWRST0 (1243H) Read/Write W (Note 1) W (Note 1) After reset Serial bus interface Software reset control Read- Function Master/ Transmitter/ Start/stop Release operation mode selection write “10” and “01” in modify-write slave receiver...
  • Page 178 TMP92CM22 Serial Bus Interface Status Register SBI0SR Bit symbol (1243H) Read/Write After reset Arbitration Last Slave address GENERAL Read- Function Master/ Transmitter/ C bus INTSBE0 lost received bit match CALL modify-write slave receiver status interrupt detection monitor instruction is status status monitor request...
  • Page 179 TMP92CM22 Serial Bus Interface Baud Rate Register 0 − SBI0BR0 Bit symbol I2SBI0 (1244H) Read/Write After reset Read- IDLE2 Function Always modify-write 0: Stop write “0”. instruction is 1: Run prohibited. Operation during IDLE 2 mode Stop Serial Bus Interface Baud Rate Register 1 −...
  • Page 180 TMP92CM22 3.10.5 Control in I C Bus Mode (1) Acknowledge mode specification Set the SBI0CR1<ACK> to 1 for operation in the acknowledge mode. The TMP92CM22 generates an additional clock pulse for an acknowledge signal when operating in master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver.
  • Page 181 TMP92CM22 Clock synchronization In the I C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to low level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure.
  • Page 182 TMP92CM22 (6) Transmitter/receiver selection Set the SBI0CR2<TRX> to “1” for operating the TMP92CM22 as a transmitter. Clear the <TRX> to “0” for operation as a receiver. In slave mode, when transfer data in addressing format, when received slave address is same value with setting value to I2C0AR, or GENERAL CALL is received (All 8-bit data are “0”...
  • Page 183 TMP92CM22 (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 (INTSBE0) occurs, the SBI0SR2 <PIN> is cleared to “0”. During the time that the SBI0SR2<PIN> is “0”, the SCL line is pulled down to the low level. The <PIN>...
  • Page 184 TMP92CM22 The TMP92CM22 compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBI0SR<AL> is set to “1”. When SBI0SR<AL>...
  • Page 185 TMP92CM22 (14) Software reset function The software reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. When write first “10” next “01” to SBI0CR2<SWRST1:0>, reset signal is inputted to serial bus interface circuit, and circuit is initialized. All command registers except SBI0CR2<SBIM1:0>...

  • Page 186: Device Initialization

    TMP92CM22 3.10.6 Data Transfer in I C Bus Mode (1) Device initialization In first, set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2:0>. Set SBI0BR1<P4EN> to “1” and clear bits 7 to 5 and 3 in the SBI0CR1 to “0”. Next, set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format) to the I2C0AR.
  • Page 187 TMP92CM22 SCL line SDA line Acknowledge signal from a Start condition Slave address + Direction bit slave device <PIN> INTSBE0 interrupt request Output of master Output of slave Figure 3.10.13 Start Condition and Slave Address Generation (3) 1-word data transfer Check the <MST>...
  • Page 188 TMP92CM22 When the <TRX> is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and read the received data from SBI0DBR to release the SCL line (Data which is read immediately after a slave address is sent is undefined). After the data is read, <PIN>...
  • Page 189 TMP92CM22 If <MST> = 0 (Slave mode) In the slave mode the TMP92CM22 operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBE0 interrupt request generate when the TMP92CM22 receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is completed, or after matching received address.
  • Page 190 TMP92CM22 (4) Stop condition generation When SBI0SR<BB> = 1, the sequence for generating a stop condition is started by writing “111” to SBI0CR2<MST, TRX, PIN> and “0” to SBI0CR2<BB>. Do not modify the contents of SBI0CR2<MST, TRX, PIN, BB> until a stop condition has been generated on the bus.
  • Page 191 TMP92CM22 (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when this device is in the master mode. Clear the SBI0CR2<MST, TRX, BB> to “000” and set the SBI0CR2<PIN> to “1” to release the bus.
  • Page 192 TMP92CM22 3.10.7 Clocked-synchronous 8-bit SIO Mode Control The following registers are used to control and monitor the operation status when the serial bus interface (SBI) is being operated in clocked synchronous 8-bit SIO mode. Serial Bus Interface 0 Control Register 1 SBI0CR1 Bit symbol SIOS...
  • Page 193 TMP92CM22 Serial Bus Interface 0 Control Register 2 − − SBI0CR2 Bit symbol SBIM1 SBIM0 (1243H) Read/Write After reset Serial bus interface Read- Function (Note 2) (Note 2) operation mode selection modify-write 00: Port mode instruction is 01: SIO mode prohibited.
  • Page 194 TMP92CM22 (1) Serial Clock Clock source SBI0CR1<SCK2:0> is used to select the following functions: Internal clock In internal clock mode one of seven frequencies can be selected. The serial clock signal is output to the outside on the SCK pin. When the device is writing (in transmit mode) or reading (in receive mode), data cannot follow the serial clock rate, so an automatic wait function is executed which automatically stops the serial clock and holds the next shift operation until...
  • Page 195 TMP92CM22 Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK pin input/output). Trailing edge shift Data is shifted on the trailing edge of the serial clock (on the rising edge of the SCK pin input/output).
  • Page 196 TMP92CM22 (2) Transfer modes The SBI0CR1<SIOM1:0> is used to select a transmit, receive or transmit/receive mode. 8-bit transmit mode Set a control register to a transmit mode and write transmission data to the SBI0DBR. After the transmit data has been written, set the SBI0CR1<SIOS> to “1” to start data transfer.
  • Page 197 TMP92CM22 Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin (Output) SO pin INTSBE0 interrupt request SBI0DBR Writing transmission data (a) Internal clock Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin (Input) SO pin INTSBE0 interrupt request SBI0DBR Writing transmission data (b) External clock Figure 3.10.25 Transmission Mode Example: Program to stop data transmission (when an external clock is used) ;...
  • Page 198 TMP92CM22 SCK pin <SIOF> Bit6 Bit7 SO pin = 3.5/f [s] (Min) SODH Figure 3.10.26 Transmission Data Hold Time at End Transmit 8-bit receive mode Set the control register to receive mode and set the SBI0CR1<SIOS> to “1” for switching to receive mode. Data is received into the shift register via the SI pin and synchronized with the serial clock, starting from the least significant bit (LSB).
  • Page 199 TMP92CM22 Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin (Output) SI pin INTSEB0 interrupt request SBI0DBR Read receive data Read receive data Figure 3.10.27 Receiver Mode (Example: Internal clock) 8-bit transmit/receive mode Set a control register to a transmit/receive mode and write data to the SBI0DBR. After the data is written, set the SBI0CR<SIOS>...
  • Page 200 TMP92CM22 Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin (Output) SO pin SI pin INTSBE0 Interrupt interrupt SBI0DBR Write transmission data (a) Write transmission data (b) Read receiving data (d) Read receiving data (c) Figure 3.10.28 Transmission/Receiving Mode (when an external clock is used) SCK pin <SIOF>...
  • Page 201 TMP92CM22 3.11 Analog/Digital Converter The TMP92CM22 incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are shared with the input-only port G so they can be used as an input port. Note: When IDLE2, IDLE1, or STOP mode is selected, as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled.
  • Page 202 TMP92CM22 3.11.1 Analog/Digital Converter Registers The AD converter is controlled by the three AD mode control registers: ADMOD0, ADMOD1, and ADMOD2. The eight AD conversion data result registers (ADREG0H/L to ADREG7H/L) store the results of AD conversion. Figure 3.11.2 shows the registers related to the AD converter. AD Mode Control Register 0 −...
  • Page 203 TMP92CM22 AD Mode Control Register 1 − − − ADMOD1 Bit symbol VREFON I2AD ADCH2 ADCH1 ADCH0 (12B9H) Read/Write After reset Function VREF IDLE2 Always Always write Always Analog input channel selection application write “0”. “0”. write “0”. 0: Stop control 1: Operate 0: OFF...
  • Page 204 TMP92CM22 AD Conversion Result Register 0 Low ADREG0L Bit symbol ADR01 ADR00 ADR0RF (12A0H) Read/Write After reset Undefined Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1: Conversion result stored AD Conversion Result Register 0 High ADREG0H Bit symbol ADR09...
  • Page 205 TMP92CM22 AD Conversion Result Register 2 Low ADREG2L Bit symbol ADR21 ADR20 ADR2RF (12A4H) Read/Write After reset Undefined Function Stores lower 2 bits of AD AD conversion conversion result. data storage flag 1: Conversion result stored AD Conversion Result Register 2 High ADREG2H Bit symbol ADR29...
  • Page 206 TMP92CM22 AD Conversion Result Register 4 Low ADREG4L Bit symbol ADR41 ADR40 ADR4RF (12A8H) Read/Write After reset Undefined Function Stores lower 2 bits of AD AD conversion conversion result. data storage flag 1: Conversion result stored AD Conversion Result Register 4 High ADREG4H Bit symbol ADR49...
  • Page 207 TMP92CM22 AD Conversion Result Register 6 Low ADREG6L Bit symbol ADR61 ADR60 ADR6RF (12ACH) Read/Write After reset Undefined Function Stores lower 2 bits of AD AD conversion conversion result. data storage flag 1:Conversion result stored AD Conversion Result Register 6 High ADREG6H Bit symbol ADR69...
  • Page 208 TMP92CM22 3.11.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance.
  • Page 209 TMP92CM22 (3) Starting AD conversion To start AD conversion, program “1” to ADMOD0<ADS> in AD mode control register 0, or ADMOD1<ADTRGE> in AD mode control register 1 and input falling edge on ADTRG pin. When AD conversion starts, the AD conversion busy flag ADMOD0<ADBF>...
  • Page 210 TMP92CM22 Channel fixed repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to “10” selects conversion channel fixed repeat conversion mode. In this mode data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0<EOCF> is set to “1” and ADMOD0<ADBF>...
  • Page 211 TMP92CM22 (5) AD conversion time 84 states (8.4 μs at f = 20 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREG0H/L to ADREG7H/L) store the results of AD conversion.
  • Page 212 TMP92CM22 Example: Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the AD interrupt (INTAD) processing routine. Setting of main routine 7 6 5 4 3 2 1 0 INTE0AD ← X 1 0 0 − − − − Enable INTAD and set it to interrupt level 4.
  • Page 213 TMP92CM22 3.12 Watchdog Timer (Runaway detection timer) The TMP92CM22 contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction.
  • Page 214 TMP92CM22 3.12.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared “0” in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
  • Page 215 TMP92CM22 3.12.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway.
  • Page 216 TMP92CM22 − − WDMOD Bit symbol WDTE WDTP1 WDTP0 I2WDT RESCR (1300H) Read/Write After reset Function WDT control Select detecting time Always IDLE2 1: Internally Always write “0” connects write “0” 1: Enable 00: 2 0: Stop WDT out 01: 2 1: Operate to the 10: 2...

  • Page 217: Electrical Characteristics

    TMP92CM22 Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit −0.5 to 4.0 Power supply voltage −0.5 to Vcc + 0.5 Input voltage Output current (1 pin) −2 Output current (1 pin) ΣIOL Output current (Total) ΣIOH −80 Output current (Total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) TSOLDER...
  • Page 218 TMP92CM22 DC Characteristics (1/2) Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C Parameter Condition Typ. Unit Symbol fc = 4 to 40 MHz Power supply voltage = 125 kHz to 20 MHz) (DVCC = AVCC) (DVSS = AVSS = 0 V) Input low voltage P00 to P07 (D0 to D7)
  • Page 219 TMP92CM22 DC Characteristics (2/2) Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C Parameter Condition Typ. Unit Symbol IOL = 1.6 mA Output low voltage 0.45 IOH = −400 μA Output high voltage 0.0 ≤ Vin ≤ VCC Input leakage current 0.02 μA...

  • Page 220: Read Cycle

    TMP92CM22 AC Characteristics 4.2.1 Basis Bus Cycle Read cycle Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C Parameter Symbol 20 MHz 125 kHz Unit (fc = 40 MHz) (fc = 4 MHz) OSC period (X1/X2) System clock period (= T) 8000 8000...
  • Page 221 TMP92CM22 (1) Read cycle (0 waits, fc = f = fc/1) OSCH CLKOUT WAIT A0 to A23 D0 to D31 Data input Note: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. 2007-02-16 92CM22-219...
  • Page 222 TMP92CM22 (2) Write cycle (0 waits, fc = f = fc/1) OSCH CLKOUT WAIT A0 to A23 WRxx Data output D0 to D31 Note: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. 2007-02-16 92CM22-220...
  • Page 223 TMP92CM22 (3) Read cycle (1 wait) CLKOUT WAIT A0 to A23 D0 to D31 Data input (4) Write cycle (1 wait) CLKOUT WAIT A0 to A23 WRxx D0 to D31 Data output 2007-02-16 92CM22-221...
  • Page 224 TMP92CM22 4.2.2 Page ROM Read Cycle (1) 3-2-2-2 mode Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = − 40 to 85°C Parameter Symbol 20 MHz 125 kHz Unit (fc = 40 MHz) (fc = 4 MHz) System clock period ( = T) 8000 8000...

  • Page 225: Ad Conversion Characteristics

    TMP92CM22 AD Conversion Characteristics Parameter Symbol Typ. Unit Analog reference voltage ( + ) VCC − 0.2 REFH Analog reference voltage ( − ) VSS + 0.2 REFL AD converter power supply voltage AD converter power supply ground Analog input voltage VREFL VREFH Analog current for analog reference voltage...
  • Page 226 TMP92CM22 Serial Channel Timing (I/O interface mode) Note: Symbol “X” in the following table means the period of clock “f ”, it’s same period of the system clock “f ” for CPU core. The period of f depends on the clock gear setting or changing high-speed oscillator/low-speed oscillator and so on.
  • Page 227 TMP92CM22 SCLK Output mode/ input rising mode SCLK (Input falling mode) Output data Input data Valid Valid Valid Valid Interrupt, Capture Note: Symbol “X” in the following table means the period of clock “f ”, it’s same period of the system clock “f ”...
  • Page 228 TMP92CM22 Recommended Oscillation Circuit TMP92CM22 is evaluated by below oscillator vender. When selecting external parts, make use of this information. Note 1: Total loads value of oscillation is sum of external (or internal) loads (C1 and C2) and floating loads of actual assemble board. There is a possibility of miss operating using C1 and C2 values in below table.
  • Page 229 TMP92CM22 (2) TMP92CM22 recommended ceramic oscillator: Murata Manufacturing Co., Ltd. Following table shows circuit parameter recommended. Oscillation Parameter of Elements Running Condition Item of Oscillator IC Name Frequency Type Voltage of (Old number) Tc [ ° [MHz] [pF] [pF] [Ω] [Ω] Power [V] CSTCR4M00G55-R0...
  • Page 230 TMP92CM22 Table of Special Function Registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 8 Kbytes address space from 000000H to 001FFFH. (1) I/O port (2) Interrupt controller (3) DMA controller (4) Memory controller (5) Clock gear/PLL (6) 8-bit timer (7) 16-bit timer...
  • Page 231 TMP92CM22 Table 5.1 I/O Register Address Map [1] I/O port Address Address Address Address Name Name Name Name 0000H 0010H 0020H 0030H P4CR PCCR P4FC P8FC PCFC P9ODE P1CR P5CR P9CRP PDCR P1FC P5FC PDFC P6CR P6FC P7CR PFCR P7FC PFFC Address Name...

  • Page 232: Interrupt Controller

    TMP92CM22 [2] Interrupt controller DMA controller Address Address Address Address Name Name Name Name 00D0H INTE12 00E0H INTE45 00F0H INTE0AD 0100H DMA0V INTE3 INTETB1 INTETC01 DMA1V INTETBO1 INTETC23 DMA2V INTESB0 INTETC45 DMA3V INTETA01 INTETC67 DMA4V INTETA23 SIMC DMA5V IIMC DMA6V INTWDT DMA7V INTETB0...
  • Page 233 TMP92CM22 [6] 8-bit timer [7] 16-bit timer [8] UART/SIO Address Name Address Name Address Name Address Name 1100H TA01RUN 1180H TB0RUN 1190H TB1RUN 1200H SC0BUF SC0CRS TA0REG TB0MOD TB1MOD C0MOD0 TA1REG TB0FFCR TB1FFCR BR0CR TA01MOD BR0ADD TA1FFCR SC0MOD1 SIRCR TA23RUN TB0RG0L TB1RG0L SC1BUF...
  • Page 234 TMP92CM22 (1) I/O port (1/3) Symbol Name Address Port 1 0004H Data from external port (Output latch register is cleared to “0”) Port 4 0010H Data from external port (Output latch register is cleared to “0”) Port 5 0014H Data from external port (Output latch register is cleared to “0”) Port 6 0018H Data from external port (Output latch register is cleared to “0”)
  • Page 235 TMP92CM22 I/O port (2/3) Symbol Name Address P17C P16C P15C P14C P13C P12C P11C P10C Port 1 0006H P1CR control (Prohibit RMW) register 0: Input 1: Output Port 1 0007H P1FC function (Prohibit 0: Port RMW) register 1: Data bus (D8 to D15) P47C P46C...
  • Page 236 TMP92CM22 I/O port (3/3) Symbol Name Address P92C P91C P90C Port 9 0026H P9CR control (Prohibit RMW) register 0: Input 1: Output P92F P91F P90F 0027H Port 9 0: Port, SI 0: Port 0: Port, SCK P9FC (Prohibit function input RMW) 1: SCL 1: SO, SDA...
  • Page 237 TMP92CM22 (2) Interrupt control (1/2) Symbol Name Address INT2 INT1 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INT1 & INT2 INTE12 00D0H enable 1: INT2 1: INT1 Interrupt request level. Interrupt request level − INT3 − − − − I3M2 I3M1 I3M0 INT3 −...
  • Page 238 TMP92CM22 Interrupt control (2/2) Symbol Name Address − INTP0 − − − − IP0C IP0M2 IP0M1 IP0M0 INTP0 − − − − INTEP0 00EEH enable 1: INTP0 Always write “0”. Interrupt request level INTAD INT0 IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INT0 &...
  • Page 239 TMP92CM22 (3) DMA controller Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0 start DMA0V 0100H vector DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1 start DMA1V 0101H vector DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2 start...
  • Page 240 TMP92CM22 (4) Memory controller (1/2) Symbol Name Address B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 Block 0 MEMC 0140H Write waits Read waits B0CSL control (Prohibit 001: 0 waits 010: 1 wait 001: 0 waits 010: 1 wait register RMW) 101: 2 waits 110: 3 waits 101: 2 waits 110: 3 waits...
  • Page 241 TMP92CM22 Memory controller (2/2) Symbol Name Address BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 Block EX MEMC 0158H Write waits Read waits BEXCSL (Prohibit control 001: 0 waits 010: 1 wait 001: 0 waits 010: 1 wait RMW) register 101: 2 waits 110: 3 waits 101: 2 waits 110: 3 waits...
  • Page 242 TMP92CM22 (5) Clock gear Symbol Name Address − − System SYSCR0 clock 10E0H control 0 Always Always write “1”. write “0”. − GEAR2 GEAR1 GEAR0 Always Select gear value of high frequency write “0”. (fc) System 000: fc SYSCR1 clock 10E1H 001: fc/2 control 1...
  • Page 243 TMP92CM22 (6) 8-bit timer Symbol Name Address TA0RDE I2TA01 TA1RUN TA0RUN TA01PRUN TMRA01 TA01RUN 1100H Double IDLE2 TMRA01 UP counter UP counter register buffer 0: Stop prescaler (UC1) (UC0) 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) −...
  • Page 244 TMP92CM22 (7) 16-bit timer (1/2) Symbol Name Address − TB0RDE I2TB0 TB0PRUN TB0RUN Timer B0 TB0RUN 1180H Double Always IDLE2 TMRB0 UP counter register buffer write “0”. 0: Stop prescaler (UC10) 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) −...
  • Page 245 TMP92CM22 16-bit timer (2/2) Symbol Name Address − TB1RDE I2TB0 TB1PRUN TB1RUN Timer B1 TB1RUN 1190H TMRB1 UP counter Double Always IDLE2 prescaler (UC12) register write “0”. buffer 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable TB1CT1 TB1ET1...
  • Page 246 TMP92CM22 (8) UART/Serial channel (1/2) Symbol Name Address Serial 1200H channel 0 SC0BUF (Prohibit R(Receiving) / W(Transmission) buffer RMW) Undefined register EVEN OERR PERR FERR SCLKS R (Clear o after reading) Serial Undefined channel 0 SC0CR 1201H 0: SCLK0↑ 0: Baud 1: Error Receive Parity...
  • Page 247 TMP92CM22 UART/Serial channel (2/2) Symbol Name Address Serial 1208H channel 1 SC1BUF (Prohibit R (Receiving)/W (Transmission) buffer RMW) Undefined register EVEN OERR PERR FERR SCLKS R (Clear 0 after reading) Serial Undefined channel 1 0: SCLK1↑ SC1CR 1209H 1: Error Receive Parity Parity...
  • Page 248 TMP92CM22 (9) I C bus/Serial channel (1/2) Symbol Name Address SCK0/ SCK2 SCK1 SWRMON 1240H (Prohibit Number of transfer bits Setting of the divide value “n” RMW) Acknowledge 000: 8 001: 1 010: 2 011: 3 000: 5 001: 6 010: 7 011: 8 mode...
  • Page 249 TMP92CM22 C bus/Serial channel (2/2) Symbol Name Address − I2SBI0 1244H C mode) (Prohibit Always IDLE2 write “0”. RMW) SBI0 0: Abort SBI0BR0 baud rate 1: Operate − − register 0 1244H (SIO mode) (Prohibit Always Always RMW) write “0”. write “0”.
  • Page 250 TMP92CM22 (10) AD converter (1/2) Symbol Name Address − − EOCF ADBF ITM0 REPEAT SCAN 0: Every Always Always Repeat Scan AD mode 1 time write “0”. write “0”. conversion conversion mode mode conversion ADMOD0 control 12B8H 1: Every end flag start 0: Single 0: Fixed...
  • Page 251 TMP92CM22 AD converter (2/2) Symbol Name Address ADR41 ADR40 ADR4RF AD result ADREG4L 12A8H register 4 Undefined ADR49 ADR48 ADR47 ADR46 ADR45 ADR44 ADR43 ADR42 AD result ADREG4H 12A9H register 4 high Undefined ADR51 ADR50 ADR5RF AD result ADREG5L 12AAH register 5 Undefined ADR59...
  • Page 252 TMP92CM22 (11) Watchdog timer Symbol Name Address − − WDTE WDTP1 WDTP0 I2WDT RESCR 1: Internally Select detecting time Always IDLE2 Always WDMOD mode 1300H connects control write “0”. write “0”. 00: 2 0: Stop register WDT out 01: 2 1: Enable 1: Operate to the...
  • Page 253 TMP92CM22 Port Section Equivalent Circuit Diagram ■ Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active “1” when the halt mode setting register is set to the STOP mode and the CPU executes the HALT instruction.
  • Page 254 TMP92CM22 ■ P70 ( ), P71 ( ), P72 ( ), P73, P74 (CLKOUT), P75 ( ), P80 ( ), P81 ( WRLL WRLU P82 ( ), and P83 ( Output data P-ch Output Stop N-ch ■ PA0, PA1, PA2, and PA7 Input Input data ■...
  • Page 255 TMP92CM22 ■ PF0 (TXD0) and PF3 (TXD1) Output data P-ch Open-drain N-ch output enable Stop Input data Input enable ■ PG0 (AN0), PG1 (AN1), PG2 (AN2), PG3 (AN3/ ), PG4 (AN4), PG5 (AN5), PG6 (AN6), ADTRG and PG7 (AN7) Analog input P-ch channel select Analog input...
  • Page 256 TMP92CM22 ■ X1 and X2 Clock Oscillator High-frequency N-ch P-ch oscillation enable ■ VREFH and VREFL VREFON P-ch VREFH String resistance VREFL ■ AM0 and AM1 Input Input data ■ Input Schmitt 2007-02-16 92CM22-254...
  • Page 257 TMP92CM22 Points to Note and Restrictions (1) Notation The notation for built-in I/O registers is as follows register symbol <Bit symbol>. Example: TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN. Read-modify-write instructions (RMW) An instruction in that the CPU reads data from memory and writes the data to the same memory location by using one instruction.
  • Page 258 TMP92CM22 (2) Points to note AM0 and AM1 pins This pin is connected to the VCC (Power supply level) or VSS (Ground level) pins. Do not alter the level when the pin is active. Reservation area of address area TMP92CM22 don’t include reservation area. Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator.

  • Page 259: Package Dimensions

    TMP92CM22 Package Dimensions P-LQFP100-144-0.50F Unit: mm 2007-02-16 92CM22-257...
  • Page 260 TMP92CM22 2007-02-16 92CM22-258...

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Tlcs-900/h1 series

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