Toshiba TLCS-900/H1 Series Manual page 408

3.17.4.5 NAND-Flash Interrupt Status Register (ND0FISR and ND1FISR)
Bits Mnemonic
−
7:1
0 RDY
Figure 3.17.6 NAND-Flash Interrupt Status Register (ND0FISR and ND1FISR)
3.17.4.6 NAND-Flash Interrupt Mask Register (ND0FIMR and ND1FIMR)
Bits Mnemonic
7 INTEN
−
6:1
0 MRDY
Figure 3.17.7 NAND-Flash Interrupt Mask Register (ND0FIMR and ND1FIMR)
Field Name
−
Reserved
Ready Ready (Default: 0)
When NDR/ B signal changes from low (BUSY) to High (
READY) and NDFIMR<MRDY> is "1", this bit is set to "1". By writing "1", this bit is
cleared to 0.
Read:
0: None
1: Change NDR/ B signal from BUSY to READY.
Write:
0: No change
1: Clear to "0"
INTEN
R/W
Field Name
Interrupt enable Interrupt enable (Default: 0)
When <INTEN> and <MRDY> are set "1" and NDFISR<RDY> becomes "1",
INTNDFC occurs.
0: Disable
1: Enable
−
Reserved
Mask RDY Mask RDY interrupt (Default: 0)
interrupt
This bit masks the NDFISR<RDY>. If <MRDY> is "1" and NDR/ B signal changes
from Low to High, NDFISR<RDY> is set to "1".
0: Disable to set NDFISR<RDY>
1: Enable to set NDFISR<RDY>
92CH21-406
7 6 5 4
Description
7 6 4
0
0
Description
TMP92CH21
3 2 1 0
RDY
3 2 1 0
MRDY
R/W
0
2009-06-19
: Type
: Default
: Type
: Default