Toshiba TLCS-900/H1 Series Manual page 349

3.14.3.5 Refresh Rate Setting
Frame cycle (refresh rate) is generated from setting of LSCC (LCDSCC<SCC7:0>)
and FP [9:0] (LCDCTL0<FP9, 8>, LCDFFP<FP7:0>). The LBCD terminal outputs one
pulse every cycle and the LFR normally outputs an inverted signal every cycle. But
when the DIVIDE FRAME function is used, the LFR signal changes to a special signal
for high quality display.
(1) Basic clock setting
controller. This generator can set details of the refresh rate for the LCDC.
f
BCD
FP: FP [9:0] setting value of FFP register
SCC: <SCC7:0> setting value of LSCC register
Example:
Value of setting to register is only integer, SCC = 17. The floating value is disregarded.
In this case, the refresh rate comes to 144.6 [Hz]
LCDSCC Bit symbol SCC7
(0287H)
Read/Write
Reset State
Function
* Data should be written from 1-hex to FFFF-hex in the above register. It cancannot operate if set
to "0".
* If the refresh rate is set too fast, it may not be in time with the display data. t
by SCC.
[s] = (1/f
t
LP
t is shown in 1-line (ROW) display time. 1-line data transmission must be completed
LP
during t
data transmission time.
This LSI has a special clock generator for basic source clock used in the LCD
This generator is made by dividing the system clock by 16 and an 8-bit counter.
The following shows the method of setting and calculation.
[Hz]: Frame rate (Refresh rate: Frequency of LBCD signal)
[Hz] = f [Hz] / ((SCC+1) × 16 × FP)
f
BCD SYS
[Hz] = 20MHz, 480COM (FP = 480), target refresh rate = 140Hz
f
SYS
140 [Hz] = 20000000 [Hz]/((SCC+1) × 16 × 480)
(SCC+1) = 20000000/(140 ×16 × 480) = 18.60
LCDC Source Clock Counter Register
7 6 5
SCC6 SCC5
0 0 0
[Hz]) × 16 × (SCC + 1)
SYS
cycle time. AboutRefer to "Data transmission and bus occupation" for details of
LP
92CH21-347
4 3
SCC4 SCC3
R/W
0 0
LCDC Source Clock Counter bit7 to bit0
TMP92CH21
2 1
SCC2 SCC1 SCC0
0 0 0
time is determined
LP
2009-06-19
0