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L C O - I I I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Display
C ...
Input
r----~
I
I
I
2
3
-;:;..----0
An
I
I
:22:
OAo2
I
I
To
A,B
Aegister: 21
-1-----0
Rol
: 2'
-1-----0
Aoo
I
I
L. ___
.J
Output
ROMpetternOrd.tI
r---------1
(
Sede' segment
0 ... 101
Letch clock
ICL,I
Shift clock
ICL,I
Alrern.ting
signellM)
OutPUt
C ... (
::
2'
2'
I
I
L_+ ____________
,.J _
~~.'~ ~:.~o
:
I
function.
:
2' 21 2* 2' :
Gate for IJICcMnging
thl
output
regilter
,ignl'
and
the display d ... Ii . . ' Iccording
to the contlnt of
R.
a
Output
ROM pettern or dltl
L ______
~
To A
.nd
B regilter
Ret ="1"
ditil/Oregi.ter
.ignal
R41I
="0"
Dllpllyditl
,ign.1
R"
),,' -
R"
RIO
R"
Input
U~(~' i~' ~~
}M_
(~U
Set all
bits
to "'"
by r ...
t
'unction.
Figure 10 Data I/O Block Diagram
When expansion of segment signal for liquid crystal display
is designated by a program (Register
R.2
="0"), Rl is used as
a display data output terminal. This prohibits Rl to be used as
an I/O common channel by users (Refer to Figure 10, Rl
channel).
If LRA or LRB instruction is executed at the time, data is
transferred to data I/O register, but the content of data I/O
register is not output from Rl. If LAR or LBR instruction is
executed, display data is inputted to accumulator (A register)
or B register.
Data is transferred from the accumulator (A register) and B
/One Instruction Cvcle
I i i
i
~
LRA, LRS
r
--I
A Output
I
n.truc~lon
l
n
instruction
~nHN~iO"[
LAA, LBR[
Inltructlon
-
An
X
Pattern Ganera-
tion Instruction
A2,A3
register to data I/O registers Rl, R2, and R3 through the bus
line. In addition, ROM bit patterns can be transferred to R2
and R3 by pattern generation instructions.
4-bit data can be inputted to the accumulator (A register)
and B register from RO, Rl and R2 channels by input instruc-
tions. However, in the case of I/O common channels R2 and
R3, since data I/O register outputs are connected to terminals,
inputs are done to wired logic of register output and terminal
input information. For this reason, to input terminal input
signal, registers must be set to a state that would not affect
the terminal input.
(second cycle)
An Input Instruction
""'"-
Rn Sampling Pulse
Figure 11 Data I/O Timing Chart
154
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