Timer 3 Irq Clear (T3Ic); Timer 4 Irq Clear (T4Ic); Watchdog Timer; Wdt Control Status Register (Wcsr) - GE V7768 Hardware Reference Manual

Intel core duo processor vme single board computer
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3.4 Watchdog Timer

"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (TCSR1). This register is write only and the data written is irrelevant.

3.3.11 Timer 3 IRQ Clear (T3IC)

The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by
Timer 3. Writing to this register, located at offset 0x38 from the address in BAR2,
causes the interrupt from Timer 3 to be cleared. This can also be done by writing a
"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (TCSR1). This register is write only and the data written is irrelevant.

3.3.12 Timer 4 IRQ Clear (T4IC)

The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by
Timer 4. Writing to this register, located at offset 0x3C from the address in BAR2,
causes the interrupt from Timer 4 to be cleared. This can also be done by writing a
"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (TCSR1). This register is write only and the data written is irrelevant.
The V7768/V7769 provide a programmable Watchdog Timer (WDT) which can be
used to reset the system if software integrity fails.

3.4.1 WDT Control Status Register (WCSR)

The WDT is controlled and monitored by the WDT Control Status Register
(WCSR) which is located at offset 0x08 from the address in BAR2. The mapping of
the bits in this register is shown in Table 3-11.

Table 3-11 WCSR Bit Mapping

Field
Bits
SERR/RST Select
WCSR[16]
WDT Timeout Select
WCSR[10..8]
WDT Enable
WCSR[0]
All of these bits default to "0" after system reset. All other bits are reserved.
The "WDT Timeout Select" field is used to select the timeout value of the WDT as
shown in Table 3-12.

Table 3-12 Selecting Timeout Value of the WDT

Timeout
135 s
33.6 s
2.1 s
524 ms
262 ms
131 ms
32.768 ms
2.048 ms
WCSR[10]
WCSR[9]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Read or Write
R/W
R/W
R/W
WCSR[8]
0
1
0
1
0
1
0
1
Embedded PC/RTOS Features 51
.

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