Timer 3 Load Count Register (Tmrlcr3); Timer 4 Load Count Register (Tmrlcr4); Timer 1 & 2 Current Count Register (Tmrccr12); Table 3-5 Tmrlcr12 Bit Mapping - GE V7768 Hardware Reference Manual

Table 3-5 TMRLCR12 Bit Mapping

Field Bits
Timer 2 Load Count TMRLCR12[31..16]
Timer 1 Load Count TMRLCR12[15..0]
When either of these fields are written (either by a single 32-bit write or separate
16-bit writes), the respective timer is loaded with the written value on the next
rising edge of the timer clock, regardless of whether the timer is enabled or
disabled. The value stored in this register is also automatically reloaded on
terminal count (or timeout) of the timer.

3.3.4 Timer 3 Load Count Register (TMRLCR3)

Timer 3 is 32-bits wide and obtains its load count from the Timer 3 Load Count
Register (TMRLCR3), located at offset 0x14 from the address in BAR2. The
mapping of bits in this register is shown in Table 3-6.

Table 3-6 TMRLCR3 Bit Mapping

Field Bits
Timer 3 Load Count TMRLCR3[31..0]
When this field is written, Timer 3 is loaded with the written value on the next
rising edge of the timer clock, regardless of whether the timer is enabled or
disabled. The value stored in this register is also automatically reloaded on
terminal count (or timeout) of the timer.

3.3.5 Timer 4 Load Count Register (TMRLCR4)

Timer 4 is 32-bits wide and obtains its load count from the Timer 4 Load Count
Register (TMRLCR4), located at offset 0x18 from the address in BAR2. The
mapping of bits in this register is shown in Table 3-7.

Table 3-7 TMRLCR4 Bit Mapping

Field Bits
Timer 4 Load Count TMRLCR4[31..0]
When this field is written, Timer 4 is loaded with the written value on the next
rising edge of the timer clock, regardless of whether the timer is enabled or
disabled. The value stored in this register is also automatically reloaded on
terminal count (or timeout) of the timer.
3.3.6 Timer 1 & 2 Current Count Register (TMRCCR12)
The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count
Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The
mapping of bits in this register is shown in Table 3-8.
Read or Write
R/W
R/W
Read or Write
R/W
Read or Write
R/W
Embedded PC/RTOS Features 49
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