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Functional Description
Except where noted, Harrier A and Harrier B have the same default power-up setting.
4.6.3
Debug Connector
One 190-pin Mictor connector with center row of power and ground pins is used to provide
access to the processor bus and some miscellaneous signals. When the CPCI-6020 is
populated with an MPC7410 processor this bus is not tolerant of +3.3 V or +5 V signals. Boards
attached to this connector should not drive or pull signals up to intolerable levels.
4.6.4
PPC Bus Arbitration
The Harrier ASIC contains arbiters for the PPC Bus and the PCI Bus. The Harrier A PPC arbiter
is used to arbitrate between the processor, the Harrier A and the Harrier B PPC Bus masters
for ownership of the PPC Bus. The processor is connected to the Harrier A arbiter
CPU0_REQ/CPU0_GNT signal pair (XARB3/XARB0) and Harrier B is connected to the Harrier
A arbiter EXTL_REQ/EXTL_GNT signal pair (XARB5/XARB2). For more information on PPC
Bus arbitration refer to the CPCI-6020 CompactPCI Single Board Computer Programmer's
Reference Guide and the Harrier Application Specific Integrated Circuit (ASIC) Programmer's
Reference Guide.
4.7
ECC Memory Bus Resources
The CPCI-6020 supports 2 GB of memory via four RAM500 mezzanine modules populated in
the two memory connectors J7 and J28. There is no onboard memory. The ECC protected
memory mezzanines are distributed as separate sets, one attached to each Harrier. The CPCI-
6020 supports a total of 1 GB using currently available 256 MB SDRAMs, (evenly divided
between the two Harriers) and supports 2 GB when 512 MB SDRAMs become available.
4.7.1
Harrier A Memory Bus
Harrier A memory bus is routed to a connector on which a RAM500 mezzanine may be
mounted. The RAM500 mezzanine is capable of stacking so a total of two mezzanines may be
attached to the Harrier A memory bus. The mezzanines appear as Banks C and E to the Harrier.
Each mezzanine has a storage capacity of 256 MB of ECC protected memory using available
256 megabit SDRAMs, and a capacity of 512 MB when 512 megabit SDRAMs are available.
2
The I
C SPD serial ROMs on these mezzanines are connected to Harrier A's I
90
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Debug Connector
2
C port 0.
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