Ppg Output Operation - NEC 78K0 Series User Manual

7.4.6 PPG output operation

A square wave having a pulse width set in advance by CR01n is output from the TO0n pin as a PPG
(Programmable Pulse Generator) signal during a cycle set by CR00n when bits 3 and 2 (TMC0n3 and TMC0n2) of 16-
bit timer mode control register 0n (TMC0n) are set to 11 (clear & start upon a match between TM0n and CR00n).
The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
• Pulse cycle = (Set value of CR00n + 1) × Count clock cycle
• Duty = (Set value of CR01n + 1) / (Set value of CR00n + 1)
Caution To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting CR01n during
TM0n operation.
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
Count clock
Operable bits
TMC0n3, TMC0n2
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
222
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-45. Block Diagram of PPG Output Operation
Clear
Timer counter
(TM0n)
Compare register
Match signal
Compare register
(CR01n)
Preliminary User's Manual U17260EJ3V1UD
Match signal
Output
(CR00n)
controller
Interrupt signal
(INTTM00n)
TO0n pin
Interrupt signal
(INTTM01n)