Texas Instruments TMS320F28004x Technical Reference Manual page 1980

Registers
Table 23-10. PMBSC Register Field Descriptions (continued)
Bit Field
18-16 TX_COUNT
15 PEC_ENA
14-8 SLAVE_MASK
7 MAN_SLAVE_ACK
6-0 SLAVE_ADDR
1980
Power Management Bus Module (PMBus)
Type Reset Description
R/W 0h
0 = No bytes valid
1 = One byte valid, Byte #0 (Bits 7:0 of Transmit Data Register)
2 = Two bytes valid, Bytes #0 and #1 (Bits 15:0 of Transmit Data
Register)
3 = Three bytes valid, Bytes #0-2 (Bits 23:0 of Transmit Data
Register)
4 = Four bytes valid, Bytes #0-3 (Bits 31:0 of Transmit Data
Register)
R/W 0h
0 = PEC processing disabled
1 = PEC processing enabled
R/W 7Fh
Used in address detection, the slave mask enables
acknowledgement
of multiple device addresses by the slave. Writing a '0' to a bit within
the slave mask enables the
corresponding bit in the slave address to be either '1' or '0' and still
allow for a match. Writing a '0'
to all bits in the mask enables the PMBus Interface to acknowledge
any device address. Upon
power-up, the slave mask defaults to 7Fh, indicating the slave will
only acknowledge the address
programmed into the Slave Address (Bits 6-0).
R/W 0h
0 = Slave automatically acknowledges device address specified in
SLAVE_ADDR, Bits 6:0
1 = Enables the Manual Slave Address Acknowledgement Mode.
Firmware is required to
read received address and acknowledge on every message
Note:
When bit 31 (I2C_mode) of PMBCTRL register is set it is
recommended to use manual acknowledging of slave address only
(MAN_SLAVE_ACK =1).
R/W 7Ch
Configures the current device address of the slave. Used in
automatic slave address acknowledge mode (default mode).
The PMBus Interface will compare the received device address with
the value stored in the Slave Address bits and the mask
configured in the Slave Mask bits. If matching, the slave will
acknowledge the device address.
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SPRUI33 – November 4 2015 – Revised January 2017
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