Time-Base Counter Synchronization Scheme - Texas Instruments TMS320F28004x Technical Reference Manual

ePWM Submodules
EXTSYNCIN1
EXTSYNCIN2
EPWM1
EPWM2
EPWM4
EPWM3
EPWM5
SYNCSEL.EPWM4SYNCIN
EPWM6
SYNCSEL.EPWM7SYNCIN
SYNCSEL.ECAP1SYNCIN
NOTE: See the data manual for the number of ePWM and eCAP modules available on your specific
device.
Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN]
bit is set, then the time-base counter (TBCTR) of the ePWM module will be automatically loaded with the
phase register (TBPHS) contents when one of the following conditions occur:
• EPWMxSYNCI: Synchronization Input Pulse:
The value of the phase register is loaded into the counter register when an input synchronization pulse
is detected (TBPHS → TBCTR). This operation occurs on the next valid time-base clock (TBCLK)
edge.
The delay from internal master module to slave modules is given by:
– if ( TBCLK = EPWMCLK): 2 x EPWMCLK
– if ( TBCLK != EPWMCLK):1 TBCLK
• Software Forced Synchronization Pulse:
Writing a 1 to the TBCTL[SWFSYNC] control bit invokes a software forced synchronization. This pulse
is ORed with the synchronization input signal, and therefore has the same effect as a pulse on
EPWMxSYNCI.
1496
Enhanced Pulse Width Modulator (ePWM)
Figure 15-7. Time-Base Counter Synchronization Scheme
EPWM7
EPWM8
ECAP1
ECAP2
ECAP3
SYNCSEL.ECAP4SYNCIN
Copyright © 2015–2017, Texas Instruments Incorporated
ECAP4
ECAP5
ECAP6
ECAP7
SYNCSEL.EHRCAP1SYNCIN
SPRUI33 – November 4 2015 – Revised January 2017
www.ti.com
EPWM1SYNCOUT
EXTSYNCOUT
EPWM4SYNCOUT
Pulse-Stretched
(8 PLLSYSCLK
Cycles)
EPWM7SYNCOUT
SYNCSEL.SYNCOUT
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