Sharp ER-A770 Manual page 43

Pin Signal
Symbol In/Out
No. name
35 CS1 S A1
36 CLK/TRG3 S TM1
37 CLK/TRG2 S TM0
38 NC NC
39 NC NC
40 CLK/TRG1 S INTS
41 CLK/TRG0 VCC
42 NC NC
43 +5V VCC
44 NC NC
2-6. PD71037
DMA CONTROLLER
The PD71037 is a direct memory access controller (DMAC) for the
micro processor system. It provides higher processing speed and
lower power consumption in comparison with those in conventional
use. Each of the four built-in DMA channels has 64-KB addresses
and the function of counting the number of bytes of transferred data,
and can transfer data from I/O to memory and from memory to mem-
ory as well.
1) FEATURES
The clock speed is 10 MHz, twice that of the PD8237A-5 (clock
speed of 5 MHz).
Each of the four DMA channels can be operated independently.
Each channel can be self-initialized.
Data is transferrable from memory to memory.
Data in memory can independently initialized by block.
High speed data transfer:
3.2 MB/sec. (clock seed of 10 MHz, normal transfer mode)
5.0 MB/sec. (clock speed of 10 MHz, compression transfer mode)
The number of DMA channels can directly be expanded
(Expansion mode).
END input when data transfer is finished.
Software DMA request available.
CMOS
Low power consumption0
2) Pin configuration
READY 1
HLDAK 2
ASTB 3
AEN 4
HLDRQ 5
µPD71037GB-3B4
NC 6
CS 7
CLK 8
RESET 9
DMAAK2 1 0
DMAAK3 1 1
Function
In Channelselect signal
In External clock / timer signal
In External clock / timer signal
— NC
— NC
In External clock / timer signal
In +5V
— NC
— +5V
— NC
33 A3
32 A2
31 A1
30 A0
29 VDD
28 NC
27 A8/D0
26 A9/D1
25 A10/D2
24 A11/D3
23 A12/D4
3) Pin configuration
Pin Signal
Symbol
No. name
1 READY READY
2 HLDAK HLDAK
3 ASTB S ASTB
4 AEN S AEN
5 HLDRQ HLDRQ
6 NC NC
7 CS CS
8 CLK CLK
9 RESET SRNRESET
10 DMAAK2 S DACK2
11 DMAAK3 S DACK3
12 DMARQ3 S DRQ3
13 DMARQ2 S DRQ2
14 DMARQ1 S DRQ1
15 DMARQ0 S DRQ0
16 GND GND
17 NC NC
18 A15/D7 S D7
19 A14/D6 S D6
20 A13/D5 S D5
21 DMAAK1 S DACK1
22 DMAAK0 S DACK0
23 A12/D4 S D4
24 A11/D3 S D3
25 A10/D2 S D2
26 A9/D1 S D1
27 A8/D0 S D0
28 NC NC
29 VDD VCC
30 A0 S A0
31 A1 S A1
32 A2 S A2
33 A3 S A3
34 NC NC
35 END / TC TC
36 A4 S A4
37 A5 S A5
38 A6 S A6
39 A7 S A7
40 IORD S IOR
41 IOWR S IOW
42 MRD S MRD
43 MWR NC
44 NC NC
In/
Function
Out
In Ready signal
In Hold acknowledge signal
Out Address strobe signal
Out Address enable signal
Out Hold request signal
— NC
In Chip select signal
In Clock
In Reset signal
Out DMA acknowlidge signal
Out DMA acknowlidge signal
In DMA request signal
In DMA request signal
In DMA request signal
In DMA request signal
— GND
— NC
In/Out Data bus
In/Out Data bus
In/Out Data bus
Out DMA acknowlidge signal
Out DMA acknowlidge signal
In/Out Data bus
In/Out Data bus
In/Out Data bus
In/Out Data bus
In/Out Data bus
— NC
— +5V
In Address bus
In Address bus
In Address bus
In Address bus
— NC
In/Out End / Terminal cut signal
In Address bus
In Address bus
In Address bus
In Address bus
In/Out I/O read signal
In/Out I/O write signal
Out Memory read signal
— NC
— NC