Sharp ER-A770 Manual page 40

Pin
Name ER-A770
NO.
142 VCC VCC
143 GND GND
144 /CSD VCC
145 TRNDTD NC
146 /DTRD NC
147 /RTSD NC
148 RCVDTD GND
149 /CTSD GND
150 /DSRD GND
151 TRNRDYD NC
152 RCVRDYD NC
153 TRNEMPD NC
154 SYCBKD NC
155 /WIN /WRH
156 /RIN /RDH
157 RSLCT0 AH0
158 RSLCT1 AH1
159 RST RES USART
160 MCLK CLK USART
I TTL input
ID TTL input with pull down
IS TTL Schmidt input
ISU TTL Schmidt input with pull up
IO TTL I/O
3S 3-state Buffer (6mA)
ON6 Open drain (6mA)
2-4. Z80 CPU
1) Features
The extensive instruction set contains 158 instructions, including the
8080A instruction set as a subset.
NMOS version for low cost high performance solutions, CMOS
version for high performance low power designs.
Z0840006 - 6.17 MHz
CMOS Z84C0006 - DC to 6.17 MHz, Z84C008 - DC to 8 MHz,
Z84C0010 - DC to 10 MHz, Z84C0020 - DC - 20 MHz
6 MHz version can be operated at 6.144 MHz clock.
The Z80 microprocessors and associated family of peripherals can
be linked by a vectored interrupt system. This system can be
daisy-chained to allow implementation of a priority interrupt
scheme.
Duplicate set of both general-purpose and flag registers.
Two sixteen-bit index registers.
Three modes of maskable interrupts:
Mode 0 — 8080A similar;
Mode 1 — Non-Z80 environment, location 38H;
Mode 2 — Z80 family peripherals, vectored interrupts.
On-chip dynamic memory refresh counter.
I/O Description
+5V
GND
IS +5V
O NC
O NC
O NC
IS GND
IS GND
IS GND
O NC
O NC
O NC
IO NC
I Write signal
I Read signal
I Address bus
I Address bus
IS Reset signal
I Clock (4.91MHz)
M1
MREQ
SYSTEM IORQ
CONTROL
RD
WR
RFSH
HALT
WAIT
Z8400
CPU
Z80 CPU
CONTROL
INT
NMI
RESET
CPU
BUSREQ
BUS
BUSACK
CONTROL
CLK
+5V
GND
Figure 1. Pin functions
2) Pin configuration
44
1
CLK
D4
D3
D5
D6
Z80 CPU
+5V
D2
D7
D0
D1
NC
11
12
44Pin Quad Flat Pack (QFP), Pin Assignments
(Only available for 84C00)
A0
A1
A2
A3
A4
A5
A6
ADDRESS
A7
BUS
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
DATA
BUS
D4
D5
D6
D7
34
33
NC
A5
A4
A3
A2
A1
A0
GND
RFSH
M1
RESET
23
22