Epson 0C88832 Technical Manual page 69

Address Bit Name
00FF23 D7 EPT1 Programmable timer 1 interrupt enable register
D6 EPT0
Programmable timer 0 interrupt enable register
D5 EK1 K10 interrupt enable register
D4 EK0H
K04–K07 interrupt enable register
D3 EK0L
K00–K03 interrupt enable register
D2 ESERR
Serial I/F (error) interrupt enable register
D1 ESREC
Serial I/F (receiving) interrupt enable register
D0 ESTRA
Serial I/F (transmitting) interrupt enable register
00FF25 D7 FPT1
Programmable timer 1 interrupt factor flag
D6 FPT0
Programmable timer 0 interrupt factor flag
D5 FK1
K10 interrupt factor flag
D4 FK0H K04–K07 interrupt factor flag
D3 FK0L
K00–K03 interrupt factor flag
D2 FSERR Serial I/F (error) interrupt factor flag
D1 FSREC
Serial I/F (receiving) interrupt factor flag
D0 FSTRA Serial I/F (transmitting) interrupt factor flag
ESIF: 00FF48H•D0
Sets the serial interface terminals (P10–P13).
When "1" is written: Serial input/output terminal
When "0" is written: I/O port terminal
Reading:
The ESIF is the serial interface enable register and
P10–P13 terminals become serial input/output
terminals (SIN, SOUT, SCLK, SRDY) when "1" is
written, and they become I/O port terminals when
"0" is written.
Also, see Table 5.7.3.2 for the terminal settings
according to the transfer modes.
At initial reset, ESIF is set to "0" (I/O port).
SMD0, SMD1: 00FF48H•D1, D2
Set the transfer modes according to Table 5.7.9.2.
Table 5.7.9.2 Transfer mode settings
SMD1 SMD0
1 1 Asynchronous system 8-bit
1 0 Asynchronous system 7-bit
0 1 Clock synchronous system slave
0 0 Clock synchronous system master
SMD0 and SMD1 can also read out.
At initial reset, this register is set to "0" (clock
synchronous master mode).
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
Table 5.7.9.1(b) Serial interface control bits
Function
Valid
Mode
1
Interrupt Interrupt
enable disable
(R)
Interrupt No interrupt
factor is factor is
generated generated
(W)
Reset No operation
SCS0, SCS1: 00FF48H•D3, D4
Select the clock source according to Table 5.7.9.3.
Table 5.7.9.3 Clock source selection
SCS1 SCS0
1
1
0
0
SCS0 and SCS1 can also be read out.
In the clock synchronous slave mode, setting of this
register is invalid.
At initial reset, this register is set to "0" (f
EPR: 00FF48H•D6
Selects the parity function.
When "1" is written: With parity
When "0" is written: Non parity
Reading:
Selects whether or not to check parity of the
received data and to add a parity bit to the trans-
mitting data. When "1" is written to EPR, the most
significant bit of the received data is considered to
be the parity bit and a parity check is executed. A
parity bit is added to the transmitting data. When
"0" is written, neither checking is done nor is a
parity bit added.
Parity is valid only in asynchronous mode and the
EPR setting becomes invalid in the clock synchro-
nous mode.
At initial reset, EPR is set to "0" (non parity).
EPSON
0 SR R/W Comment
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
(R)
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
(W)
0 R/W
0 R/W
Clock source
1 Programmable timer
0 f / 4
OSC3
1 f / 8
OSC3
0 f / 16
OSC3
OSC3
Valid
/16).
63