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7 ELECTRICAL CHARACTERISTICS
• Asynchronous system (All operating mode)
Condition: V
= 1.8 to 5.5 V, V
DD
Item
Start bit detection error time
Erroneous start bit detection range time
Note) 1
Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
2
Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started.
When a HIGH level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit.
(Time as far as AC is excluded.)
SCLK OUT
SOUT
SIN
SCLK IN
SOUT
SIN
SIN
Sampling
clock
Erroneous
start bit
detection signal
130
= 0 V, Ta = -40 to 85°C
SS
Symbol
t
sa
1
t
sa
2
V
OH
V
OL
t
smd
V
OH
V
OL
t
sms
V
IH1
V
IL1
V
IH1
V
IL1
t
ssd
V
OH
V
OL
t
sss
V
IH1
V
IL1
Start bit
t
sa
1
t
sa
2
EPSON
Min.
Typ.
0
t
9
/16
t
smh
t
ssh
t
E0C88832/88862 TECHNICAL MANUAL
Max.
Unit
Note
t
/16
S
t
10
/16
S
Stop bit
1
2
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