Epson 0C88832 Technical Manual page 25

Address Bit Name
00FF11 D7 –
–
D6 DSPAR
LCD display memory area selection
D5 LCDC1
LCD display control
D4 LCDC0
D3 LC3
LCD contrast adjustment
D2 LC2
D1 LC1
D0 LC0
00FF12 D7 –
–
D6 –
–
D5 SVDSP
SVD auto-sampling control
D4 SVDON
SVD continuous sampling control/status
D3 SVD3
SVD detection level
D2 SVD2
D1 SVD1
D0 SVD0
00FF20 D7 PK01
K00–K07 interrupt priority register
D6 PK00
D5 PSIF1
Serial interface interrupt priority register
D4 PSIF0
D3 PSW1
Stopwatch timer interrupt priority register
D2 PSW0
D1 PTM1
Clock timer interrupt priority register
D0 PTM0
00FF21 D7 – –
D6 – –
D5 – –
D4 – –
D3 PPT1
Programmable timer interrupt priority register
D2 PPT0
D1 PK11
K10 interrupt priority register
D0 PK10
00FF22 D7 –
–
D6 ESW100
Stopwatch timer 100 Hz interrupt enable register
D5 ESW10
Stopwatch timer 10 Hz interrupt enable register
D4 ESW1
Stopwatch timer 1 Hz interrupt enable register
D3 ETM32
Clock timer 32 Hz interrupt enable register
D2 ETM8
Clock timer 8 Hz interrupt enable register
D1 ETM2
Clock timer 2 Hz interrupt enable register
D0 ETM1
Clock timer 1 Hz interrupt enable register
*1 After initial reset, this status is set "1" until conclusion of hardware first sampling.
*2 Initial values are set according to the supply voltage detected at first sampling by hardware.
Until conclusion of first sampling, SVD0–SVD3 data are undefined.
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(b) I/O Memory map (00FF11H–00FF22H)
Function
LCDC1 LCDC0 LCD display
1 1 All LCDs lit
1 0 All LCDs out
0 1 Normal display
0 0 Drive off
LC3 LC2 LC1 LC0
1 1 1 1
1 1 1 0
: : : :
0 0 0 0
SVD3 SVD2 SVD1 SVD0
1 1 1 1
1 1 1 0
: : : :
0 0 0 0
1
–
Display area 1
Contrast
Dark
:
:
Light
–
–
On
R
Busy
W
On
Detection level
Level 15
Level 14
:
Level 0
PK01 PK00
PSIF1 PSIF0
PSW1 PSW0
PTM1 PTM0
1 1
1 0
0 1
0 0
–
–
–
–
PPT1 PPT0
PK11 PK10
1 1
1 0
0 1
0 0
–
Interrupt
enable
EPSON
0 SR R/W
–
– "0" when being read
0 R/W
Display area 0
0 R/W
These bits are reset
to (0, 0) when
0 R/W
SLP instruction
is executed.
0 R/W
0 R/W
0 R/W
0 R/W
–
– Constantry "0" when
–
– being read
0 R/W
Off These registers are
reset to "0" when
→
R/W
Ready 1 0*1 SLP instruction
0
Off is executed.
X R
*2
X R
X R
X R
0 R/W
0 R/W
0 R/W
Priority
0 R/W
level
Level 3
0 R/W
Level 2
0 R/W
Level 1
Level 0
0 R/W
0 R/W
–
–
–
– Constantly "0" when
–
– being read
–
–
Priority
0 R/W
level
0 R/W
Level 3
Level 2
0 R/W
Level 1
0 R/W
Level 0
–
– "0" when being read
0 R/W
0 R/W
0 R/W
Interrupt
0 R/W
disable
0 R/W
0 R/W
0 R/W
Comment
19