Ltdc Shadow Reload Configuration Register (Ltdc_Srcr) - STMicroelectronics STM32F405 Reference Manual

RM0090
16.7.6

LTDC Shadow Reload Configuration Register (LTDC_SRCR)

This register allows to reload either immediately or during the vertical blanking period, the
shadow registers values to the active registers. The shadow registers are all Layer1 and
Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:2 Reserved, must be kept at reset value
Bit 1 VBR: Vertical Blanking Reload
Bit 0 IMR: Immediate Reload
Note: The shadow registers read back the active values. Until the reload has been done, the 'old'
value will be read.
16.7.7 LTDC Background Color Configuration Register (LTDC_BCCR)
This register defines the background color (RGB888).
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
BCGREEN[7:0]
27 26 25
11 10 9
Reserved
This bit is set by software and cleared only by hardware after reload. (it cannot be cleared
through register write once it is set)
0: No effect
1: The shadow registers are reloaded during the vertical blanking period (at the
beginning of the first line after the Active Display Area)
This bit is set by software and cleared only by hardware after reload.
0: No effect
1: The shadow registers are reloaded immediately
27 26 25
Reserved
11 10 9
rw
DocID018909 Rev 11
24 23 22 21
Reserved
8 7 6 5
24 23 22 21
rw rw rw
8 7 6 5
rw rw rw
LCD-TFT Controller (LTDC)
20 19 18 17
4 3 2 1
VBR
rw
20 19 18 17
BCRED[7:0]
rw rw rw rw
4 3 2 1
BCBLUE[7:0]
rw rw rw rw
16
0
IMR
rw
16
rw
0
rw
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