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STMicroelectronics STM32F405 Reference Manual

Advanced arm-based 32-bit mcus

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RM0090

Reference manual

STM32F405/415, STM32F407/417, STM32F427/437 and

®

STM32F429/439 advanced ARM

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and

STM32F43xxx microcontroller memory and peripherals.

The STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx constitute

a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

datasheets.

®

®

For information on the ARM Cortex

-M4 with FPU core, please refer to the Cortex

-M4 with

FPU Technical Reference Manual.

Related documents

Available from STMicroelectronics web site (http://www.st.com):

• STM32F40x and STM32F41x datasheets

• STM32F42x and STM32F43x datasheets

®

• For information on the ARM Cortex

-M4 with FPU, refer to the STM32F3xx/F4xxx

®

Cortex

-M4 with FPU programming manual (PM0214).

October 2015

DocID018909 Rev 11

1/1731

1

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Summary of Contents for STMicroelectronics STM32F405

Page 1 -M4 with FPU core, please refer to the Cortex -M4 with FPU Technical Reference Manual. Related documents Available from STMicroelectronics web site (http://www.st.com): • STM32F40x and STM32F41x datasheets • STM32F42x and STM32F43x datasheets ® • For information on the ARM Cortex -M4 with FPU, refer to the STM32F3xx/F4xxx ®...
Page 2: Table Of Contents
Contents RM0090 Contents Documentation conventions ....... . . 57 List of abbreviations for registers ....... 57 Glossary .
Page 3 RM0090 Contents 3.5.2 Adaptive real-time memory accelerator (ART Accelerator™) ..82 Erase and program operations ....... . . 84 3.6.1 Unlocking the Flash control register .
Page 4 Contents RM0090 CRC introduction ......... . .113 CRC main features .
Page 5 RM0090 Contents PWR register map ......... 149 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) .
Page 6 Contents RM0090 6.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) ........192 6.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR) .
Page 7 RM0090 Contents 7.3.4 RCC clock interrupt register (RCC_CIR) ..... . . 230 7.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) ..233 7.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .
Page 8 Contents RM0090 8.3.7 I/O alternate function input/output ......277 8.3.8 External interrupt/wakeup lines ......277 8.3.9 Input configuration .
Page 9 RM0090 Contents 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) ........295 9.2.7 Compensation cell control register (SYSCFG_CMPCR) .
Page 10 Contents RM0090 10.3.16 Summary of the possible DMA configurations ....324 10.3.17 Stream configuration procedure ......324 10.3.18 Error management .
Page 11 RM0090 Contents 11.4 DMA2D interrupts ......... . 353 11.5 DMA2D registers .
Page 12 Contents RM0090 12.3 EXTI registers ..........386 12.3.1 Interrupt mask register (EXTI_IMR) .
Page 13 RM0090 Contents 13.9.5 Combined regular/injected simultaneous mode ....413 13.9.6 Combined regular simultaneous + alternate trigger mode ..414 13.10 Temperature sensor .
Page 14 Contents RM0090 14.3.8 Noise generation ......... 440 14.3.9 Triangle-wave generation .
Page 15 RM0090 Contents Digital camera interface (DCMI) ......457 15.1 DCMI introduction ......... . 457 15.2 DCMI main features .
Page 16 Contents RM0090 16.3 LTDC functional description ........481 16.3.1 LTDC block diagram .
Page 17 RM0090 Contents 16.7.22 LTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR) (where x=1..2) ......... . . 506 16.7.23 LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2) .
Page 18 Contents RM0090 17.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) ... 558 17.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) ..560 17.4.5 TIM1&TIM8 status register (TIMx_SR) ......562 17.4.6 TIM1&TIM8 event generation register (TIMx_EGR) .
Page 19 RM0090 Contents 18.3.14 Timers and external trigger synchronization ....609 18.3.15 Timer synchronization ........612 18.3.16 Debug mode .
Page 20 Contents RM0090 19.3.6 PWM input mode (only for TIM9/12) ......653 19.3.7 Forced output mode ........654 19.3.8 Output compare mode .
Page 21 RM0090 Contents Basic timers (TIM6&TIM7) ........688 20.1 TIM6&TIM7 introduction .
Page 22 Contents RM0090 22.3 WWDG functional description ....... . 704 22.4 How to program the watchdog timeout .
Page 23 RM0090 Contents 23.6.13 CRYP register map ........754 Random number generator (RNG) .
Page 24 Contents RM0090 Real-time clock (RTC) ........789 26.1 Introduction .
Page 25 RM0090 Contents 26.6.14 RTC time stamp date register (RTC_TSDR) ....819 26.6.15 RTC timestamp sub second register (RTC_TSSSR) ....820 26.6.16 RTC calibration register (RTC_CALR) .
Page 26 Contents RM0090 Serial peripheral interface (SPI) ......865 28.1 SPI introduction ......... . . 865 28.2 SPI and I S main features .
Page 27 RM0090 Contents 28.5.8 SPI_I S configuration register (SPI_I2SCFGR) ....915 28.5.9 SPI_I S prescaler register (SPI_I2SPR) ..... . . 916 28.5.10 SPI register map .
Page 28 Contents RM0090 29.17 SAI registers ..........943 29.17.1 SAI xConfiguration register 1 (SAI_xCR1) where x is A or B .
Page 29 RM0090 Contents 30.6.5 Control register 2 (USART_CR2) ......1005 30.6.6 Control register 3 (USART_CR3) ......1006 30.6.7 Guard time and prescaler register (USART_GTPR) .
Page 30 Contents RM0090 31.6.1 SDIO I/O read wait operation by SDIO_D2 signaling ... . 1050 31.6.2 SDIO read wait operation by stopping SDIO_CK ....1050 31.6.3 SDIO suspend/resume operation .
Page 31 RM0090 Contents 32.4 bxCAN operating modes ........1071 32.4.1 Initialization mode .
Page 32 Contents RM0090 33.4.3 Reduced media-independent interface: RMII ....1123 33.4.4 MII/RMII selection ........1124 33.5 Ethernet functional description: MAC 802.3 .
Page 33 RM0090 Contents 34.3 OTG_FS functional description ......1235 34.3.1 OTG full-speed core ........1236 34.3.2 Full-speed OTG PHY .
Page 34 Contents RM0090 34.16.2 OTG_FS global registers ........1262 34.16.3 Host-mode registers .
Page 35 RM0090 Contents 35.6.3 Host channels ......... . 1380 35.6.4 Host scheduler .
Page 36 Contents RM0090 36.4.1 NOR/PSRAM address mapping ......1533 36.4.2 NAND/PC Card address mapping ......1534 36.5 NOR Flash/PSRAM controller .
Page 37 RM0090 Contents 37.6 NAND Flash/PC Card controller ......1634 37.6.1 External memory interface signals ......1635 37.6.2 NAND Flash / PC Card supported memories and transactions .
Page 38 Contents RM0090 38.8.1 SW protocol introduction ........1680 38.8.2 SW protocol sequence .
Page 39 RM0090 Contents 38.17.10 Example of configuration ........1700 38.18 DBG register map .
Page 40 List of tables RM0090 List of tables Table 1. STM32F4xx register boundary addresses ........64 Table 2.
Page 41 RM0090 List of tables Table 40. SYSCFG register map and reset values (STM32F405xx/07xx and STM32F415xx/17xx) 296 Table 41. SYSCFG register map and reset values (STM32F42xxx and STM32F43xxx) ..303 Table 42. DMA1 request mapping ..........309 Table 43.
Page 42 List of tables RM0090 Table 92. Counting direction versus encoder signals ........546 Table 93.
Page 43 RM0090 List of tables Table 137. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 16............976 Table 138.
Page 44 List of tables RM0090 Table 183. bxCAN register map and reset values ........1109 Table 184.
Page 45 RM0090 List of tables Table 233. FSMC_BTRx bit fields ..........1552 Table 234.
Page 46 List of tables RM0090 Table 285. 8-bit NAND Flash ............1635 Table 286.
Page 47 RM0090 List of figures List of figures Figure 1. System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices..60 Figure 2. System architecture for STM32F42xxx and STM32F43xxx devices ....62 Figure 3.
Page 48 List of figures RM0090 Figure 46. Analog watchdog’s guarded area ......... . . 396 Figure 47.
Page 49 RM0090 List of figures Figure 97. Counter timing diagram, internal clock divided by 4 ......520 Figure 98.
Page 50 List of figures RM0090 Figure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 ....591 Figure 149. Counter timing diagram, internal clock divided by 2 ......592 Figure 150.
Page 51 RM0090 List of figures Figure 198. Edge-aligned PWM waveforms (ARR=8) ........656 Figure 199.
Page 52 List of figures RM0090 Figure 248. Data clock timing diagram ..........871 Figure 249.
Page 53 RM0090 List of figures Figure 294. Overrun detection error........... 938 Figure 295.
Page 54 List of figures RM0090 Figure 346. Bit timing ............. 1085 Figure 347.
Page 55 RM0090 List of figures Figure 398. Normal bulk/control OUT/SETUP and bulk/control IN transactions ....1329 Figure 399. Bulk/control IN transactions ..........1332 Figure 400.
Page 56 List of figures RM0090 Figure 448. Asynchronous wait during a write access ........1557 Figure 449.
Page 57: Documentation Conventions
RM0090 Documentation conventions Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value.
Page 58: Glossary
Documentation conventions RM0090 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • The CPU core integrates two debug ports: – JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol. –...
Page 59: Memory And Bus Architecture
RM0090 Memory and bus architecture Memory and bus architecture System architecture In STM32F405xx/07xx and STM32F415xx/17xx, the main system consists of 32-bit multilayer AHB bus matrix that interconnects: The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Eight masters: ®...
Page 60: Figure 1. System Architecture For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx Devices
Memory and bus architecture RM0090 Figure 1. System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices 60/1731 DocID018909 Rev 11...
Page 61 RM0090 Memory and bus architecture In the STM32F42xx and STM32F43xx devices, the main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Ten masters: ® – Cortex -M4 with FPU core I-bus, D-bus and S-bus – DMA1 memory bus –...
Page 62: I-Bus
Memory and bus architecture RM0090 Figure 2. System architecture for STM32F42xxx and STM32F43xxx devices 2.1.1 I-bus ® This bus connects the Instruction bus of the Cortex -M4 with FPU core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM or external memories through the FSMC/FMC).
Page 63: Dma Memory Bus
RM0090 Memory and bus architecture 2.1.4 DMA memory bus This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the DMA to perform transfer to/from memories. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the FSMC/FMC.
Page 64: Ahb/Apb Bridges (Apb)
Memory and bus architecture RM0090 2.1.11 AHB/APB bridges (APB) The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency. Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies, and to Table 1 for the address mapping of AHB and APB peripherals.
Page 65 RM0090 Memory and bus architecture Table 1. STM32F4xx register boundary addresses (continued) Boundary address Peripheral Register map 0x5006 0800 - 0x5006 0BFF Section 24.4.4: RNG register map on page 762 0x5006 0400 - 0x5006 07FF HASH Section 25.4.9: HASH register map on page 786 0x5006 0000 - 0x5006 03FF CRYP Section 23.6.13: CRYP register map on page 754...
Page 66 Memory and bus architecture RM0090 Table 1. STM32F4xx register boundary addresses (continued) Boundary address Peripheral Register map 0x4001 4800 - 0x4001 4BFF TIM11 Section 19.5.12: TIM10/11/13/14 register map on page 686 0x4001 4400 - 0x4001 47FF TIM10 Section 19.4.13: TIM9/12 register map on 0x4001 4000 - 0x4001 43FF TIM9 page 675...
Page 67 RM0090 Memory and bus architecture Table 1. STM32F4xx register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7400 - 0x4000 77FF Section 14.5.15: DAC register map on page 455 0x4000 7000 - 0x4000 73FF Section 5.6: PWR register map on page 149 0x4000 6800 - 0x4000 6BFF CAN2 Section 32.9.5: bxCAN register map on page 1109...
Page 68: Embedded Sram
Memory and bus architecture RM0090 2.3.1 Embedded SRAM The STM32F405xx/07xx and STM32F415xx/17xx feature 4 Kbytes of backup SRAM (see Section 5.1.2: Battery backup domain) plus 192 Kbytes of system SRAM. The STM32F42xxx and STM32F43xxx feature 4 Kbytes of backup SRAM (see Section 5.1.2: Battery backup domain) plus 256 Kbytes of system SRAM.
Page 69: Boot Configuration
RM0090 Memory and bus architecture ® are only available for Cortex -M4 with FPU accesses, and not from other bus masters (e.g. DMA). A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number ×...
Page 70 Memory and bus architecture RM0090 The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.
Page 71: Table 3. Memory Mapping Vs. Boot Mode/Physical Remap In Stm32F405Xx/07Xx And Stm32F415Xx/17Xx
RM0090 Memory and bus architecture Table 3. Memory mapping vs. Boot mode/physical remap in STM32F405xx/07xx and STM32F415xx/17xx Boot/Remap in Boot/Remap in Boot/Remap in Addresses Remap in FSMC main Flash memory embedded SRAM System memory 0x2001 C000 - 0x2001 FFFF SRAM2 (16 KB) SRAM2 (16 KB) SRAM2 (16 KB) SRAM2 (16 KB)
Page 72 Memory and bus architecture RM0090 Table 4. Memory mapping vs. Boot mode/physical remap in STM32F42xxx and STM32F43xxx (continued) Boot/Remap in Boot/Remap in Boot/Remap in Addresses Remap in FMC main Flash memory embedded SRAM System memory FMC bank 1 0x0400 0000 - 0x07FF FFFF Reserved Reserved Reserved...
Page 73: Embedded Flash Memory Interface
RM0090 Embedded Flash memory interface Embedded Flash memory interface Introduction The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 74: Embedded Flash Memory In Stm32F405Xx/07Xx And Stm32F415Xx/17Xx
Embedded Flash memory interface RM0090 Figure 4. Flash memory interface connection inside system architecture (STM32F42xxx and STM32F43xxx) Embedded Flash memory in STM32F405xx/07xx and STM32F415xx/17xx The Flash memory has the following main features: • Capacity up to 1 Mbyte • 128 bits wide data read •...
Page 75: Table 5. Flash Module Organization (Stm32F40X And Stm32F41X)
RM0090 Embedded Flash memory interface Table 5. Flash module organization (STM32F40x and STM32F41x) Block Name Block base addresses Size Sector 0 0x0800 0000 - 0x0800 3FFF 16 Kbytes Sector 1 0x0800 4000 - 0x0800 7FFF 16 Kbytes Sector 2 0x0800 8000 - 0x0800 BFFF 16 Kbytes Sector 3 0x0800 C000 - 0x0800 FFFF...
Page 76: Embedded Flash Memory In Stm32F42Xxx And Stm32F43Xxx
Embedded Flash memory interface RM0090 Embedded Flash memory in STM32F42xxx and STM32F43xxx The Flash memory has the following main features: • Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write capability (RWW) • 128 bits wide data read •...
Page 77: Table 6. Flash Module - 2 Mbyte Dual Bank Organization (Stm32F42Xxx And Stm32F43Xxx)
RM0090 Embedded Flash memory interface Table 6. Flash module - 2 Mbyte dual bank organization (STM32F42xxx and STM32F43xxx) Block Bank Name Block base addresses Size Sector 0 0x0800 0000 - 0x0800 3FFF 16 Kbytes Sector 1 0x0800 4000 - 0x0800 7FFF 16 Kbytes Sector 2 0x0800 8000 - 0x0800 BFFF...
Page 78: Mbyte Flash Memory Single Bank Vs Dual Bank Organization (Stm32F42Xxx And Stm32F43Xxx)
Embedded Flash memory interface RM0090 Table 7. 1 Mbyte Flash memory single bank vs dual bank organization (STM32F42xxx and STM32F43xxx) 1 Mbyte single bank Flash memory (default) 1 Mbyte dual bank Flash memory DB1M=0 DB1M=1 Main memory Sector number Sector size Main memory Sector number Sector size...
Page 79: Table 9. 1 Mbyte Dual Bank Flash Memory Organization (Stm32F42Xxx And Stm32F43Xxx)
RM0090 Embedded Flash memory interface Table 8. 1 Mbyte single bank Flash memory organization (STM32F42xxx and STM32F43xxx) (continued) Block Bank Name Block base addresses Size System memory 0x1FFF 0000 - 0x1FFFF 77FF 30 Kbytes 0x1FFF 7800 - 0x1FFF 7A0F 528 bytes 0x1FFF C000 - 0x1FFF C00F 16 bytes Option bytes...
Page 80: Read Interface
Embedded Flash memory interface RM0090 Read interface 3.5.1 Relation between CPU clock frequency and Flash memory read time To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.
Page 81: Table 11. Number Of Wait States According To Cpu Clock (Hclk) Frequency (Stm32F42Xxx And Stm32F43Xxx)
RM0090 Embedded Flash memory interface Table 11. Number of wait states according to CPU clock (HCLK) frequency (STM32F42xxx and STM32F43xxx) HCLK (MHz) Wait states (WS) Voltage range Voltage range Voltage range Voltage range (LATENCY) 1.8 V - 2.1 V 2.7 V - 3.6 V 2.4 V - 2.7 V 2.1 V - 2.4 V Prefetch OFF...
Page 82: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
Embedded Flash memory interface RM0090 Note: A change in CPU clock configuration or wait state (WS) configuration may not be effective straight away. To make sure that the current CPU clock frequency is the one you have configured, you can check the AHB prescaler factor and clock source status values. To make sure that the number of WS you have programmed is effective, you can read the FLASH_ACR register.
Page 83: Figure 5. Sequential 32-Bit Instruction Execution
RM0090 Embedded Flash memory interface Figure 5. Sequential 32-bit instruction execution When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states.
Page 84: Erase And Program Operations
Embedded Flash memory interface RM0090 Instruction cache memory To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory. This feature can be enabled by setting the instruction cache enable (ICEN) bit in the FLASH_ACR register.
Page 85: Program/Erase Parallelism
RM0090 Embedded Flash memory interface Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared.
Page 86: Programming
Embedded Flash memory interface RM0090 Bank erase in STM32F42xxx and STM32F43xxx devices To erase bank 1 or bank 2, follow the procedure below: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register Set MER or MER1 bit accordingly in the FLASH_CR register Set the STRT bit in the FLASH_CR register Wait for the BSY bit to be reset.
Page 87: Read-While-Write (Rww)
RM0090 Embedded Flash memory interface Programming errors It is not allowed to program data to the Flash memory that would cross the 128-bit row boundary. In such a case, the write operation is not performed and a program alignment error flag (PGAERR) is set in the FLASH_SR register. The write access type (byte, half-word, word or double word) must correspond to the type of parallelism chosen (x8, x16, x32 or x64).
Page 88: Interrupts
Embedded Flash memory interface RM0090 Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register (BSY is active when erase/program operation is on going on bank 1 or bank 2) Set the PG bit in the FLASH_CR register Perform the data write operation(s) to the desired memory address inside main memory block or OTP area Wait for the BSY bit to be reset.
Page 89: Table 15. Description Of The Option Bytes (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx)
RM0090 Embedded Flash memory interface Table 14. Option byte organization (continued) Address [63:16] [15:0] 0x1FFE C000 Reserved Reserved SPRMOD and Write protection nWRP bits for 0x1FFE C008 Reserved sectors 12 to 23 Table 15. Description of the option bytes (STM32F405xx/07xx and STM32F415xx/17xx) Option bytes (word, address 0x1FFF C000) RDP: Read protection option byte.
Page 90: Table 16. Description Of The Option Bytes (Stm32F42Xxx And Stm32F43Xxx)
Embedded Flash memory interface RM0090 Table 15. Description of the option bytes (STM32F405xx/07xx and STM32F415xx/17xx) (continued) Option bytes (word, address 0x1FFF C008) Bits 15:12 0xF: Not used nWRP: Flash memory write protection option bytes Sectors 0 to 11 can be write protected. nWRPi Bits 11:0 0: Write protection active on selected sector...
Page 91 RM0090 Embedded Flash memory interface Table 16. Description of the option bytes (STM32F42xxx and STM32F43xxx) (continued) BOR_LEV: BOR reset Level These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory. 00: BOR Level 3 (VBOR3), brownout threshold level 3 Bits 3:2 01: BOR Level 2 (VBOR2), brownout threshold level 2...
Page 92: Programming User Option Bytes
Embedded Flash memory interface RM0090 Table 16. Description of the option bytes (STM32F42xxx and STM32F43xxx) (continued) Option bytes (word, address 0x1FFE C008) Bit 15:12 0xF: not used nWRP: Flash memory write protection option bytes for bank 2. Sectors 12 to 23 can be write protected.
Page 93: Read Protection (Rdp)
The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a consequence, boundary scan cannot be performed. STMicroelectronics is not able to perform analysis on defective parts on which the Level 2 protection has been set.
Page 94: Write Protections
Embedded Flash memory interface RM0090 Table 17. Access versus read protection level Debug features, Boot from RAM or Booting from Flash memory Protection from System memory bootloader Memory area Level Read Write Erase Read Write Erase Level 1 Main Flash Memory and Backup SRAM Level 2 Level 1...
Page 95: Proprietary Code Readout Protection (Pcrop)
RM0090 Embedded Flash memory interface sector cannot be erased or programmed. Consequently, a mass erase cannot be performed if one of the sectors is write-protected. If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register.
Page 96: Figure 7. Pcrop Levels
Embedded Flash memory interface RM0090 When a sector is readout protected (PCROP mode activated), it can only be accessed for code fetch through ICODE Bus on Flash interface: • Any read access performed through the D-bus triggers a RDERR flag error. •...
Page 97: One-Time Programmable Bytes
RM0090 Embedded Flash memory interface One-time programmable bytes Table 18 shows the organization of the one-time programmable (OTP) part of the OTP area. Table 18. OTP area organization Block [128:96] [95:64] [63:32] [31:0] Address byte 0 OTP0 OTP0 OTP0 OTP0 0x1FFF 7800 OTP0 OTP0...
Page 98: Flash Interface Registers
Embedded Flash memory interface RM0090 Flash interface registers 3.9.1 Flash access control register (FLASH_ACR) for STM32F405xx/07xx and STM32F415xx/17xx The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency. Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access...
Page 99: Flash Access Control Register (Flash_Acr)
RM0090 Embedded Flash memory interface 3.9.2 Flash access control register (FLASH_ACR) for STM32F42xxx and STM32F43xxx The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency. Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved...
Page 100: Flash Key Register (Flash_Keyr)
Embedded Flash memory interface RM0090 3.9.3 Flash key register (FLASH_KEYR) The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations. Address offset: 0x04 Reset value: 0x0000 0000 Access: no wait state, word access KEY[31:16] KEY[15:0] Bits 31:0 FKEYR[31:0]: FPEC key...
Page 101: Flash Status Register (Flash_Sr) For
RM0090 Embedded Flash memory interface 3.9.5 Flash status register (FLASH_SR) for STM32F405xx/07xx and STM32F415xx/17xx The Flash status register gives information on ongoing program and erase operations. Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved PGSERR PGPERR PGAERR WRPERR OPERR...
Page 102: Stm32F42Xxx And Stm32F43Xxx
Embedded Flash memory interface RM0090 Bits 3:2 Reserved, must be kept cleared. Bit 1 OPERR: Operation error Set by hardware when a flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1).
Page 103: Flash Control Register (Flash_Cr) For
RM0090 Embedded Flash memory interface Bit 6 PGPERR: Programming parallelism error Set by hardware when the size of the access (byte, half-word, word, double word) during the program sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, x64).
Page 104 Embedded Flash memory interface RM0090 Bit 31 LOCK: Lock Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In the event of an unsuccessful unlock operation, this bit remains set until the next reset. Bits 30:26 Reserved, must be kept cleared.
Page 105: Flash Control Register (Flash_Cr) For
RM0090 Embedded Flash memory interface 3.9.8 Flash control register (FLASH_CR) for STM32F42xxx and STM32F43xxx The Flash control register is used to configure and start Flash memory operations. Address offset: 0x10 Reset value: 0x8000 0000 Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.
Page 106: Flash Option Control Register (Flash_Optcr) For
Embedded Flash memory interface RM0090 Bits 7:3 SNB[3:0]: Sector number These bits select the sector to erase. 0000: sector 0 0001: sector 1 01011: sector 11 01100: not allowed 01101: not allowed 01110: not allowed 01111: not allowed 10000: section 12 10001: section 13 11011 sector 23 11100: not allowed...
Page 107 RM0090 Embedded Flash memory interface Bits 31:28 Reserved, must be kept cleared. Bits 27:16 nWRP[11:0]: Not write protect These bits contain the value of the write-protection option bytes after reset. They can be written to program a new write protect value into Flash memory. 0: Write protection active on selected sector 1: Write protection inactive on selected sector Bits 15:8 RDP[7:0]: Read protect...
Page 108: Flash Option Control Register (Flash_Optcr)
Embedded Flash memory interface RM0090 3.9.10 Flash option control register (FLASH_OPTCR) for STM32F42xxx and STM32F43xxx The FLASH_OPTCR register is used to modify the user option bytes. Address offset: 0x14 Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at reset release.
Page 109 RM0090 Embedded Flash memory interface Bits 7:5 USER: User option bytes These bits contain the value of the user option byte after reset. They can be written to program a new user option byte value into Flash memory. Bit 7: nRST_STDBY Bit 6: nRST_STOP Bit 5: WDG_SW Note: When changing the WDG mode from hardware to software or from software to...
Page 110: Flash Option Control Register (Flash_Optcr1)
Embedded Flash memory interface RM0090 3.9.11 Flash option control register (FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx This register is available only on STM32F42xxx and STM32F43xxx. The FLASH_OPTCR1 register is used to modify the user option bytes for bank 2. Address offset: 0x18 Reset value: 0x0FFF 0000.
Page 111: Flash Interface Register Map
RM0090 Embedded Flash memory interface 3.9.12 Flash interface register map Table 19. Flash register map and reset values (STM32F405xx/07xx and STM32F415xx/17xx) Offset Register LATENCY FLASH_ACR [2:0] 0x00 Reserved Reserved Reset value FLASH_ KEY[31:16] KEY[15:0] KEYR 0x04 Reset value FLASH_OPT OPTKEYR[31:16] OPTKEYR[15:0] KEYR 0x08...
Page 112 Embedded Flash memory interface RM0090 Table 20. Flash register map and reset values (STM32F42xxx and STM32F43xxx) (continued) Offset Register FLASH_CR SNB[4:0] 0x10 Reserved Reserved Reserved Reset value FLASH_OPTCR nWRP[11:0] RDP[7:0] 0x14 Reset value 1 0 1 FLASH_ nWRP[11:0] OPTCR1 0x18 Reserved Reset value 112/1731...
Page 113: Crc Calculation Unit
RM0090 CRC calculation unit CRC calculation unit This section applies to the whole STM32F4xx family, unless otherwise specified. CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 114: Crc Functional Description
CRC calculation unit RM0090 CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: • is used as an input register to enter new data in the CRC calculator (when writing into the register) •...
Page 115: Control Register (Crc_Cr)
RM0090 CRC calculation unit Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
Page 116: Power Controller (Pwr)
Power controller (PWR) RM0090 Power controller (PWR) This section applies to the whole STM32F4xx family, unless otherwise specified. Power supplies The device requires a 1.8 to 3.6 V operating voltage supply (V ). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power. The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V voltage when the main V...
Page 117: Independent A/D Converter Supply And Reference Voltage
RM0090 Power controller (PWR) Figure 10. Power supply overview for STM32F42xxx and STM32F43xxx 1. V and V must be connected to V and V , respectively. 5.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.
Page 118: Battery Backup Domain
Power controller (PWR) RM0090 5.1.2 Battery backup domain Backup domain description To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when is turned off, V pin can be connected to an optional standby voltage supplied by a battery or by another source.
Page 119 RM0090 Power controller (PWR) When the backup domain is supplied by V (analog switch connected to V because is not present), the following functions are available: • PC14 and PC15 can be used as LSE pins only • PC13 can be used as the RTC_AF1 pin (refer to Table 37: RTC_AF1 pin for more details about this pin configuration)
Page 120: Voltage Regulator For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx
Power controller (PWR) RM0090 by a dedicated bit, the BRE control bit of the PWR_CSR register (see Section 5.4.2: PWR power control/status register (PWR_CSR) for STM32F405xx/07xx and STM32F415xx/17xx). The backup SRAM is not mass erased by an tamper event. When the Flash memory is read protected, the backup SRAM is also read protected to prevent confidential data, such as cryptographic private key, from being accessed.
Page 121: Voltage Regulator For Stm32F42Xxx And Stm32F43Xxx
RM0090 Power controller (PWR) regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). The programmed voltage scale remains the same during Stop mode: The programmed voltage scale remains the same during Stop mode (see Section 5.4.1: PWR power control register (PWR_CR) for STM32F405xx/07xx STM32F415xx/17xx).
Page 122: Table 22. Voltage Regulator Configuration Mode Versus Device Operating Mode
Power controller (PWR) RM0090 (PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx. 2 operating modes are available: – Normal mode: The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3) – Over-drive mode: This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for the voltage scaling scale 1 and scale •...
Page 123 RM0090 Power controller (PWR) Entering Over-drive mode It is recommended to enter Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. To optimize the configuration time, enable the Over-drive mode during the PLL lock phase. To enter Over-drive mode, follow the sequence below: Select HSI or HSE as system clock.
Page 124: Power Supply Supervisor
Power controller (PWR) RM0090 Example of sequence 2: Select HSI or HSE as system clock source. Disable the peripheral clocks that are not generated by the System PLL (I2S clock, LCD-TFT clock, SAI1 clock, USB_48MHz clock,..). Reset the ODSW bit in the PWR_CR register to switch back the voltage regulator to Normal mode.
Page 125: Brownout Reset (Bor)
RM0090 Power controller (PWR) 5.2.2 Brownout reset (BOR) During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V threshold. is configured through device option bytes. By default, BOR is off. 3 programmable threshold levels can be selected: •...
Page 126: Low-Power Modes
Power controller (PWR) RM0090 for STM32F42xxx and STM32F43xxx. The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the PWR power control/status register (PWR_CSR) for STM32F405xx/07xx and STM32F415xx/17xx, to indicate if V is higher or lower than the PVD threshold.
Page 127 RM0090 Power controller (PWR) Entering low-power mode Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or ® WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex -M4 with FPU System Control register is set on Return from ISR. Entering Low-power mode through WFI or WFE will be executed only if no interrupt is pending or no event is pending.
Page 128: Slowing Down System Clocks
Power controller (PWR) RM0090 Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. Table 23. Low-power mode summary Effect on Effect on 1.2 V Mode name Entry Wakeup Voltage regulator domain clocks domain clocks WFI or Return Sleep CPU CLK OFF Any interrupt...
Page 129: Sleep Mode
RM0090 Power controller (PWR) Peripheral clock gating is controlled by the AHB1 peripheral clock enable register (RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3 peripheral clock enable register (RCC_AHB3ENR) (see Section 7.3.10: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR), Section 7.3.11: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR), Section 7.3.12: RCC AHB3 peripheral clock...
Page 130: Stop Mode (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx)
Power controller (PWR) RM0090 Table 24. Sleep-now entry and exit (continued) Sleep-now mode Description If WFI or Return from ISR was used for entry: Interrupt: Refer to Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx Table 62: Vector table for STM32F42xxx and STM32F43xxx If WFE was used for entry and SEVONPEND = 0 Mode exit...
Page 131: Table 26. Stop Operating Modes (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx)
RM0090 Power controller (PWR) Table 26. Stop operating modes (STM32F405xx/07xx and STM32F415xx/17xx) Stop mode LPDS bit FPDS bit Wake-up latency STOP MR HSI RC startup time (Main regulator) HSI RC startup time + STOP MR-FPD Flash wakeup time from Power Down mode HSI RC startup time + STOP LP...
Page 132: Table 27. Stop Mode Entry And Exit (For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx)
Power controller (PWR) RM0090 Note: If the application needs to disable the external clock before entering Stop mode, the HSEON bit must first be disabled and the system clock switched to HSI. Otherwise, if the HSEON bit is kept enabled while the external clock (external oscillator) can be removed before entering stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering stop mode.
Page 133: Stop Mode (Stm32F42Xxx And Stm32F43Xxx)
RM0090 Power controller (PWR) Table 27. Stop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx) Stop mode Description If WFI or Return from ISR was used for entry: Any EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability.
Page 134: Table 28. Stop Operating Modes (Stm32F42Xxx And Stm32F43Xxx)
Power controller (PWR) RM0090 Table 28. Stop operating modes (STM32F42xxx and STM32F43xxx) UDEN[1:0] MRUDS LPUDS LPDS FPDS Voltage Regulator Mode Wakeup latency bits STOP MR HSI RC startup time (Main Regulator) HSI RC startup time + STOP MR- FPD Flash wakeup time from power- down mode HSI RC startup time + Normal...
Page 135 RM0090 Power controller (PWR) In Stop mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 21.3 Section 21: Independent watchdog (IWDG).
Page 136: Standby Mode
Power controller (PWR) RM0090 Table 29. Stop mode entry and exit (STM32F42xxx and STM32F43xxx) Stop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – No interrupt or event is pending, ® – SLEEPDEEP bit is set in Cortex -M4 with FPU System Control register, –...
Page 137: Table 30. Standby Mode Entry And Exit
RM0090 Power controller (PWR) Entering Standby mode The Standby mode is entered according to Section : Entering low-power mode, when the ® SLEEPDEEP bit in the Cortex -M4 with FPU System Control register is set. Refer to Table 30 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: •...
Page 138: Programming The Rtc Alternate Functions To Wake Up The Device From The Stop And Standby Modes
Power controller (PWR) RM0090 I/O states in Standby mode In Standby mode, all I/O pins are high impedance except for: • Reset pad (still available) • RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out •...
Page 139 RM0090 Power controller (PWR) RTC alternate functions to wake up the device from the Stop mode • To wake up the device from the Stop mode with an RTC alarm event, it is necessary to: Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) Enable the RTC Alarm Interrupt in the RTC_CR register Configure the RTC to generate the RTC alarm...
Page 140 Power controller (PWR) RM0090 Clear the PWR Wakeup (WUF) flag Enable the RTC alarm interrupt Re-enter the low-power mode • When using RTC wakeup to wake up the device from the low-power modes: Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register) Clear the RTC Wakeup (WUTF) flag Clear the PWR Wakeup (WUF) flag Enable the RTC Wakeup interrupt...
Page 141: Power Control Registers (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx)
RM0090 Power controller (PWR) Power control registers (STM32F405xx/07xx and STM32F415xx/17xx) 5.4.1 PWR power control register (PWR_CR) STM32F405xx/07xx and STM32F415xx/17xx Address offset: 0x00 Reset value: 0x0000 4000 (reset by wakeup from Standby mode) Reserved FPDS PLS[2:0] PVDE CSBF CWUF PDDS LPDS Res.
Page 142: Pwr Power Control/Status Register (Pwr_Csr)
Power controller (PWR) RM0090 Bit 4 PVDE: Power voltage detector enable This bit is set and cleared by software. 0: PVD disabled 1: PVD enabled Bit 3 CSBF: Clear standby flag This bit is always read as 0. 0: No effect 1: Clear the SBF Standby Flag (write).
Page 143 RM0090 Power controller (PWR) Bits 13:10 Reserved, must be kept at reset value. Bit 9 BRE: Backup regulator enable When set, the Backup regulator (used to maintain backup SRAM content in Standby and modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup SRAM can still be used but its content will be lost in the Standby and V modes.
Page 144: Power Control Registers (Stm32F42Xxx And Stm32F43Xxx)
Power controller (PWR) RM0090 Power control registers (STM32F42xxx and STM32F43xxx) 5.5.1 PWR power control register (PWR_CR) for STM32F42xxx and STM32F43xxx Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) ODSWE UDEN[1:0] ODEN Reserved VOS[1:0] ADCDC1 MRUDS LPUDS FPDS PLS[2:0]...
Page 145 RM0090 Power controller (PWR) Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection These bits control the main internal voltage regulator output voltage to achieve a trade-off between performance and power consumption when the device does not operate at the maximum frequency (refer to the STM32F42xx and STM32F43xx datasheets for more details).
Page 146 Power controller (PWR) RM0090 Bits 7:5 PLS[2:0]: PVD level selection These bits are written by software to select the voltage threshold detected by the Power Voltage Detector 000: 2.0 V 001: 2.1 V 010: 2.3 V 011: 2.5 V 100: 2.6 V 101: 2.7 V 110: 2.8 V 111: 2.9 V...
Page 147: Pwr Power Control/Status Register (Pwr_Csr)
RM0090 Power controller (PWR) 5.5.2 PWR power control/status register (PWR_CSR) for STM32F42xxx and STM32F43xxx Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. UDRDY[1:0] ODSWRDY ODRDY Reserved...
Page 148 Power controller (PWR) RM0090 Bit 8 EWUP: Enable WKUP pin This bit is set and cleared by software. 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode. 1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Page 149: Pwr Register Map
RM0090 Power controller (PWR) PWR register map The following table summarizes the PWR registers. Table 31. PWR - register map and reset values for STM32F405xx/07xx and STM32F415xx/17xx Offset Register PWR_CR PLS[2:0] 0x000 Reserved Reserved Reset value PWR_CSR 0x004 Reserved Reserved Reserved Reset value Table 32.
Page 150: Reset And Clock Control For Stm32F42Xxx And Stm32F43Xxx (Rcc)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 6.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure A system reset is generated when one of the following events occurs:...
Page 151: Backup Domain Reset
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address in the memory map. 0x0000_0004 The system reset signal provided to the device is output on the NRST pin.
Page 152: Figure 16. Clock Tree
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Each clock source can be switched on or off independently when it is not used, to optimize power consumption. Figure 16. Clock tree 1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet.
Page 153 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like Ethernet, USB OTG FS and HS, I2S, SAI, LTDC, and SDIO.
Page 154: Hse Clock
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 ® FCLK acts as Cortex -M4 with FPU free-running clock. For more details, refer to the ® Cortex -M4 with FPU technical reference manual. 6.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: •...
Page 155: Hsi Clock
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control register (RCC_CR). 6.2.2 HSI clock The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used directly as a system clock, or used as PLL input.
Page 156: Lse Clock
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 The three PLLs are disabled by hardware when entering Stop and Standby modes, or when an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. PLL configuration register (RCC_PLLCFGR),RCC clock configuration register (RCC_CFGR), and RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
Page 157: Clock Security System (Css)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.2.7 Clock security system (CSS) The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an interrupt is generated to inform the software about the failure (clock security system...
Page 158: Watchdog Clock
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Note: To read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (f < 7xf ), the software must read the calendar time and APB1 RTCLCK date registers twice.
Page 159: Figure 18. Frequency Measurement With Tim5 In Input Capture Mode
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) The primary purpose of having the LSE connected to the channel4 input capture is to be able to precisely measure the HSI (this requires to have the HSI used as the system clock source).
Page 160: Figure 19. Frequency Measurement With Tim11 In Input Capture Mode
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Figure 19. Frequency measurement with TIM11 in Input capture mode 160/1731 DocID018909 Rev 11...
Page 161: Rcc Registers
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RCC registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. 6.3.1 RCC clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLSAI PLLSAI...
Page 162 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure is detected.
Page 163: Rcc Pll Configuration Register (Rcc_Pllcfgr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •...
Page 164 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled. Caution: The software has to set these bits correctly not to exceed 180 MHz on this domain.
Page 165: Rcc Clock Configuration Register (Rcc_Cfgr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.3.3 RCC clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. I2SSC MCO2 MCO2 PRE[2:0]...
Page 166 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bits 22:21 MCO1: Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset before enabling the external oscillators and PLL.
Page 167: Rcc Clock Interrupt Register (Rcc_Cir)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control AHB clock division factor. Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after HPRE write.
Page 168 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 22 PLLSAIRDYC: PLLSAI Ready Interrupt Clear This bit is set by software to clear PLLSAIRDYF flag.
Page 169 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 11 HSERDYIE: HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.
Page 170: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 3 HSERDYF: HSE ready interrupt flag This bit is set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. It is cleared by software by setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator Bit 2 HSIRDYF: HSI ready interrupt flag...
Page 171 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 25 ETHMACRST: Ethernet MAC reset This bit is set and cleared by software. 0: does not reset Ethernet MAC 1: resets Ethernet MAC Bit 24 Reserved, must be kept at reset value. Bit 23 DMA2DRST: DMA2D reset This bit is set and reset by software.
Page 172 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 5 GPIOFRST: IO port F reset This bit is set and cleared by software. 0: does not reset IO port F 1: resets IO port F Bit 4 GPIOERST: IO port E reset This bit is set and cleared by software.
Page 173: Rcc Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved OTGFS HASH CRYP DCMI Reserved Reserved Bits 31:8 Reserved, must be kept at reset value.
Page 174: Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 6.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Reserved FMCRST Reserved Bits 31:1 Reserved, must be kept at reset value. Bit 0 FMCRST: Flexible memory controller module reset Set and cleared by software.
Page 175 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 31 UART8RST: UART8 reset Set and cleared by software. 0: does not reset UART8 1: resets UART8 Bit 30 UART7RST: UART7 reset Set and cleared by software. 0: does not reset UART7 1: resets UART7 Bit 29 DACRST: DAC reset Set and cleared by software.
Page 176 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 18 USART3RST: USART3 reset Set and cleared by software. 0: does not reset USART3 1: resets USART3 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: does not reset USART2 1: resets USART2 Bit 16 Reserved, must be kept at reset value.
Page 177 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 3 TIM5RST: TIM5 reset Set and cleared by software. 0: does not reset TIM5 1: resets TIM5 Bit 2 TIM4RST: TIM4 reset Set and cleared by software. 0: does not reset TIM4 1: resets TIM4 Bit 1 TIM3RST: TIM3 reset Set and cleared by software.
Page 178: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 SAI1 SPI6 SPI5 CRST Reserved Reserved Res.
Page 179 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 15 Reserved, must be kept at reset value. Bit 14 SYSCFGRST: System configuration controller reset This bit is set and cleared by software. 0: does not reset the System configuration controller 1: resets the System configuration controller Bit 13 SPI4RST: SPI4 reset This bit is set and cleared by software.
Page 180: Rcc Ahb1 Peripheral Clock Register (Rcc_Ahb1Enr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 6.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR) Address offset: 0x30 Reset value: 0x0010 0000 Access: no wait state, word, half-word and byte access. OTGH ETHM ETHM ETHM OTGH ETHMA DMA2D DMA2E DMA1E CCMDAT...
Page 181 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 22 DMA2EN: DMA2 clock enable This bit is set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 21 DMA1EN: DMA1 clock enable This bit is set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled Bit 20 CCMDATARAMEN: CCM data RAM clock enable...
Page 182: Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 5 GPIOFEN: IO port F clock enable This bit is set and cleared by software. 0: IO port F clock disabled 1: IO port F clock enabled Bit 4 GPIOEEN: IO port E clock enable This bit is set and cleared by software.
Page 183: Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 5 HASHEN: Hash modules clock enable This bit is set and cleared by software. 0: Hash modules clock disabled 1: Hash modules clock enabled Bit 4 CRYPEN: Cryptographic modules clock enable This bit is set and cleared by software.
Page 184 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 31 UART8EN: UART8 clock enable This bit is set and cleared by software. 0: UART8 clock disabled 1: UART8 clock enabled Bit 30 UART7EN: UART7 clock enable This bit is set and cleared by software. 0: UART7 clock disabled 1: UART7 clock enabled Bit 29 DACEN: DAC interface clock enable...
Page 185 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 18 USART3EN: USART3 clock enable This bit is set and cleared by software. 0: USART3 clock disabled 1: USART3 clock enabled Bit 17 USART2EN: USART2 clock enable This bit is set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bit 16 Reserved, must be kept at reset value.
Page 186 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 3 TIM5EN: TIM5 clock enable This bit is set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled Bit 2 TIM4EN: TIM4 clock enable This bit is set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 clock enable...
Page 187: Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR) Address offset: 0x44 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 LTDC SAI1EN SPI6EN SPI5EN Reserved Reserved Res.
Page 188 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 14 SYSCFGEN: System configuration controller clock enable This bit is set and cleared by software. 0: System configuration controller clock disabled 1: System configuration controller clock enabled Bit 13 SPI4EN: SPI4 clock enable This bit is set and cleared by software.
Page 189: Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) Address offset: 0x50 Reset value: 0x7EEF 97FF Access: no wait state, word, half-word and byte access. OTGHS OTGH ETHPT ETHMA BKPSRA...
Page 190 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode This bit is set and cleared by software. 0: DMA2 clock disabled during Sleep mode 1: DMA2 clock enabled during Sleep mode Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode This bit is set and cleared by software.
Page 191 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 8 GPIOILPEN: IO port I clock enable during Sleep mode This bit is set and cleared by software. 0: IO port I clock disabled during Sleep mode 1: IO port I clock enabled during Sleep mode Bit 7 GPIOHLPEN: IO port H clock enable during Sleep mode This bit is set and cleared by software.
Page 192: Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 6.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) Address offset: 0x54 Reset value: 0x0000 00F1 Access: no wait state, word, half-word and byte access. Reserved OTGFS HASH CRYP DCMI...
Page 193: Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR) Address offset: 0x58 Reset value: 0x0000 0001 Access: no wait state, word, half-word and byte access. Reserved LPEN Reserved Bits 31:1Reserved, must be kept at reset value.
Page 194 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 31 UART8LPEN: UART8 clock enable during Sleep mode This bit is set and cleared by software. 0: UART8 clock disabled during Sleep mode 1: UART8 clock enabled during Sleep mode Bit 30 UART7LPEN: UART7 clock enable during Sleep mode This bit is set and cleared by software.
Page 195 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 18 USART3LPEN: USART3 clock enable during Sleep mode This bit is set and cleared by software. 0: USART3 clock disabled during Sleep mode 1: USART3 clock enabled during Sleep mode Bit 17 USART2LPEN: USART2 clock enable during Sleep mode This bit is set and cleared by software.
Page 196 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode This bit is set and cleared by software. 0: TIM5 clock disabled during Sleep mode 1: TIM5 clock enabled during Sleep mode Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode This bit is set and cleared by software.
Page 197: Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) 6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0x0477 7F33 Access: no wait state, word, half-word and byte access. LTDC SAI1 SPI6 SPI5 TIM11...
Page 198 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode This bit is set and cleared by software. 0: TIM9 clock disabled during Sleep mode 1: TIM9 clock enabled during Sleep mode Bit 15 Reserved, must be kept at reset value.
Page 199: Rcc Backup Domain Control Register (Rcc_Bdcr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode This bit is set and cleared by software. 0: TIM8 clock disabled during Sleep mode 1: TIM8 clock enabled during Sleep mode Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode This bit is set and cleared by software.
Page 200: Rcc Clock Control & Status Register (Rcc_Csr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bits 9:8 RTCSEL[1:0]: RTC clock source selection These bits are set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset.
Page 201 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bit 31 LPWRRSTF: Low-power reset flag This bit is set by hardware when a Low-power management reset occurs. Cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Low-power management...
Page 202: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bits 23:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low-speed oscillator ready This bit is set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
Page 203: Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bits 29:28 Reserved, must be kept at reset value. Bits 27:13 INCSTEP: Incrementation step These bits are set and cleared by software. To write before setting CR[24]=PLLON bit. Configuration input for modulation profile amplitude. Bits 12:0 MODPER: Modulation period These bits are set and cleared by software.
Page 204 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bit 31 Reserved, must be kept at reset value. Bits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks These bits are set and cleared by software to control the I2S clock frequency. These bits should be written only if the PLLI2S is disabled.
Page 205 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bits 23:15 Reserved, must be kept at reset value. Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO These bits are set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when PLLI2S is disabled.
Page 206: Rcc Pll Configuration Register (Rcc_Pllsaicfgr)
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR) Address offset: 0x88 Reset value: 0x2400 3000 Access: no wait state, word, half-word and byte access. This register is used to configure the PLLSAI clock outputs according to the formulas: •...
Page 207: Rcc Dedicated Clock Configuration Register (Rcc_Dckcfgr)
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bits 23:15 Reserved, must be kept at reset value. Bits 14:6 PLLSAIN: PLLSAI division factor for VCO These bits are set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when PLLSAI is disabled.
Page 208 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Bits 31:25 Reserved, must be kept at reset value. Bit 24 TIMPRE: Timers clocks prescalers selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domain.
Page 209 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Bits 12:8 PLLSAIDIVQ: PLLSAI division factor for SAI1 clock These bits are set and reset by software to control the SAI1 clock frequency. They should be written only if PLLSAI is disabled. SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ with 1 ≤...
Page 210: Rcc Register Map
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 6.3.26 RCC register map Table 33 gives the register map and reset values. Table 33. RCC register map and reset values for STM32F42xxx and STM32F43xxx Addr. Register offset name 0x00 RCC_CR Reserved RCC_PLLCFG...
Page 211 RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) Table 33. RCC register map and reset values for STM32F42xxx and STM32F43xxx (continued) Addr. Register offset name RCC_ 0x40 APB1ENR RCC_ 0x44 Reserved APB2ENR 0x48 Reserved Reserved 0x4C Reserved Reserved RCC_AHB1LP 0x50 RCC_AHB2LP...
Page 212 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090 Table 33. RCC register map and reset values for STM32F42xxx and STM32F43xxx (continued) Addr. Register offset name RCC_PLLSAI 0x88 CFGR RCC_DCKCF 0x8C Reserved Reserved PLLSAIDIVQ Reserved PLLI2SDIVQ Refer to Table 1: STM32F4xx register boundary addresses for the register boundary addresses.
Page 213: Reset And Clock Control For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx(Rcc)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 7.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure A system reset is generated when one of the following events occurs:...
Page 214: Power Reset
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Low-power management reset There are two ways of generating a low-power management reset: Reset generated when entering the Standby mode: This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering the Standby mode.
Page 215: Clocks
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR). or V power on, if both supplies have previously been powered off.
Page 216: Figure 21. Clock Tree
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Figure 21. Clock tree 1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet. 216/1731 DocID018909 Rev 11...
Page 217: Hse Clock
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like Ethernet, USB OTG FS and HS, I2S and SDIO.
Page 218: Hsi Clock
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Figure 22. HSE/ LSE clock sources Hardware configuration OSC_OUT External clock (HI-Z) External source OSC_IN OSC_OUT Crystal/ceramic resonators Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. You select this mode by setting the HSEBYP and HSEON bits in the RCC clock control register (RCC_CR).
Page 219: Pll Configuration
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C.
Page 220: Lsi Clock
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware.
Page 221: Rtc/Awu Clock
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.
Page 222: Clock-Out Capability
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.2.10 Clock-out capability Two microcontroller clock output (MCO) pins are available: • MCO1 You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5): –...
Page 223: Figure 23. Frequency Measurement With Tim5 In Input Capture Mode
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement. It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal.
Page 224: Rcc Registers
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 RCC registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. 7.3.1 RCC clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLI2S PLLI2S...
Page 225 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 18 HSEBYP: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
Page 226: Rcc Pll Configuration Register (Rcc_Pllcfgr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •...
Page 227 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled. Caution: The software has to set these bits correctly not to exceed 168 MHz on this domain.
Page 228: Rcc Clock Configuration Register (Rcc_Cfgr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.3 RCC clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. I2SSC MCO2 MCO2 PRE[2:0]...
Page 229 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bits 22:21 MCO1: Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset before enabling the external oscillators and PLL.
Page 230: Rcc Clock Interrupt Register (Rcc_Cir)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control AHB clock division factor. Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after HPRE write.
Page 231 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bits 22 Reserved, must be kept at reset value.
Page 232 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
Page 233: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the HSI oscillator 1: Clock ready interrupt caused by the HSI oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is...
Page 234 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 22 DMA2RST: DMA2 reset Set and cleared by software. 0: does not reset DMA2 1: resets DMA2 Bit 21 DMA1RST: DMA1 reset Set and cleared by software. 0: does not reset DMA1 1: resets DMA1 Bits 20:13 Reserved, must be kept at reset value.
Page 235 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 2 GPIOCRST: IO port C reset Set and cleared by software. 0: does not reset IO port C 1: resets IO port C Bit 1 GPIOBRST: IO port B reset Set and cleared by software.
Page 236: Rcc Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved OTGFS HASH CRYP DCMI Reserved Reserved Bits 31:8 Reserved, must be kept at reset value. Bit 7 OTGFSRST: USB OTG FS module reset Set and cleared by software.
Page 237: Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) 7.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Reserved FSMCRST Reserved Bits 31:1 Reserved, must be kept at reset value. Bit 0 FSMCRST: Flexible static memory controller module reset Set and cleared by software.
Page 238 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: does not reset CAN2 1: resets CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: does not reset CAN1 1: resets CAN1 Bit 24 Reserved, must be kept at reset value.
Page 239 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: does not reset the window watchdog 1: resets the window watchdog Bits 10:9 Reserved, must be kept at reset value.
Page 240: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 Reserved USART USART SPI1 SDIO TIM8 TIM1 SYSCF...
Page 241 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 8 ADCRST: ADC interface reset (common to all ADCs) Set and cleared by software. 0: does not reset the ADC interface 1: resets the ADC interface Bits 7:6 Reserved, must be kept at reset value. Bit 5 USART6RST: USART6 reset Set and cleared by software.
Page 242: Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x30 Reset value: 0x0010 0000 Access: no wait state, word, half-word and byte access. OTGH ETHM ETHM ETHM OTGH ETHMA DMA2E DMA1E CCMDAT BKPSR...
Page 243 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 21 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled Bit 20 CCMDATARAMEN: CCM data RAM clock enable Set and cleared by software. 0: CCM data RAM clock disabled 1: CCM data RAM clock enabled Bit 19 Reserved, must be kept at reset value.
Page 244: Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 2 GPIOCEN: IO port C clock enable Set and cleared by software. 0: IO port C clock disabled 1: IO port C clock enabled Bit 1 GPIOBEN: IO port B clock enable Set and cleared by software.
Page 245: Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 4 CRYPEN: Cryptographic modules clock enable Set and cleared by software. 0: cryptographic module clock disabled 1: cryptographic module clock enabled Bits 3:1 Reserved, must be kept at reset value. Bit 0 DCMIEN: Camera interface enable Set and cleared by software.
Page 246 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACEN: DAC interface clock enable Set and cleared by software. 0: DAC interface clock disabled 1: DAC interface clock enable Bit 28 PWREN: Power interface clock enable Set and cleared by software.
Page 247 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3EN: SPI3 clock enable Set and cleared by software.
Page 248: Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 2 TIM4EN: TIM4 clock enable Set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 clock enable Set and cleared by software. 0: TIM3 clock disabled 1: TIM3 clock enabled Bit 0 TIM2EN: TIM2 clock enable Set and cleared by software.
Page 249 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 14 SYSCFGEN: System configuration controller clock enable Set and cleared by software. 0: System configuration controller clock disabled 1: System configuration controller clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software.
Page 250: Rcc Apb2 Peripheral Clock Enable Register(Rcc_Apb2Enr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.15 RCC APB2 peripheral clock enable register(RCC_APB2ENR) Address offset: 0x44 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 SPI6EN SPI5EN Reserved Res. USART USART SPI1 SDIO...
Page 251 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 SDIOEN: SDIO clock enable Set and cleared by software. 0: SDIO module clock disabled 1: SDIO module clock enabled Bit 10 ADC3EN: ADC3 clock enable Set and cleared by software.
Page 252: Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.16 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) Address offset: 0x50 Reset value: 0x7E67 91FF Access: no wait state, word, half-word and byte access. OTGHS OTGH ETHPT ETHMA BKPSRA SRAM...
Page 253 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode Set and cleared by software. 0: DMA1 clock disabled during Sleep mode 1: DMA1 clock enabled during Sleep mode Bits 20:19 Reserved, must be kept at reset value. Bit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode Set and cleared by software.
Page 254: Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode Set and cleared by software. 0: IO port E clock disabled during Sleep mode 1: IO port E clock enabled during Sleep mode Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode Set and cleared by software.
Page 255: Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 5 HASHLPEN: Hash modules clock enable during Sleep mode Set and cleared by software. 0: Hash modules clock disabled during Sleep mode 1: Hash modules clock enabled during Sleep mode Bit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode Set and cleared by software.
Page 256: Rcc Apb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Apb1Lpenr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.19 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) Address offset: 0x60 Reset value: 0x36FE C9FF Access: no wait state, word, half-word and byte access. USART USART CAN2 CAN1 I2C3 I2C2...
Page 257 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode Set and cleared by software. 0: I2C1 clock disabled during Sleep mode 1: I2C1 clock enabled during Sleep mode Bit 20 UART5LPEN: UART5 clock enable during Sleep mode Set and cleared by software.
Page 258 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 6 TIM12LPEN: TIM12 clock enable during Sleep mode Set and cleared by software. 0: TIM12 clock disabled during Sleep mode 1: TIM12 clock enabled during Sleep mode Bit 5 TIM7LPEN: TIM7 clock enable during Sleep mode Set and cleared by software.
Page 259: Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) 7.3.20 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0407 5F33 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 LPEN LPEN LPEN...
Page 260 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode Set and cleared by software. 0: ADC 3 clock disabled during Sleep mode 1: ADC 3 clock disabled during Sleep mode Bit 9 ADC2LPEN: ADC2 clock enable during Sleep mode Set and cleared by software.
Page 261: Rcc Backup Domain Control Register (Rcc_Bdcr)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) 7.3.21 RCC Backup domain control register (RCC_BDCR) Address offset: 0x70 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register.
Page 262: Rcc Clock Control & Status Register (Rcc_Csr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass the oscillator. This bit can be written only when the LSE clock is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable.
Page 263 RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs.
Page 264: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 7.3.23 RCC spread spectrum clock generation register (RCC_SSCGR) Address offset: 0x80 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. The spread spectrum clock generation is available only for the main PLL. The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.
Page 265: Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr)
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) 7.3.24 RCC PLLI2S configuration register (RCC_PLLI2SCFGR) Address offset: 0x84 Reset value: 0x2000 3000 Access: no wait state, word, half-word and byte access. This register is used to configure the PLLI2S clock outputs according to the formulas: •...
Page 266 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Bits 27:15 Reserved, must be kept at reset value. Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO These bits are set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when PLLI2S is disabled.
Page 267: Rcc Register Map
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) 7.3.25 RCC register map Table 34 gives the register map and reset values. Table 34. RCC register map and reset values Addr. Register offset name 0x00 RCC_CR Reserved Reserved RCC_ 0x04 Reserved Reserved PLLCFGR...
Page 268 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) RM0090 Table 34. RCC register map and reset values (continued) Addr. Register offset name RCC_ 0x40 APB1ENR RCC_ 0x44 Reserved APB2ENR 0x48 Reserved Reserved 0x4C Reserved Reserved RCC_AHB1LP 0x50 RCC_AHB2LP 0x54 Reserved RCC_AHB3LP 0x58 Reserved...
Page 269: General-Purpose I/Os (Gpio)
RM0090 General-purpose I/Os (GPIO) General-purpose I/Os (GPIO) This section applies to the whole STM32F4xx family, unless otherwise specified. GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).
Page 270: Table 35. Port Bit Configuration Table
General-purpose I/Os (GPIO) RM0090 Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Page 271: General-Purpose I/O (Gpio)
RM0090 General-purpose I/Os (GPIO) Table 35. Port bit configuration table (continued) MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [B:A] [1:0] PP + PU PP + PD Reserved SPEED [B:A] OD + PU OD + PD Reserved Input Floating Input Input Reserved (input floating) Input/output Analog...
Page 272: I/O Pin Multiplexer And Mapping
General-purpose I/Os (GPIO) RM0090 8.3.2 I/O pin multiplexer and mapping The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:...
Page 273: Table 36. Flexible Swj-Dp Pin Assignment
RM0090 General-purpose I/Os (GPIO) Table 36. Flexible SWJ-DP pin assignment SWJ I/O pin assigned PA13 / PA14 / Available debug ports PA15 / PB3 / PB4/ JTMS/ JTCK/ JTDI JTDO NJTRST SWDIO SWCLK Full SWJ (JTAG-DP + SW-DP) - Reset state Full SWJ (JTAG-DP + SW-DP) but without NJTRST JTAG-DP Disabled and SW-DP Enabled...
Page 274: Figure 26. Selecting An Alternate Function On Stm32F405Xx/07Xx And Stm32F415Xx/17Xx
General-purpose I/Os (GPIO) RM0090 Figure 26. Selecting an alternate function on STM32F405xx/07xx and STM32F415xx/17xx 1. Configured in FS. 274/1731 DocID018909 Rev 11...
Page 275: Figure 27. Selecting An Alternate Function On Stm32F42Xxx And Stm32F43Xxx
RM0090 General-purpose I/Os (GPIO) Figure 27. Selecting an alternate function on STM32F42xxx and STM32F43xxx 1. Configured in FS. DocID018909 Rev 11 275/1731...
Page 276: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0090 8.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction).
Page 277: I/O Alternate Function Input/Output
RM0090 General-purpose I/Os (GPIO) freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH). The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..I/J/K)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
Page 278: Output Configuration
General-purpose I/Os (GPIO) RM0090 Figure 28. Input floating/pull up/pull down configurations 8.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 279: Alternate Function Configuration
RM0090 General-purpose I/Os (GPIO) Figure 29. Output configuration 8.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured as open-drain or push-pull • The output buffer is driven by the signal coming from the peripheral (transmitter enable and data) •...
Page 280: Analog Configuration
General-purpose I/Os (GPIO) RM0090 8.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 281: Selection Of Rtc_Af1 And Rtc_Af2 Alternate Functions
RM0090 General-purpose I/Os (GPIO) 8.3.15 Selection of RTC_AF1 and RTC_AF2 alternate functions The STM32F4xx feature two GPIO pins RTC_AF1 and RTC_AF2 that can be used for the detection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs. •...
Page 282: Table 38. Rtc_Af2 Pin
General-purpose I/Os (GPIO) RM0090 Table 38. RTC_AF2 pin TSINSEL Time TAMP1INSEL ALARMOUTTYPE Tamper TIMESTAMP Pin configuration and function stamp TAMPER1 RTC_ALARM enabled enabled pin selection configuration selection TAMPER1 input floating Don’t care Don’t care TIMESTAMP and TAMPER1 input Don’t care floating TIMESTAMP input floating Don’t care...
Page 283: Gpio Registers
RM0090 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..I/J/K) Address offset: 0x00...
Page 284: (X = A
General-purpose I/Os (GPIO) RM0090 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I/J/K) Address offset: 0x08 Reset values: • 0x0C00 0000 for port A • 0x0000 00C0 for port B • 0x0000 0000 for other ports OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12 OSPEEDR11 OSPEEDR10...
Page 285: Gpio Port Input Data Register (Gpiox_Idr) (X = A
RM0090 General-purpose I/Os (GPIO) Bits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I/J/K) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Reserved...
Page 286: Gpio Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A
General-purpose I/Os (GPIO) RM0090 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K) Address offset: 0x18 Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 BR10 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only and can be accessed in word, half-word or byte mode.
Page 287: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A
RM0090 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK[16]: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 288: (X = A
General-purpose I/Os (GPIO) RM0090 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..I/J) Address offset: 0x24 Reset value: 0x0000 0000 AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRHy selection: 0000: AF0...
Page 289 RM0090 General-purpose I/Os (GPIO) Table 39. GPIO register map and reset values (continued) Offset Register GPIOx_ OTYPER (where x = 0x04 Reserved A..I/J/K) Reset value GPIOx_ OSPEEDR (where x = 0x08 A..I/J/K except Reset value GPIOB_ OSPEEDR 0x08 Reset value GPIOA_PUPDR 0x0C Reset value...
Page 290 General-purpose I/Os (GPIO) RM0090 Table 39. GPIO register map and reset values (continued) Offset Register GPIOx_AFRH (where x = AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] 0x24 A..I/J) Reset value Refer to Section: Memory map for the register boundary addresses. 290/1731 DocID018909 Rev 11...
Page 291: System Configuration Controller (Syscfg)
RM0090 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area, select the Ethernet PHY interface and manage the external interrupt line connection to the GPIOs. This section applies to the whole STM32F4xx family, unless otherwise specified.
Page 292: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
System configuration controller (SYSCFG) RM0090 Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 MEM_MODE: Memory mapping selection Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins (except for FSMC).
Page 293: Syscfg External Interrupt Configuration Register 1
RM0090 System configuration controller (SYSCFG) 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 Reserved EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3) These bits are written by software to select the source input for the EXTIx external interrupt.
Page 294: Syscfg External Interrupt Configuration Register 3
System configuration controller (SYSCFG) RM0090 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 295: Compensation Cell Control Register (Syscfg_Cmpcr)
RM0090 System configuration controller (SYSCFG) 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 Reserved EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15) These bits are written by software to select the source input for the EXTIx external interrupt.
Page 296: Table 40. Syscfg Register Map And Reset Values (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx)
System configuration controller (SYSCFG) RM0090 9.2.8 SYSCFG register maps for STM32F405xx/07xx and STM32F415xx/17xx The following table gives the SYSCFG register map and the reset values. Table 40. SYSCFG register map and reset values (STM32F405xx/07xx and STM32F415xx/17xx) Offset Register SYSCFG_ MEMRMP 0x00 Reserved Reset value...
Page 297 RM0090 System configuration controller (SYSCFG) There are two possible FMC remap at address 0x0000 0000: • FMC Bank 1 (NOR/PSRAM 1 and 2) remap: Only the first two regions of Bank 1 memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. •...
Page 298: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
System configuration controller (SYSCFG) RM0090 Bit 8 FB_MODE: Flash Bank mode selection Set and cleared by software. This bit controls the Flash Bank 1/2 mapping. 0: Flash Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000) and Flash Bank 2 is mapped at 0x0810 0000 (and aliased at 0x0010 0000) 1: Flash Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000) and Flash Bank 1 is mapped at 0x0810 0000 (and aliased at 0x0010 0000)
Page 299: Syscfg External Interrupt Configuration Register
RM0090 System configuration controller (SYSCFG) Bits 22:19 Reserved, must be kept at reset value. Bits 18:16 ADCxDC2: 0: No effect. 1: Refer to AN4073 on how to use this bit. Note: These bits can be set only if the following conditions are met: - ADC clock higher or equal to 30 MHz.
Page 300: Syscfg External Interrupt Configuration Register
System configuration controller (SYSCFG) RM0090 9.3.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 0000 Reserved EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt.
Page 301 RM0090 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 302: Compensation Cell Control Register (Syscfg_Cmpcr)
System configuration controller (SYSCFG) RM0090 9.3.7 Compensation cell control register (SYSCFG_CMPCR) Address offset: 0x20 Reset value: 0x0000 0000 Reserved READY CMP_PD Reserved Reserved Bits 31:9 Reserved, must be kept at reset value. Bit 8 READY: Compensation cell ready flag 0: I/O compensation cell not ready 1: O compensation cell ready Bits 7:2 Reserved, must be kept at reset value.
Page 303: Table 41. Syscfg Register Map And Reset Values (Stm32F42Xxx And Stm32F43Xxx)
RM0090 System configuration controller (SYSCFG) 9.3.8 SYSCFG register maps for STM32F42xxx and STM32F43xxx The following table gives the SYSCFG register map and the reset values. Table 41. SYSCFG register map and reset values (STM32F42xxx and STM32F43xxx) Offset Register SYSCFG_ MEM_ MEMRMP MODE 0x00...
Page 304: Dma Introduction
DMA controller (DMA) RM0090 DMA controller (DMA) This section applies to the whole STM32F4xx family, unless otherwise specified. 10.1 DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action.
Page 305 RM0090 DMA controller (DMA) FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral. • Each stream can be configured by hardware to be: – a regular channel that supports peripheral-to-memory, memory-to-peripheral and memory-to-memory transfers –...
Page 306: Figure 32. Dma Block Diagram
DMA controller (DMA) RM0090 10.3 DMA functional description 10.3.1 General description Figure 32 shows the block diagram of a DMA. Figure 32. DMA block diagram DMA controller REQ_STR0_CH0 Memory port REQ_STR0_CH1 REQ_STR0_CH7 REQ_STR1_CH0 REQ_STR1_CH1 REQ_STREAM0 REQ_STREAM1 REQ_STR1_CH7 REQ_STREAM2 REQ_STREAM3 REQ_STREAM4 Arbiter REQ_STREAM5 REQ_STREAM6...
Page 307: Figure 33. System Implementation Of The Two Dma Controllers (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx )
RM0090 DMA controller (DMA) Figure 33. System implementation of the two DMA controllers (STM32F405xx/07xx and STM32F415xx/17xx ) 1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like DMA2 controller. As a result, only DMA2 streams are able to perform memory-to-memory transfers. DocID018909 Rev 11 307/1731...
Page 308: Figure 34. System Implementation Of The Two Dma Controllers (Stm32F42Xxx And Stm32F43Xxx)
DMA controller (DMA) RM0090 Figure 34. System implementation of the two DMA controllers (STM32F42xxx and STM32F43xxx) 1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus only DMA2 streams are able to perform memory-to-memory transfers. 10.3.2 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers.
Page 309: Table 42. Dma1 Request Mapping
RM0090 DMA controller (DMA) After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the DMA controller.
Page 310: Table 43. Dma2 Request Mapping
DMA controller (DMA) RM0090 Table 42. DMA1 request mapping (continued) Peripheral Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 requests TIM5_CH3 TIM5_CH4 TIM5_CH4 Channel 6 TIM5_CH1 TIM5_CH2 TIM5_UP TIM5_UP TIM5_TRIG TIM5_TRIG Channel 7 TIM6_UP I2C2_RX I2C2_RX...
Page 311: Table 44. Source And Destination Address
RM0090 DMA controller (DMA) 10.3.5 DMA streams Each of the 8 DMA controller streams provides a unidirectional transfer link between a source and a destination. Each stream can be configured to perform: • Regular type transactions: memory-to-peripherals, peripherals-to-memory or memory- to-memory transfers •...
Page 312: Figure 36. Peripheral-To-Memory Mode
DMA controller (DMA) RM0090 In direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, the corresponding data are immediately drained and stored into the destination. The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won.
Page 313: Figure 37. Memory-To-Peripheral Mode
RM0090 DMA controller (DMA) Figure 37. Memory-to-peripheral mode DMA_SxM0AR DMA controller DMA_SxM1AR Memory bus AHB memory port Memory source FIFO Arbiter level REQ_STREAMx FIFO AHB peripheral Peripheral bus port Peripheral destination DMA_SxPAR Peripheral DMA request ai15949 1. For double-buffer mode. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral.
Page 314: Figure 38. Memory-To-Memory Mode
DMA controller (DMA) RM0090 Figure 38. Memory-to-memory mode DMA_SxM0AR DMA controller DMA_SxM1AR AHB memory Memory bus port Memory 2 destination Arbiter FIFO FIFO level FIFO Stream enable AHB peripheral Peripheral bus port Memory 1 source DMA_SxPAR ai15950 1. For double-buffer mode. 10.3.7 Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented or kept...
Page 315: Circular Mode
RM0090 DMA controller (DMA) 10.3.8 Circular mode The Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.
Page 316: Table 45. Source And Destination Address Registers In Double Buffer Mode (Dbm=1)
DMA controller (DMA) RM0090 memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the Double buffer mode), the memory address registers are write-protected as soon as the stream is enabled.
Page 317: Table 46. Packing/Unpacking & Endian Behavior (Bit Pinc = Minc = 1)
RM0090 DMA controller (DMA) Table 46. Packing/unpacking & endian behavior (bit PINC = MINC = 1) Number Peripheral port address / byte lane Peripher of data Memory Memory port memory peripheral items to transfer address / byte port transfer PINCOS = 1 PINCOS = 0 port width transfer...
Page 318: Table 47. Restriction On Ndt Versus Psize And Msize
DMA controller (DMA) RM0090 Table 47. Restriction on NDT versus PSIZE and MSIZE PSIZE[1:0] of DMA_SxCR MSIZE[1:0] of DMA_SxCR NDT[15:0] of DMA_SxNDTR 00 (8-bit) 01 (16-bit) must be a multiple of 2 00 (8-bit) 10 (32-bit) must be a multiple of 4 01 (16-bit) 10 (32-bit) must be a multiple of 2...
Page 319: Figure 39. Fifo Structure
RM0090 DMA controller (DMA) 10.3.12 FIFO FIFO structure The FIFO is used to temporarily store data coming from the source before transmitting them to the destination. Each stream has an independent 4-word FIFO and the threshold level is software- configurable between 1/4, 1/2, 3/4 or full. To enable the use of the FIFO threshold level, the direct mode must be disabled by setting the DMDIS bit in the DMA_SxFCR register.
Page 320: Table 48. Fifo Threshold Configurations
DMA controller (DMA) RM0090 Table 48: FIFO threshold configurations. Table 48. FIFO threshold configurations MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16 1 burst of 4 beats forbidden 2 bursts of 4 beats 1 burst of 8 beats forbidden Byte 3 bursts of 4 beats...
Page 321: Dma Transfer Completion
RM0090 DMA controller (DMA) FIFO flush The FIFO can be flushed when the stream is disabled by resetting the EN bit in the DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers: If some data are still present in the FIFO when the stream is disabled, the DMA controller continues transferring the remaining data to the destination (even though stream is effectively disabled).
Page 322: Dma Transfer Suspension
DMA controller (DMA) RM0090 to-memory) all the remaining data have been flushed from the FIFO into the memory • In Peripheral flow controller mode: – The last external burst or single request has been generated from the peripheral and (when the DMA is operating in peripheral-to-memory mode) the remaining data have been transferred from the FIFO into the memory –...
Page 323: Flow Controller
RM0090 DMA controller (DMA) 10.3.15 Flow controller The entity that controls the number of data to be transferred is known as the flow controller. This flow controller is configured independently for each stream using the PFCTRL bit in the DMA_SxCR register. The flow controller can be: •...
Page 324: Table 49. Possible Dma Configurations
DMA controller (DMA) RM0090 10.3.16 Summary of the possible DMA configurations Table 49 summarizes the different possible DMA configurations. Table 49. Possible DMA configurations DMA transfer Flow Circular Transfer Direct Double Source Destination mode controller mode type mode buffer mode single possible possible...
Page 325: Error Management
RM0090 DMA controller (DMA) Double buffer mode and interrupts after half and/or full transfer, and/or errors in the DMA_SxCR register. 10. Activate the stream by setting the EN bit in the DMA_SxCR register. As soon as the stream is enabled, it can serve any DMA request from the peripheral connected to the stream.
Page 326: Table 50. Dma Interrupt Requests
DMA controller (DMA) RM0090 If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register.
Page 327: Dma Registers
RM0090 DMA controller (DMA) 10.5 DMA registers The DMA registers have to be accessed by words (32 bits). 10.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved TCIF3 HTIF3 TEIF3 DMEIF3 Reserv FEIF3 TCIF2 HTIF2 TEIF2 DMEIF2 Reserv...
Page 328: Dma High Interrupt Status Register (Dma_Hisr)
DMA controller (DMA) RM0090 10.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x04 Reset value: 0x0000 0000 TCIF7 HTIF7 TEIF7 DMEIF7 Reserv FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Reserv FEIF6 Reserved TCIF5 HTIF5 TEIF5 DMEIF5 Reserv FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4 Reserv FEIF4 Reserved...
Page 329: Dma Low Interrupt Flag Clear Register (Dma_Lifcr)
RM0090 DMA controller (DMA) 10.5.3 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x08 Reset value: 0x0000 0000 CTCIF3 CHTIF3 CTEIF3 CDMEIF3 CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 CFEIF2 Reserved Reserved Reserved CTCIF1 CHTIF1 CTEIF1 CDMEIF1 CFEIF1 CTCIF0 CHTIF0 CTEIF0 CDMEIF0 CFEIF0 Reserved Reserved...
Page 330: Dma Stream X Configuration Register (Dma_Sxcr) (X = 0..7)
DMA controller (DMA) RM0090 Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register 10.5.5...
Page 331 RM0090 DMA controller (DMA) Bit 20 Reserved, must be kept at reset value. Bit 19 CT: Current target (only in double buffer mode) This bits is set and cleared by hardware. It can also be written by software. 0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) 1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) This bit can be written only if EN is ‘0’...
Page 332 DMA controller (DMA) RM0090 Bit 9 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral address pointer is fixed 1: Peripheral address pointer is incremented after each data transfer (increment is done according to PSIZE) This bit is protected and can be written only if EN is ‘0’.
Page 333: Dma Stream X Number Of Data Register (Dma_Sxndtr) (X = 0..7)
RM0090 DMA controller (DMA) Bit 0 EN: Stream enable / flag stream ready when read low This bit is set and cleared by software. 0: Stream disabled 1: Stream enabled This bit may be cleared by hardware: – on a DMA end of transfer (stream ready to be configured) –...
Page 334: Dma Stream X Peripheral Address Register (Dma_Sxpar) (X = 0..7)
DMA controller (DMA) RM0090 10.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) Address offset: 0x18 + 0x18 × stream number Reset value: 0x0000 0000 PAR[31:16] PAR[15:0] Bits 31:0 PAR[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
Page 335: Dma Stream X Fifo Control Register (Dma_Sxfcr) (X = 0..7)
RM0090 DMA controller (DMA) Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode) Base address of Memory area 1 from/to which the data will be read/written. This register is used only for the Double buffer mode. These bits are write-protected.
Page 336 DMA controller (DMA) RM0090 Bits 5:3 FS[2:0]: FIFO status These bits are read-only. 000: 0 < fifo_level < 1/4 001: 1/4 ≤ fifo_level < 1/2 010: 1/2 ≤ fifo_level < 3/4 011: 3/4 ≤ fifo_level < full 100: FIFO is empty 101: FIFO is full others: no meaning These bits are not relevant in the direct mode (DMDIS bit is zero).
Page 337: Table 51. Dma Register Map And Reset Values
RM0090 DMA controller (DMA) 10.5.11 DMA register map Table 51 summarizes the DMA registers. Table 51. DMA register map and reset values Offset Register DMA_LISR 0x0000 Reserved Reserved Reset value DMA_HISR 0x0004 Reserved Reserved Reset value DMA_LIFCR 0x0008 Reserved Reserved Reset value DMA_HIFCR 0x000C...
Page 338 DMA controller (DMA) RM0090 Table 51. DMA register map and reset values (continued) Offset Register DMA_S1PAR PA[31:0] 0x0030 Reset value DMA_S1M0AR M0A[31:0] 0x0034 Reset value DMA_S1M1AR M1A[31:0] 0x0038 Reset value DMA_S1FCR FS[2:0] [1:0] 0x003C Reserved Reset value DMA_S2CR 0x0040 Reserved Reset value DMA_S2NDTR NDT[15:.]...
Page 339 RM0090 DMA controller (DMA) Table 51. DMA register map and reset values (continued) Offset Register DMA_S3M1AR M1A[31:0] 0x0068 Reset value DMA_S3FCR FS[2:0] [1:0] 0x006C Reserved Reset value DMA_S4CR 0x0070 Reserved Reset value DMA_S4NDTR NDT[15:.] 0x0074 Reserved Reset value DMA_S4PAR PA[31:0] 0x0078 Reset value DMA_S4M0AR...
Page 340 DMA controller (DMA) RM0090 Table 51. DMA register map and reset values (continued) Offset Register DMA_S6M0AR M0A[31:0] 0x00AC Reset value DMA_S6M1AR M1A[31:0] 0x00B0 Reset value DMA_S6FCR FS[2:0] [1:0] 0x00B4 Reserved Reset value DMA_S7CR 0x00B8 Reserved Reset value DMA_S7NDTR NDT[15:.] 0x00BC Reserved Reset value DMA_S7PAR...
Page 341: Dma2D Introduction
RM0090 Chrom-Art Accelerator™ controller (DMA2D) Chrom-Art Accelerator™ controller (DMA2D) 11.1 DMA2D introduction The Chrom-Art Accelerator™ (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations: • Filling a part or the whole of a destination image with a specific color •...
Page 342: Dma2D Main Features
Chrom-Art Accelerator™ controller (DMA2D) RM0090 11.2 DMA2D main features The main DMA2D features are: • Single AHB master bus architecture. • AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT accesses which are 32-bit). • User programmable working area size •...
Page 343: Dma2D Control
RM0090 Chrom-Art Accelerator™ controller (DMA2D) Figure 40. DMA2D block diagram 11.3.2 DMA2D control The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR) which allows selecting: The user application can perform the following operations: • Select the operating mode •...
Page 344: Table 52. Supported Color Mode In Input
Chrom-Art Accelerator™ controller (DMA2D) RM0090 They are programmed through a set of control registers: • DMA2D foreground memory address register (DMA2D_FGMAR) • DMA2D foreground offset register (DMA2D_FGOR) • DMA2D background memory address register (DMA2D_BGMAR) • DMA2D background offset register (DMA2D_BGBOR) •...
Page 345: Table 53. Data Order In Memory
RM0090 Chrom-Art Accelerator™ controller (DMA2D) The color format are coded as follows: • Alpha value field: transparency 0xFF value corresponds to an opaque pixel and 0x00 to a transparent one. • R field for Red • G field for Green •...
Page 346: Dma2D Foreground And Background Clut Interface
Chrom-Art Accelerator™ controller (DMA2D) RM0090 The alpha channel can be: • kept as it is (no modification), • replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR, • or replaced by the original alpha value multiplied by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255. Table 54.
Page 347: Table 56. Clut Data Order In Memory
RM0090 Chrom-Art Accelerator™ controller (DMA2D) Table 55. Supported CLUT color mode CLUT color mode 32-bit ARGB8888 24-bit RGB888 The way the CLUT data are organized in the system memory is specified in Table 56: CLUT data order in memory. Table 56. CLUT data order in memory CLUT Color Mode @ + 3 @ + 2...
Page 348: Table 57. Supported Color Mode In Output
Chrom-Art Accelerator™ controller (DMA2D) RM0090 Table 57. Supported color mode in output CM[2:0] Color mode ARGB8888 RGB888 RGB565 ARGB1555 ARGB4444 11.3.8 DMA2D output FIFO The output FIFO programs the pixels according to the color format defined in the output PFC. The destination area is defined through a set of control registers: •...
Page 349: Dma2D Transactions
RM0090 Chrom-Art Accelerator™ controller (DMA2D) The timer enabling and the dead time value are configured through the AHB master port timer configuration register (DMA2D_AMPTCR). 11.3.10 DMA2D transactions DMA2D transactions consist of a sequence of a given number of data transfers. The number of data and the width can be programmed by software.
Page 350 Chrom-Art Accelerator™ controller (DMA2D) RM0090 The size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination. Memory-to-memory with PFC In this mode, the DMA2D performs a pixel format conversion of the source data and stores them in the destination memory location.
Page 351 RM0090 Chrom-Art Accelerator™ controller (DMA2D) Memory-to-memory with PFC and blending In this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR. The two pixel format converters have to be configured as described in the memory-to- memory mode.
Page 352: Dma2D Transfer Control (Start, Suspend, Abort And Completion)
Chrom-Art Accelerator™ controller (DMA2D) RM0090 The wrong configurations that can be detected are listed below: • Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR not aligned with CCM of DMA2D_FGPFCCR. • Background CLUT automatic loading: MA of DMA2D_BGCMAR not aligned with CCM of DMA2D_BGPFCCR •...
Page 353: Table 59. Dma2D Interrupt Requests
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.3.13 Watermark A watermark can be programmed to generate an interrupt when the last pixel of a given line has been written to the destination memory area. The line number is defined in the LW[15:0] field of the DMA2D_LWR register. When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.
Page 354: Dma2D Registers
Chrom-Art Accelerator™ controller (DMA2D) RM0090 Table 59. DMA2D interrupt requests (continued) Interrupt event Event flag Enable control bit CLUT access error CAEIF CAEIE Transfer watermark TWIE Transfer complete TCIF TCIE Transfer error TEIF TEIE 11.5 DMA2D registers 11.5.1 DMA2D control register (DMA2D_CR) Address offset: 0x0000 Reset value: 0x0000 0000 MODE...
Page 355 RM0090 Chrom-Art Accelerator™ controller (DMA2D) Bit 10 TWIE: Transfer watermark interrupt enable This bit is set and cleared by software. 0: TW interrupt disable 1: TW interrupt enable Bit 9 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disable 1: TC interrupt enable Bit 8 TEIE: Transfer error interrupt enable...
Page 356: Dma2D Interrupt Status Register (Dma2D_Isr)
Chrom-Art Accelerator™ controller (DMA2D) RM0090 11.5.2 DMA2D Interrupt Status Register (DMA2D_ISR) Address offset: 0x0004 Reset value: 0x0000 0000 Reserved CEIF CTCIF CAEIF TWIF TCIF TEIF Reserved Bits 31:6 Reserved, must be kept at reset value Bit 5 CEIF: Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed.
Page 357: Dma2D Interrupt Flag Clear Register (Dma2D_Ifcr)
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) Address offset: 0x0008 Reset value: 0x0000 0000 Reserved CCEIF CCTCIF CAECIF CTWIF CTCIF CTEIF Reserved rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:6 Reserved, must be kept at reset value Bit 5 CCEIF: Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag...
Page 358: Dma2D Foreground Memory Address Register (Dma2D_Fgmar)
Chrom-Art Accelerator™ controller (DMA2D) RM0090 11.5.4 DMA2D foreground memory address register (DMA2D_FGMAR) Address offset: 0x000C Reset value: 0x0000 0000 MA[31:16] MA[15:0] Bits 31:0 MA[31: 0]: Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled.
Page 359: Dma2D Background Memory Address Register (Dma2D_Bgmar)
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.5.6 DMA2D background memory address register (DMA2D_BGMAR) Address offset: 0x0014 Reset value: 0x0000 0000 MA[31:16] MA[15:0] Bits 31: 0 MA[31: 0]: Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled.
Page 360 Chrom-Art Accelerator™ controller (DMA2D) RM0090 ALPHA[7:0] AM[1:0] Reserved CS[7:0] START CM[3:0] Reserved rc_w1 Bits 31:24 ALPHA[7: 0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits.
Page 361 RM0090 Chrom-Art Accelerator™ controller (DMA2D) Bit 5 START: Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR –...
Page 362: Dma2D Foreground Color Register (Dma2D_Fgcolr)
Chrom-Art Accelerator™ controller (DMA2D) RM0090 11.5.9 DMA2D foreground color register (DMA2D_FGCOLR) Address offset: 0x0020 Reset value: 0x0000 0000 RED[7:0] Reserved GREEN[7:0] BLUE[7:0] Bits 31:24 Reserved, must be kept at reset value Bits 23:16 RED[7: 0]: Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled.
Page 363: Dma2D Background Pfc Control Register (Dma2D_Bgpfccr)
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) Address offset: 0x0024 Reset value: 0x0000 0000 ALPHA[7:0] AM[1:0] Reserved CS[7:0] START CM[3:0] Reserved rc_w1 Bits 31:24 ALPHA[7: 0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0].
Page 364 Chrom-Art Accelerator™ controller (DMA2D) RM0090 Bit 5 START: Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR –...
Page 365: Dma2D Background Color Register (Dma2D_Bgcolr)
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.5.11 DMA2D background color register (DMA2D_BGCOLR) Address offset: 0x0028 Reset value: 0x0000 0000 RED[7:0] Reserved GREEN[7:0] BLUE[7:0] Bits 31:24 Reserved, must be kept at reset value Bits 23:16 RED[7: 0]: Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled.
Page 366: Dma2D Output Pfc Control Register (Dma2D_Opfccr)
Chrom-Art Accelerator™ controller (DMA2D) RM0090 11.5.13 DMA2D background CLUT memory address register (DMA2D_BGCMAR) Address offset: 0x0030 Reset value: 0x0000 0000 MA[31:16] MA[15:0] Bits 31: 0 MA[31: 0]: Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going.
Page 367: Dma2D Output Color Register (Dma2D_Ocolr)
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.5.15 DMA2D output color register (DMA2D_OCOLR) Address offset: 0x0038 Reset value: 0x0000 0000 ALPHA[7:0] RED[7:0] GREEN[7:0] BLUE[7:0] RED[4:0] GREEN[5:0] BLUE[4:0] RED[4:0] GREEN[4:0] BLUE[4:0] ALPHA[3:0] RED[3:0] GREEN[3:0] BLUE[3:0] Bits 31:24 ALPHA[7: 0]: Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled.
Page 368: Dma2D Output Memory Address Register (Dma2D_Omar)
Chrom-Art Accelerator™ controller (DMA2D) RM0090 11.5.16 DMA2D output memory address register (DMA2D_OMAR) Address offset: 0x003C Reset value: 0x0000 0000 MA[31:16] MA[15:0] Bits 31: 0 MA[31: 0]: Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled.
Page 369: Dma2D Output Offset Register (Dma2D_Oor)
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.5.17 DMA2D output offset register (DMA2D_OOR) Address offset: 0x0040 Reset value: 0x0000 0000 Reserved LO[13:0] Reserved Bits 31:14 Reserved, must be kept at reset value Bits 13:0 LO[13: 0]: Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation.
Page 370: Dma2D Line Watermark Register (Dma2D_Lwr)
Chrom-Art Accelerator™ controller (DMA2D) RM0090 11.5.19 DMA2D line watermark register (DMA2D_LWR) Address offset: 0x0048 Reset value: 0x0000 0000 Reserved LW[15:0] Bits 31:16 Reserved, must be kept at reset value Bits 15:0 LW[15:0]: Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred.
Page 371: Table 60. Dma2D Register Map And Reset Values
RM0090 Chrom-Art Accelerator™ controller (DMA2D) 11.5.21 DMA2D register map The following table summarizes the DMA2D registers. Refer to Section: Memory map for the DMA2D register base address. Table 60. DMA2D register map and reset values Offset Register DMA2D_CR 0x0000 Reserved Reserved Reserved Reset value...
Page 372 Chrom-Art Accelerator™ controller (DMA2D) RM0090 Table 60. DMA2D register map and reset values (continued) Offset Register DMA2D_OOR LO[13:0] 0x0040 Reserved Reset value DMA2D_NLR PL[13:0] NL[15:0] 0x0044 Reset value DMA2D_LWR LW[15:0] 0x0048 Reserved Reset value DMA2D_AMTCR DT[7:0] 0x004C Reserved Reserved Reset value 0x0050- Reserved Ox03FF...
Page 373: Nested Vectored Interrupt Controller (Nvic)
RM0090 Interrupts and events Interrupts and events This Section applies to the whole STM32F4xx family, unless otherwise specified. 12.1 Nested vectored interrupt controller (NVIC) 12.1.1 NVIC features The nested vector interrupt controller NVIC includes the following features: • 82 maskable interrupt channels for STM32F405xx/07xx and STM32F415xx/17xx, and up to 91 maskable interrupt channels for STM32F42xxx and STM32F43xxx (not ®...
Page 374: Table 61. Vector Table For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx
Interrupts and events RM0090 Table 61. Vector table for STM32F405xx/07xx and STM32F415xx/17xx Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 Non maskable interrupt. The RCC fixed Clock Security System (CSS) is linked 0x0000 0008 to the NMI vector.
Page 375 RM0090 Interrupts and events Table 61. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued) Type of Acronym Description Address priority settable DMA1_Stream1 DMA1 Stream1 global interrupt 0x0000 0070 settable DMA1_Stream2 DMA1 Stream2 global interrupt 0x0000 0074 settable DMA1_Stream3 DMA1 Stream3 global interrupt 0x0000 0078 settable DMA1_Stream4...
Page 376 Interrupts and events RM0090 Table 61. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued) Type of Acronym Description Address priority settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0 RTC Alarms (A and B) through EXTI settable RTC_Alarm 0x0000 00E4 line interrupt USB On-The-Go FS Wakeup through settable OTG_FS WKUP 0x0000 00E8...
Page 377: Table 62. Vector Table For Stm32F42Xxx And Stm32F43Xxx
RM0090 Interrupts and events Table 61. Vector table for STM32F405xx/07xx and STM32F415xx/17xx (continued) Type of Acronym Description Address priority settable CAN2_RX1 CAN2 RX1 interrupt 0x0000 0144 settable CAN2_SCE CAN2 SCE interrupt 0x0000 0148 settable OTG_FS USB On The Go FS global interrupt 0x0000 014C settable DMA2_Stream5...
Page 378 Interrupts and events RM0090 Table 62. Vector table for STM32F42xxx and STM32F43xxx (continued) Type of Acronym Description Address priority fixed HardFault All class of fault 0x0000 000C settable MemManage Memory management 0x0000 0010 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014 settable UsageFault...
Page 379 RM0090 Interrupts and events Table 62. Vector table for STM32F42xxx and STM32F43xxx (continued) Type of Acronym Description Address priority settable ADC1, ADC2 and ADC3 global interrupts 0x0000 0088 settable CAN1_TX CAN1 TX interrupts 0x0000 008C settable CAN1_RX0 CAN1 RX0 interrupts 0x0000 0090 settable CAN1_RX1...
Page 380 Interrupts and events RM0090 Table 62. Vector table for STM32F42xxx and STM32F43xxx (continued) Type of Acronym Description Address priority TIM8 Update interrupt and TIM13 global settable TIM8_UP_TIM13 0x0000 00F0 interrupt TIM8_TRG_COM_TIM1 TIM8 Trigger and Commutation interrupts settable 0x0000 00F4 and TIM14 global interrupt settable TIM8_CC TIM8 Capture Compare interrupt...
Page 381: Exti Main Features
RM0090 Interrupts and events Table 62. Vector table for STM32F42xxx and STM32F43xxx (continued) Type of Acronym Description Address priority settable I2C3_EV C3 event interrupt 0x0000 0160 settable I2C3_ER C3 error interrupt 0x0000 0164 USB On The Go HS End Point 1 Out global settable OTG_HS_EP1_OUT 0x0000 0168...
Page 382: Figure 41. External Interrupt/Event Controller Block Diagram
Interrupts and events RM0090 12.2.2 EXTI block diagram Figure 41 shows the block diagram. Figure 41. External interrupt/event controller block diagram 12.2.3 Wakeup event management The STM32F4xx are able to handle external or internal events in order to wake up the core (WFE).
Page 383 RM0090 Interrupts and events generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’...
Page 384: Figure 42. External Interrupt/Event Gpio Mapping (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx)
Interrupts and events RM0090 12.2.5 External interrupt/event line mapping Up to 140 GPIOs (STM32F405xx/07xx and STM32F415xx/17xx), 168 GPIOs (STM32F42xxx and STM32F43xxx) are connected to the 16 external interrupt/event lines in the following manner: Figure 42. External interrupt/event GPIO mapping (STM32F405xx/07xx and STM32F415xx/17xx) 384/1731 DocID018909 Rev 11...
Page 385: Figure 43. External Interrupt/Event Gpio Mapping (Stm32F42Xxx And Stm32F43Xxx)
RM0090 Interrupts and events Figure 43. External interrupt/event GPIO mapping (STM32F42xxx and STM32F43xxx) The seven other EXTI lines are connected as follows: • EXTI line 16 is connected to the PVD output • EXTI line 17 is connected to the RTC Alarm event •...
Page 386: Interrupt Mask Register (Exti_Imr)
Interrupts and events RM0090 12.3 registers EXTI Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. 12.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 MR22 MR21 MR20 MR19 MR18 MR17...
Page 387: Rising Trigger Selection Register (Exti_Rtsr)
RM0090 Interrupts and events 12.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 TR22 TR21 TR20 TR19 TR18 TR17 TR16 Reserved TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line...
Page 388: Software Interrupt Event Register (Exti_Swier)
Interrupts and events RM0090 12.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER SWIER SWIER SWIER Reserved SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:23 Reserved, must be kept at reset value.
Page 389: Table 63. External Interrupt/Event Controller Register Map And Reset Values
RM0090 Interrupts and events 12.3.7 EXTI register map Table 64 gives the EXTI register map and the reset values. Table 63. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[22:0] 0x00 Reserved Reset value EXTI_EMR MR[22:0] 0x04 Reserved Reset value EXTI_RTSR...
Page 390: Adc Introduction
Analog-to-digital converter (ADC) RM0090 Analog-to-digital converter (ADC) This section applies to the whole STM32F4xx family, unless otherwise specified. 13.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V channel.
Page 391: Adc Functional Description
RM0090 Analog-to-digital converter (ADC) 13.3 ADC functional description Figure 44 shows a single ADC block diagram and Table 65 gives the ADC pin description. DocID018909 Rev 11 391/1731...
Page 392: Figure 44. Single Adc Block Diagram
Analog-to-digital converter (ADC) RM0090 Figure 44. Single ADC block diagram 392/1731 DocID018909 Rev 11...
Page 393: Table 65. Adc Pins
RM0090 Analog-to-digital converter (ADC) Table 65. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ ≤ ≤ positive 1.8 V REF+ Analog power supply equal to V ≤ ≤ Input, analog supply 2.4 V (3.6 V) for full speed ≤...
Page 394: Single Conversion Mode
Analog-to-digital converter (ADC) RM0090 The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.
Page 395: Figure 45. Timing Diagram
RM0090 Analog-to-digital converter (ADC) 13.3.5 Continuous conversion mode In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one. This mode is started with the CONT bit at 1 either by external trigger or by setting the SWSTRT bit in the ADC_CR2 register (for regular channels only).
Page 396: Table 66. Analog Watchdog Channel Selection
Analog-to-digital converter (ADC) RM0090 Figure 46. Analog watchdog’s guarded area Table 66. Analog watchdog channel selection ADC_CR1 register control bits (x = don’t care) Channels guarded by the analog watchdog AWDSGL bit AWDEN bit JAWDEN bit None All injected channels All regular channels All regular and injected channels Single...
Page 397: Figure 47. Injected Conversion Latency
RM0090 Analog-to-digital converter (ADC) 13.3.9 Injected channel management Triggered injection To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register. Start the conversion of a group of regular channels either by external trigger or by setting the SWSTART bit in the ADC_CR2 register. If an external injected trigger occurs or if the JSWSTART bit is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches to Scan-once mode.
Page 398: Discontinuous Mode
Analog-to-digital converter (ADC) RM0090 13.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADC_SQRx registers.
Page 399: Figure 48. Right Alignment Of 12-Bit Data
RM0090 Analog-to-digital converter (ADC) 13.4 Data alignment The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 48 Figure The converted data value from the injected group of channels is decreased by the user- defined offset written in the ADC_JOFRx registers so the result can be a negative value.
Page 400: Table 67. Configuring The Trigger Polarity
Analog-to-digital converter (ADC) RM0090 13.5 Channel-wise programmable sampling time The ADC samples the input voltage for a number of ADCCLK cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sampling time. The total conversion time is calculated as follows: = Sampling time + 12 cycles conv...
Page 401: Table 68. External Trigger For Regular Channels
RM0090 Analog-to-digital converter (ADC) Table 68. External trigger for regular channels Source Type EXTSEL[3:0] TIM1_CH1 event 0000 TIM1_CH2 event 0001 TIM1_CH3 event 0010 TIM2_CH2 event 0011 TIM2_CH3 event 0100 TIM2_CH4 event 0101 TIM2_TRGO event 0110 Internal signal from on-chip TIM3_CH1 event 0111 timers TIM3_TRGO event...
Page 402: Table 69. External Trigger For Injected Channels
Analog-to-digital converter (ADC) RM0090 Table 69. External trigger for injected channels Source Connection type JEXTSEL[3:0] TIM1_CH4 event 0000 TIM1_TRGO event 0001 TIM2_CH1 event 0010 TIM2_TRGO event 0011 TIM3_CH2 event 0100 TIM3_CH4 event 0101 TIM4_CH1 event 0110 Internal signal from on-chip TIM4_CH2 event 0111 timers...
Page 403: Data Management
RM0090 Analog-to-digital converter (ADC) 13.8 Data management 13.8.1 Using the DMA Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.
Page 404: Conversions Without Dma And Without Overrun Detection
Analog-to-digital converter (ADC) RM0090 13.8.3 Conversions without DMA and without overrun detection It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled (DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0).
Page 405: Figure 51. Multi Adc Block Diagram (1)
RM0090 Analog-to-digital converter (ADC) Figure 51. Multi ADC block diagram 1. Although external triggers are present on ADC2 and ADC3 they are not shown in this diagram. 2. In the Dual ADC mode, the ADC3 slave part is not present. 3.
Page 406 Analog-to-digital converter (ADC) RM0090 • DMA requests in Multi ADC mode: In Multi ADC mode the DMA may be configured to transfer converted data in three different modes. In all cases, the DMA streams to use are those connected to the ADC: –...
Page 407: Injected Simultaneous Mode
RM0090 Analog-to-digital converter (ADC) – DMA mode 3: This mode is similar to the DMA mode 2. The only differences are that the on each DMA request (two data items are available) two bytes representing two ADC converted data items are transferred as a half-word. The data transfer order is similar to that of the DMA mode 2.
Page 408: Figure 52. Injected Simultaneous Mode On 4 Channels: Dual Adc Mode
Analog-to-digital converter (ADC) RM0090 Dual ADC mode At the end of conversion event on ADC1 or ADC2: • The converted data are stored into the ADC_JDRx registers of each ADC interface. • A JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the ADC1/ADC2’s injected channels have all been converted.
Page 409: Figure 54. Regular Simultaneous Mode On 16 Channels: Dual Adc Mode
RM0090 Analog-to-digital converter (ADC) Dual ADC mode At the end of conversion event on ADC1 or ADC2: • A 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register are equal to 0b10). This request transfers the ADC2 converted data stored in the upper half-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted data stored in the lower half-word of ADC_CCR to the SRAM.
Page 410: Figure 56. Interleaved Mode On 1 Channel In Continuous Conversion Mode: Dual Adc Mode
Analog-to-digital converter (ADC) RM0090 13.9.3 Interleaved mode This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of ADC1. Dual ADC mode After an external trigger occurs: •...
Page 411: Figure 57. Interleaved Mode On 1 Channel In Continuous Conversion Mode: Triple Adc Mode
RM0090 Analog-to-digital converter (ADC) a given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For instance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on the three ADCs, then 17 clock cycles will separate the conversions on ADC1, ADC2 and ADC3). If the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs are continuously converted.
Page 412: Figure 58. Alternate Trigger: Injected Group Of Each Adc
Analog-to-digital converter (ADC) RM0090 ADC has to perform an injected conversion. It is resumed when the injected conversion is finished. If the conversion sequence is interrupted (for instance when DMA end of transfer occurs), the multi-ADC sequencer must be reset by configuring it in independent mode first (bits DUAL[4:0] = 00000) before reprogramming the interleaved mode.
Page 413: Figure 59. Alternate Trigger: 4 Injected Channels (Each Adc) In Discontinuous Mode
RM0090 Analog-to-digital converter (ADC) Figure 59. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode Triple ADC mode • When the 1st trigger occurs, all injected ADC1 channels in the group are converted. • When the 2nd trigger occurs, all injected ADC2 channels in the group are converted. •...
Page 414: Figure 61. Alternate + Regular Simultaneous
Analog-to-digital converter (ADC) RM0090 ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. 13.9.6 Combined regular simultaneous + alternate trigger mode It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group.
Page 415: Figure 62. Case Of Trigger Occurring During Injected Conversion
RM0090 Analog-to-digital converter (ADC) Figure 62. Case of trigger occurring during injected conversion 13.10 Temperature sensor The temperature sensor can be used to measure the ambient temperature (T ) of the device. • On STM32F40x and STM32F41x devices, the temperature sensor is internally connected to ADC1_IN16 channel which is used to convert the sensor output voltage to a digital value.
Page 416: Figure 63. Temperature Sensor And Vrefint Channel Block Diagram
Analog-to-digital converter (ADC) RM0090 Figure 63. Temperature sensor and V channel block diagram REFINT 1. V is input to ADC1_IN16 for the STM23F40x and STM32F41x devices and to ADC1_IN18 for the SENSE STM32F42x and STM32F43x devices. Reading the temperature To use the sensor: Select ADC1_IN16 or ADC1_IN18 input channel.
Page 417: Table 70. Adc Interrupts
RM0090 Analog-to-digital converter (ADC) The internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. If accurate temperature reading is required, an external temperature sensor should be used. 13.11 Battery charge monitoring The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the voltage could be higher than V , to ensure the correct operation of the ADC, the pin is internally connected to a bridge divider.
Page 418: Adc Registers
Analog-to-digital converter (ADC) RM0090 13.13 ADC registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 419: Adc Control Register 1 (Adc_Cr1)
RM0090 Analog-to-digital converter (ADC) 13.13.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 OVRIE AWDEN JAWDEN Reserved Reserved JDISCE DISC AWDSG DISCNUM[2:0] JAUTO SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Bits 31:27 Reserved, must be kept at reset value. Bit 26 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt.
Page 420 Analog-to-digital converter (ADC) RM0090 Bit 11 DISCEN: Discontinuous mode on regular channels This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
Page 421: Adc Control Register 2 (Adc_Cr2)
RM0090 Analog-to-digital converter (ADC) 13.13.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 SWST JSWST EXTEN EXTSEL[3:0] JEXTEN JEXTSEL[3:0] reserved reserved ALIGN EOCS CONT ADON reserved Reserved Bit 31 Reserved, must be kept at reset value. Bit 30 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.
Page 422 Analog-to-digital converter (ADC) RM0090 Bit 22 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by hardware as soon as the conversion starts. 0: Reset state 1: Starts conversion of injected channels Note: This bit can be set only when ADON = 1 otherwise no conversion is launched. Bits 21:20 JEXTEN: External trigger enable for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.
Page 423: Adc Sample Time Register 1 (Adc_Smpr1)
RM0090 Analog-to-digital converter (ADC) Bits 7:2 Reserved, must be kept at reset value. Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D Converter ON / OFF This bit is set and cleared by software.
Page 424: Adc Injected Channel Data Offset Register X (Adc_Jofrx) (X=1..4)
Analog-to-digital converter (ADC) RM0090 Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: 000: 3 cycles 001: 15 cycles 010: 28 cycles...
Page 425: Adc Watchdog Lower Threshold Register (Adc_Ltr)
RM0090 Analog-to-digital converter (ADC) 13.13.8 ADC watchdog lower threshold register (ADC_LTR) Address offset: 0x28 Reset value: 0x0000 0000 Reserved LT[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 LT[11:0]: Analog watchdog lower threshold These bits are written by software to define the lower threshold for the analog watchdog. 13.13.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C...
Page 426: Adc Regular Sequence Register 2 (Adc_Sqr2)
Analog-to-digital converter (ADC) RM0090 13.13.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 SQ12[4:0] SQ11[4:0] SQ10[4:1] Reserved SQ10_0 SQ9[4:0] SQ8[4:0] SQ7[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 12th in...
Page 427: Adc Injected Sequence Register (Adc_Jsqr)
RM0090 Analog-to-digital converter (ADC) 13.13.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 JL[1:0] JSQ4[4:1] Reserved JSQ4[0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 428: Adc Regular Data Register (Adc_Dr)
Analog-to-digital converter (ADC) RM0090 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 48 Figure 13.13.14 ADC regular data register (ADC_DR)
Page 429: Adc Common Control Register (Adc_Ccr)
RM0090 Analog-to-digital converter (ADC) Bit 19 JSTRT3: Injected channel Start flag of ADC3 This bit is a copy of the JSTRT bit in the ADC3_SR register. Bit 18 JEOC3: Injected channel end of conversion of ADC3 This bit is a copy of the JEOC bit in the ADC3_SR register. Bit 17 EOC3: End of conversion of ADC3 This bit is a copy of the EOC bit in the ADC3_SR register.
Page 430 Analog-to-digital converter (ADC) RM0090 TSVREFE VBATE ADCPRE Reserved Reserved DMA[1:0] DELAY[3:0] MULTI[4:0] Res. Reserved Bits 31:24 Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and V enable REFINT This bit is set and cleared by software to enable/disable the temperature sensor and the channel.
Page 431 RM0090 Analog-to-digital converter (ADC) Bit 11:8 DELAY: Delay between 2 sampling phases Set and cleared by software. These bits are used in dual or triple interleaved modes. 0000: 5 * T ADCCLK 0001: 6 * T ADCCLK 0010: 7 * T ADCCLK 1111: 20 * T ADCCLK...
Page 432: Table 71. Adc Global Register Map
Analog-to-digital converter (ADC) RM0090 13.13.17 ADC common regular data register for dual and triple modes (ADC_CDR) Address offset: 0x08 (this offset address is relative to ADC1 base address + 0x300) Reset value: 0x0000 0000 DATA2[15:0] DATA1[15:0] Bits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions –...
Page 433 RM0090 Analog-to-digital converter (ADC) Table 72. ADC register map and reset values for each ADC (continued) Offset Register DISC ADC_CR1 AWDCH[4:0] NUM [2:0] 0x04 Reserved Reserved Reset value JEXTSEL ADC_CR2 EXTSEL [3:0] [3:0] 0x08 Reserved Reserved Reset value ADC_SMPR1 Sample time bits SMPx_x 0x0C Reset value ADC_SMPR2...
Page 434: Table 73. Adc Register Map And Reset Values (Common Adc Registers)
Analog-to-digital converter (ADC) RM0090 Table 73. ADC register map and reset values (common ADC registers) Offset Register ADC_CSR Reser Reser 0x00 Reserved Reset value ADC3 ADC2 ADC1 ADC_CCR DELAY [3:0] MULTI [4:0] 0x04 Reserved Reserved Reserved Reset value ADC_CDR Regular DATA2[15:0] Regular DATA1[15:0] 0x08 Reset value...
Page 435: Digital-To-Analog Converter (Dac)
RM0090 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) This section applies to the whole STM32F4xx family, unless otherwise specified. 14.1 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 436: Table 74. Dac Pins
Digital-to-analog converter (DAC) RM0090 Figure 64. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex...
Page 437: Dac Functional Description
RM0090 Digital-to-analog converter (DAC) 14.3 DAC functional description 14.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only.
Page 438: Figure 65. Data Registers In Single Dac Channel Mode
Digital-to-analog converter (DAC) RM0090 Figure 65. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –...
Page 439: Table 75. External Triggers
RM0090 Digital-to-analog converter (DAC) Figure 67. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b 14.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation:...
Page 440: Dma Request
Digital-to-analog converter (DAC) RM0090 Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle. 14.3.7 DMA request Each DAC channel has a DMA capability.
Page 441: Figure 68. Dac Lfsr Register Calculation Algorithm
RM0090 Digital-to-analog converter (DAC) Figure 68. DAC LFSR register calculation algorithm ai14713b The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.
Page 442: Figure 70. Dac Triangle Wave Generation
Digital-to-analog converter (DAC) RM0090 Figure 70. DAC triangle wave generation Figure 71. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0xABE 0xABF 0xAC0 0xABE SWTRIG ai14714 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.
Page 443: Independent Trigger With Single Lfsr Generation
RM0090 Digital-to-analog converter (DAC) When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). 14.4.2 Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required:...
Page 444: Independent Trigger With Single Triangle Generation
Digital-to-analog converter (DAC) RM0090 14.4.4 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 445: Simultaneous Trigger Without Wave Generation
RM0090 Digital-to-analog converter (DAC) 14.4.7 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 446: Simultaneous Trigger With Single Triangle Generation
Digital-to-analog converter (DAC) RM0090 14.4.10 Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 447: Dac Registers
RM0090 Digital-to-analog converter (DAC) 14.5 DAC registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 14.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU...
Page 448 Digital-to-analog converter (DAC) RM0090 Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9...
Page 449 RM0090 Digital-to-analog converter (DAC) Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 450: Dac Software Trigger Register (Dac_Swtrigr)
Digital-to-analog converter (DAC) RM0090 14.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved SWTRIG2 SWTRIG1 Reserved Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2...
Page 451 RM0090 Digital-to-analog converter (DAC) 14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
Page 452 Digital-to-analog converter (DAC) RM0090 14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 453 RM0090 Digital-to-analog converter (DAC) 14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 454: Dac Channel1 Data Output Register (Dac_Dor1)
Digital-to-analog converter (DAC) RM0090 14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
Page 455: Table 76. Dac Register Map
RM0090 Digital-to-analog converter (DAC) 14.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 DMAUDR2 Reserved Reserved rc_w1 DMAUDR1 Reserved Reserved rc_w1 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Page 456 Digital-to-analog converter (DAC) RM0090 Table 76. DAC register map (continued) Register Offset name DAC_ 0x1C Reserved DACC2DHR[7:0] DHR8R2 DAC_ 0x20 Reserved DACC2DHR[11:0] Reserved DACC1DHR[11:0] DHR12RD DAC_ 0x24 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved DHR12LD DAC_ 0x28 Reserved DACC2DHR[7:0] DACC1DHR[7:0] DHR8RD DAC_ 0x2C Reserved DACC1DOR[11:0] DOR1...
Page 457: Table 77. Dcmi Pins
RM0090 Digital camera interface (DCMI) Digital camera interface (DCMI) This section applies to all STM32F4xx devices, unless otherwise specified. 15.1 DCMI introduction The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
Page 458: Figure 72. Dcmi Block Diagram
Digital camera interface (DCMI) RM0090 15.5 DCMI functional overview The digital camera interface is a synchronous parallel interface that can receive high-speed (up to 54 Mbytes/s) data flows. It consists of up to 14 data lines (D13-D0) and a pixel clock line (PIXCLK).
Page 459: Table 78. Dcmi Signals
RM0090 Digital camera interface (DCMI) 15.5.1 DMA interface The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA request is generated each time the camera interface receives a complete 32-bit data block in its register. 15.5.2 DCMI physical interface The interface is composed of 11/13/15/17 inputs.
Page 460: Table 79. Positioning Of Captured Data Bytes In 32-Bit Words (8-Bit Width)
Digital camera interface (DCMI) RM0090 8-bit data When EDM[1:0] in DCMI_CR are programmed to “00” the interface captures 8 LSB’s at its input (D[0:7]) and stores them as 8-bit data. The D[13:8] inputs are ignored. In this case, to capture a 32-bit word, the camera interface takes four pixel clock cycles. The first captured data byte is placed in the LSB position in the 32-bit word and the 4 captured data byte is placed in the MSB position in the 32-bit word.
Page 461: Table 82. Positioning Of Captured Data Bytes In 32-Bit Words (14-Bit Width)
RM0090 Digital camera interface (DCMI) word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is made up every two pixel clock cycles. The first captured data are placed in the LSB position in the 32-bit word and the 2 captured data are placed in the MSB position in the 32-bit word as shown in Table Table 82.
Page 462 Digital camera interface (DCMI) RM0090 Hardware synchronization mode In hardware synchronisation mode, the two synchronization signals (HSYNC/VSYNC) are used. Depending on the camera module/mode, data may be transmitted during horizontal/vertical synchronisation periods. The HSYNC/VSYNC signals act like blanking signals since all the data received during HSYNC/VSYNC active periods are ignored.
Page 463: Figure 76. Frame Capture Waveforms In Snapshot Mode
RM0090 Digital camera interface (DCMI) This mode can be supported by programming the following codes: • FS ≤ 0xFF • FE ≤ 0xFF • LS ≤ SAV (active) • LE ≤ EAV (active) An embedded unmask code is also implemented for frame/line start and frame/line end codes.
Page 464: Figure 77. Frame Capture Waveforms In Continuous Grab Mode
Digital camera interface (DCMI) RM0090 Continuous grab mode In this mode (CM bit = ‘0’ in DCMI_CR), once the CAPTURE bit has been set in DCMI_CR, the grabbing process starts on the next VSYNC or embedded frame start depending on the mode.
Page 465: Figure 79. Data Capture Waveforms
RM0090 Digital camera interface (DCMI) These registers specify the coordinates of the starting point of the capture window as a line number (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from 0), and the size of the window as a line number and a number of pixel clocks. The CAPCNT value can only be a multiple of 4 (two least significant bits are forced to 0) to allow the correct transfer of data through the DMA.
Page 466: Table 83. Data Storage In Monochrome Progressive Video Format
Digital camera interface (DCMI) RM0090 15.6 Data format description 15.6.1 Data formats Three types of data are supported: • 8-bit progressive video: either monochrome or raw Bayer format • YCbCr 4:2:2 progressive video • RGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits for green) takes two clock cycles to be transferred.
Page 467: Table 84. Data Storage In Rgb Progressive Video Format
RM0090 Digital camera interface (DCMI) The RGB planar format is compatible with standard OS frame buffer display formats. Only 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported. The 24 BPP (palletized format) and grayscale formats are not supported. Pixels are stored in a raster scan order, that is from top to bottom for pixel rows, and from left to right within a pixel row.
Page 468: Dcmi Register Description
Digital camera interface (DCMI) RM0090 15.8 DCMI register description All DCMI registers have to be accessed as 32-bit words, otherwise a bus error occurs. 15.8.1 DCMI control register 1 (DCMI_CR) Address offset: 0x00 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FCRC Reserved rw rw rw rw rw rw rw rw rw rw rw rw...
Page 469 RM0090 Digital camera interface (DCMI) Bit 4 ESS: Embedded synchronization select 0: Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals. 1: Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow. Note: Valid only for 8-bit parallel data. HSPOL/VSPOL are ignored when the ESS bit is set.
Page 470: Dcmi Status Register (Dcmi_Sr)
Digital camera interface (DCMI) RM0090 15.8.2 DCMI status register (DCMI_SR) Address offset: 0x04 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Bits 31:3 Reserved, must be kept at reset value.
Page 471: Dcmi Raw Interrupt Status Register (Dcmi_Ris)
RM0090 Digital camera interface (DCMI) 15.8.3 DCMI raw interrupt status register (DCMI_RIS) Address offset: 0x08 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DCMI_RIS gives the raw interrupt status and is accessible in read only.
Page 472: Dcmi Interrupt Enable Register (Dcmi_Ier)
Digital camera interface (DCMI) RM0090 15.8.4 DCMI interrupt enable register (DCMI_IER) Address offset: 0x0C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw The DCMI_IER register is used to enable interrupts.
Page 473: Dcmi Masked Interrupt Status Register (Dcmi_Mis)
RM0090 Digital camera interface (DCMI) 15.8.5 DCMI masked interrupt status register (DCMI_MIS) This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
Page 474: Dcmi Interrupt Clear Register (Dcmi_Icr)
Digital camera interface (DCMI) RM0090 15.8.6 DCMI interrupt clear register (DCMI_ICR) Address offset: 0x14 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved w w w w w The DCMI_ICR register is write-only.
Page 475: Dcmi Embedded Synchronization Code Register (Dcmi_Escr)
RM0090 Digital camera interface (DCMI) 15.8.7 DCMI embedded synchronization code register (DCMI_ESCR) Address offset: 0x18 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 FEC: Frame end delimiter code This byte specifies the code of the frame end delimiter.
Page 476: Dcmi Embedded Synchronization Unmask Register (Dcmi_Esur)
Digital camera interface (DCMI) RM0090 15.8.8 DCMI embedded synchronization unmask register (DCMI_ESUR) Address offset: 0x1C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 FEU: Frame end delimiter unmask This byte specifies the mask to be applied to the code of the frame end delimiter.
Page 477: Dcmi Crop Window Start (Dcmi_Cwstrt)
RM0090 Digital camera interface (DCMI) 15.8.9 DCMI crop window start (DCMI_CWSTRT) Address offset: 0x20 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VST[12:0 HOFFCNT[13:0] Reserv...
Page 478: Table 87. Dcmi Register Map And Reset Values
Digital camera interface (DCMI) RM0090 15.8.11 DCMI data register (DCMI_DR) Address offset: 0x28 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Byte3 Byte2 Byte1 Byte0...
Page 479 RM0090 Digital camera interface (DCMI) Table 87. DCMI register map and reset values (continued) Offset Register DCMI_ICR 0x14 Reserved Reset value DCMI_ESCR 0x18 Reset value DCMI_ESUR 0x1C Reset value DCMI_CWSTR VST[12:0 HOFFCNT[13:0] Reserve 0x20 Reset value DCMI_CWSIZ VLINE13:0] CAPCNT[13:0] 0x24 Reset value Byte3 Byte2...
Page 480: Lcd-Tft Controller (Ltdc)
LCD-TFT Controller (LTDC) RM0090 LCD-TFT Controller (LTDC) This section applies only to STM32F429xx/439xx devices. 16.1 Introduction The LCD-TFT (Liquid Crystal Display - Thin Film Transistor) display controller provides a parallel digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronisation, Pixel Clock and Data Enable as output to interface directly to a variety of LCD and TFT panels.
Page 481: Figure 81. Ltdc Block Diagram
RM0090 LCD-TFT Controller (LTDC) 16.3 LTDC functional description 16.3.1 LTDC block diagram The block diagram of the LTDC is shown in Figure 81: LTDC block diagram. Figure 81. LTDC block diagram Layer FIFO: One FIFO 64x32 bit per layer. PFC: Pixel Format Convertor performing the pixel format conversion from the selected input pixel format of a layer to words.
Page 482: Table 88. Lcd-Tft Pins And Signal Interface
LCD-TFT Controller (LTDC) RM0090 16.3.3 LCD-TFT pins and signal interface The Table below summarizes the LTDC signal interface: Table 88. LCD-TFT pins and signal interface LCD-TFT Description signals LCD_CLK Clock Output LCD_HSYNC Horizontal Synchronization LCD_VSYNC Vertical Synchronization LCD_DE Data Enable LCD_R[7:0] Data: 8-bit Red data LCD_G[7:0]...
Page 483: Figure 82. Lcd-Tft Synchronous Timings
RM0090 LCD-TFT Controller (LTDC) Figure 82. LCD-TFT Synchronous timings Note: The HBP and HFP are respectively the Horizontal back porch and front porch period. The VBP and the VFP are respectively the Vertical back porch and front porch period. The LCD-TFT programmable synchronous timings are: –...
Page 484 LCD-TFT Controller (LTDC) RM0090 When the LTDC is disabled, the timing generator block is reset to X=Total Width - 1, Y=Total Height - 1 and held the last pixel before the vertical synchronization phase and the FIFO are flushed. Therefore only blanking data is output continuously. Example of Synchronous timings configuration: TFT-LCD timings (should be extracted from Panel datasheet): •...
Page 485: Figure 83. Layer Window Programmable Parameters
RM0090 LCD-TFT Controller (LTDC) Reload Shadow registers Some configuration registers are shadowed. The shadow registers values can be reloaded immediately to the active registers when writing to these registers or at the beginning of the vertical blanking period following the configuration in the LTDC_SRCR register. If the immediate reload configuration is selected, the reload should be only activated when all new registers have been written.
Page 486: Table 89. Pixel Data Mapping Versus Color Format
LCD-TFT Controller (LTDC) RM0090 Pixel input Format The programmable pixel format is used for the data stored in the frame buffer of a layer. Up to 8 input pixel formats can be configured for every layer through the LTDC_LxPFCR register The pixel data is read from the frame buffer and then transformed to the internal 8888 (ARGB) format as follows: •...
Page 487 RM0090 LCD-TFT Controller (LTDC) Table 89. Pixel Data mapping versus Color Format (continued) ARGB8888 [3:0]R [3:0] [3:0] B [3:0] [3:0]R [3:0] [3:0] B [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] AL44 [3:0] L [3:0] [3:0] L [3:0] [3:0] L [3:0] [3:0] L [3:0]...
Page 488: Figure 84. Blending Two Layers With Background
LCD-TFT Controller (LTDC) RM0090 Color Frame Buffer Address Every Layer has a start address for the color frame buffer configured through the LTDC_LxCFBAR register. When a layer is enabled, the data is fetched from the Color Frame Buffer. Color Frame Buffer Length Every layer has a total line length setting for the color frame buffer in bytes and a number of lines in the frame buffer configurable in the LTDC_LxCFBLR and LTDC_LxCFBLNR register respectively.
Page 489: Figure 85. Interrupt Events
RM0090 LCD-TFT Controller (LTDC) Default color Every layer can have a default color in the format ARGB which is used outside the defined layer window or when a layer is disabled. The default color is configured through the LTDC_LxDCCR register. The blending is always performed between the two layers even when a layer is disabled.
Page 490: Table 90. Ltdc Interrupt Requests
LCD-TFT Controller (LTDC) RM0090 Table 90. LTDC interrupt requests Interrupt event Event flag Enable Control bit Line Register Reload RRIF RRIEN FIFO Underrun FUDERRIF FUDERRIE Transfer Error TERRIF TERRIE 16.6 LTDC programming procedure • Enable the LTDC clock in the RCC register •...
Page 491: Ltdc Registers
RM0090 LCD-TFT Controller (LTDC) 16.7 LTDC registers 16.7.1 LTDC Synchronization Size Configuration Register (LTDC_SSCR) This register defines the number of Horizontal Synchronization pixels minus 1 and the number of Vertical Synchronization lines minus 1. Refer to Figure 82 Section 16.4: LTDC programmable parameters for an example of configuration.
Page 492: Ltdc Active Width Configuration Register (Ltdc_Awcr)
LCD-TFT Controller (LTDC) RM0090 Bits 31:28 Reserved, must be kept at reset value Bits 27:16 AHBP[11:0]: Accumulated Horizontal back porch (in units of pixel clock period) These bits define the Accumulated Horizontal back porch width which includes the Horizontal Synchronization and Horizontal back porch pixels minus 1. The Horizontal back porch is the period between Horizontal Synchronization going inactive and the start of the active display part of the next scan line.
Page 493: Ltdc Total Width Configuration Register (Ltdc_Twcr)
RM0090 LCD-TFT Controller (LTDC) 16.7.4 LTDC Total Width Configuration Register (LTDC_TWCR) This register defines the accumulated number of Horizontal Synchronization, back porch, Active and front porch pixels minus 1 (HSYNC Width + HBP + Active Width + HFP - 1) and the accumulated number of Vertical Synchronization, back porch lines, Active and Front lines minus 1 (VSYNC Height+ BVBP + Active Height + VFP - 1).
Page 494 LCD-TFT Controller (LTDC) RM0090 Bit 31 HSPOL: Horizontal Synchronization Polarity This bit is set and cleared by software. 0: Horizontal Synchronization polarity is active low 1: Horizontal Synchronization polarity is active high Bit 30 VSPOL: Vertical Synchronization Polarity This bit is set and cleared by software. 0: Vertical Synchronization is active low 1: Vertical Synchronization is active high Bit 29 DEPOL: Data Enable Polarity...
Page 495: Ltdc Shadow Reload Configuration Register (Ltdc_Srcr)
RM0090 LCD-TFT Controller (LTDC) 16.7.6 LTDC Shadow Reload Configuration Register (LTDC_SRCR) This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR. Address offset: 0x24 Reset value: 0x0000 0000 Reserved...
Page 496: Ltdc Interrupt Enable Register (Ltdc_Ier)
LCD-TFT Controller (LTDC) RM0090 Bits 31:24 Reserved, must be kept at reset value Bits 23:16 BCRED[7:0]: Background Color Red value These bits configure the background red value Bits 15:8 BCGREEN[7:0]: Background Color Green value These bits configure the background green value Bits 7:0 BCBLUE[7:0]: Background Color Blue value These bits configure the background blue value 16.7.8...
Page 497: Ltdc Interrupt Status Register (Ltdc_Isr)
RM0090 LCD-TFT Controller (LTDC) 16.7.9 LTDC Interrupt Status Register (LTDC_ISR) This register returns the interrupt status flag Address offset: 0x38 Reset value: 0x0000 0000 Reserved RRIF TERRIF FUIF Reserved Bits 31:24 Reserved, must be kept at reset value Bit 3 RRIF: Register Reload Interrupt Flag 0: No Register Reload interrupt generated 1: Register Reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)
Page 498: Ltdc Line Interrupt Position Configuration Register (Ltdc_Lipcr)
LCD-TFT Controller (LTDC) RM0090 Bits 31:24 Reserved, must be kept at reset value Bit 3 CRRIF: Clears Register Reload Interrupt Flag 0: No effect 1: Clears the RRIF flag in the LTDC_ISR register Bit 2 CTERRIF: Clears the Transfer Error Interrupt Flag 0: No effect 1: Clears the TERRIF flag in the LTDC_ISR register.
Page 499: Ltdc Current Display Status Register (Ltdc_Cdsr)
RM0090 LCD-TFT Controller (LTDC) Bits 31:16: CXPOS[15:0]: Current X Position These bits return the current X position Bits 15:0 CYPOS[15:0]: Current Y Position These bits return the current Y position 16.7.13 LTDC Current Display Status Register (LTDC_CDSR) This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and Horizontal/Vertical DE signals.
Page 500: Ltdc Layerx Control Register (Ltdc_Lxcr) (Where X=1..2)
LCD-TFT Controller (LTDC) RM0090 16.7.14 LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) Address offset: 0x84 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 Reserved CLUTEN COLKEN Reserved Reserved Bits 31:5 Reserved, must be kept at reset value Bit 4 CLUTEN: Color Look-Up Table Enable This bit is set and cleared by software.
Page 501: Ltdc_Lxwvpcr) (Where X=1..2)
RM0090 LCD-TFT Controller (LTDC) WHSPPOS[11:0] Reserved WHSTPOS[11:0] Reserved Bits 31:28 Reserved, must be kept at reset value Bits 27:16 WHSPPOS[11:0]: Window Horizontal Stop Position These bits configure the last visible pixel of a line of the layer window. Bits 15:12 Reserved, must be kept at reset value Bits 11:0 WHSTPOS[11:0]: Window Horizontal Start Position These bits configure the first visible pixel of a line of the layer window.
Page 502 LCD-TFT Controller (LTDC) RM0090 Bits 31:27 Reserved, must be kept at reset value Bits 26:16 WVSPPOS[10:0]: Window Vertical Stop Position These bits configures the last visible line of the layer window. Bits 15:11 Reserved, must be kept at reset value Bits 10:0 WVSTPOS[10:0]: Window Vertical Start Position These bits configure the first visible line of the layer window.
Page 503 RM0090 LCD-TFT Controller (LTDC) 16.7.18 LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR) (where x=1..2) This register defines the pixel format which is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
Page 504 LCD-TFT Controller (LTDC) RM0090 Bits 31:8 Reserved, must be kept at reset value Bits 7:0 CONSTA[7:0]: Constant Alpha These bits configure the Constant Alpha used for blending. The Constant Alpha is divided by 255 by hardware. Example: if the programmed Constant Alpha is 0xFF, the Constant Alpha value is 255/255=1 16.7.20 LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR)
Page 505 RM0090 LCD-TFT Controller (LTDC) 16.7.21 LTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR) (where x=1..2) This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs • BC = Blended color •...
Page 506 LCD-TFT Controller (LTDC) RM0090 Note: The Constant Alpha value, is the programmed value in the LxCACR register divided by 255 by hardware. Example: Only layer1 is enabled, BF1 configured to Constant Alpha BF2 configured to Constant Alpha Constant Alpha: The Constant Alpha programmed in the LxCACR register is 240 (0xF0). Thus, the Constant Alpha value is 240/255 = 0.94 C: Current Layer Color is 128 Cs: Background color is 48...
Page 507: Ltdc_Lxcfblnr) (Where X=1..2)
RM0090 LCD-TFT Controller (LTDC) Bits 31:29 Reserved, must be kept at reset valuer Bits 28:16 CFBP[12:0]: Color Frame Buffer Pitch in bytes These bits define the pitch which is the increment from the start of one line of pixels to the start of the next line in bytes.
Page 508 LCD-TFT Controller (LTDC) RM0090 16.7.25 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) (where x=1..2) This register defines the CLUT address and the RGB value. Address offset: 0xC4 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 CLUTADD[7:0] RED[7:0] GREEN[7:0]...
Page 509: Table 91. Ltdc Register Map And Reset Values
RM0090 LCD-TFT Controller (LTDC) 16.7.26 LTDC register map The following table summarizes the LTDC registers. Refer to the register boundary addresses table for the LTDC register base address. Table 91. LTDC register map and reset values Offset Register LTDC_SSCR HSW[9:0] VSH[10:0] 0x0008 Reserved...
Page 510 LCD-TFT Controller (LTDC) RM0090 Table 91. LTDC register map and reset values (continued) Offset Register LTDC_L1WVPCR WVSPPOS[10:0] WVSTPOS[10:0] 0x008C Reserved Reserved Reset value LTDC_L1CKCR CKRED[7:0] CKGREEN[7:0] CKBLUE[7:0] 0x0090 Reserved Reset value LTDC_L1PFCR PF[2:0] 0x0094 Reserved Reset value LTDC_L1CACR CONSTA[7:0] 0x0098 Reserved Reset value LTDC_L1DCCR...
Page 511 RM0090 LCD-TFT Controller (LTDC) Table 91. LTDC register map and reset values (continued) Offset Register LTDC_L2CFBLNR CFBLNBR[10:0] 0x0134 Reserved Reset value LTDC_L2CLUTWR CLUTADD[7:0] RED[7:0] GREEN[7:0] BLUE[7:0] 0x0144 Reset value DocID018909 Rev 11 511/1731...
Page 512: Tim1&Tim8 Introduction
Advanced-control timers (TIM1&TIM8) RM0090 Advanced-control timers (TIM1&TIM8) This section applies to the whole STM32F4xx family, unless otherwise specified. 17.1 TIM1&TIM8 introduction The advanced-control timers (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 513: Tim1&Tim8 Main Features
RM0090 Advanced-control timers (TIM1&TIM8) 17.2 TIM1&TIM8 main features TIM1&TIM8 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •...
Page 514: Figure 86. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1&TIM8) RM0090 Figure 86. Advanced-control timer block diagram Internal Clock (CK_INT) CK_TIM18 from RCC ETRF Trigger ETRP Controller Polarity Selection & Edge TRGO TIMx_ETR Input Filter Detector & Prescaler to other timers ITR0 to DAC/ADC ITR1 Slave Reset, Enable, Up/Down, Count ITR2 Mode TRGI...
Page 515: Tim1&Tim8 Functional Description
RM0090 Advanced-control timers (TIM1&TIM8) 17.3 TIM1&TIM8 functional description 17.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 516: Figure 87. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Advanced-control timers (TIM1&TIM8) RM0090 Figure 87. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 88.
Page 517: Figure 89. Counter Timing Diagram, Internal Clock Divided By 1
RM0090 Advanced-control timers (TIM1&TIM8) preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).
Page 518: Figure 91. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1&TIM8) RM0090 Figure 91. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 92. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 519: Figure 94. Counter Timing Diagram, Update Event When Arpe=1
RM0090 Advanced-control timers (TIM1&TIM8) Figure 94. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register Write a new value in TIMx_ARR...
Page 520: Figure 95. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0090 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 95. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV)
Page 521: Figure 98. Counter Timing Diagram, Internal Clock Divided By N
RM0090 Advanced-control timers (TIM1&TIM8) Figure 98. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 99. Counter timing diagram, update event when repetition counter is not used CK_PSC Timer clock = CK_CNT...
Page 522: Figure 100. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1&TIM8) RM0090 The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
Page 523: Figure 101. Counter Timing Diagram, Internal Clock Divided By 2
RM0090 Advanced-control timers (TIM1&TIM8) Figure 101. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT...
Page 524: Figure 104. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
Advanced-control timers (TIM1&TIM8) RM0090 Figure 104. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timer clock = CK_CNT Counter register 05 04 03 02 01 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 525: Figure 106. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0090 Advanced-control timers (TIM1&TIM8) The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 526: Figure 107. Control Circuit In Normal Mode, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0090 17.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 527: Figure 109. Control Circuit In External Clock Mode 1
RM0090 Advanced-control timers (TIM1&TIM8) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 528: Figure 110. External Trigger Input Block
Advanced-control timers (TIM1&TIM8) RM0090 Figure 110. External trigger input block TI2F TI1F encoder mode TRGI external clock mode 1 CK_PSC ETR pin ETRP ETRF external clock filter divider mode 2 downcounter /1, /2, /4, /8 CK_INT internal clock mode (internal clock) ETPS[1:0] ETF[3:0] TIMx_SMCR...
Page 529: Figure 112. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0090 Advanced-control timers (TIM1&TIM8) used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Figure 112. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_Rising TI1F TI1FP1...
Page 530: Figure 114. Output Stage Of Capture/Compare Channel (Channel 1 To 3)
Advanced-control timers (TIM1&TIM8) RM0090 Figure 114. Output stage of capture/compare channel (channel 1 to 3) To the master mode controller Output enable ‘0’ circuit OC1_DT CC1P CNT>CCR1 OC1REF Output mode Dead-time TIM1_CCER CNT=CCR1 controller generator OC1N_DT OC1N Output ‘0’ enable circuit CC1NE CC1E TIM1_CCER...
Page 531 RM0090 Advanced-control timers (TIM1&TIM8) The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: • Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register.
Page 532: Figure 116. Pwm Input Mode Timing
Advanced-control timers (TIM1&TIM8) RM0090 17.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 533: Forced Output Mode
RM0090 Advanced-control timers (TIM1&TIM8) 17.3.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 534: Figure 117. Output Compare Mode, Toggle On Oc1
Advanced-control timers (TIM1&TIM8) RM0090 Select the counter clock (internal, external, prescaler). Write the desired data in the TIMx_ARR and TIMx_CCRx registers. Set the CCxIE bit if an interrupt request is to be generated. Select the output mode. For example: – Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx –...
Page 535: Figure 118. Edge-Aligned Pwm Waveforms (Arr=8)
RM0090 Advanced-control timers (TIM1&TIM8) OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.
Page 536: Figure 119. Center-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0090 PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration.
Page 537: Complementary Outputs And Dead-Time Insertion
RM0090 Advanced-control timers (TIM1&TIM8) Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Page 538: Figure 120. Complementary Output With Dead-Time Insertion
Advanced-control timers (TIM1&TIM8) RM0090 Figure 120. Complementary output with dead-time insertion. OCxREF delay OCxN delay Figure 121. Dead-time waveforms with delay greater than the negative pulse. OCxREF delay OCxN Figure 122. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay...
Page 539: Using The Break Function
RM0090 Advanced-control timers (TIM1&TIM8) 17.3.12 Using the break function When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time.
Page 540 Advanced-control timers (TIM1&TIM8) RM0090 Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared. The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register.
Page 541: Figure 123. Output Behavior In Response To A Break
RM0090 Advanced-control timers (TIM1&TIM8) Figure 123. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 542: Figure 124. Clearing Timx Ocxref
Advanced-control timers (TIM1&TIM8) RM0090 17.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 543: Figure 125. 6-Step Generation, Com Example (Ossr=1)
RM0090 Advanced-control timers (TIM1&TIM8) 17.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 544: Figure 126. Example Of One Pulse Mode
Advanced-control timers (TIM1&TIM8) RM0090 17.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 545: Encoder Interface Mode
RM0090 Advanced-control timers (TIM1&TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 546: Table 92. Counting Direction Versus Encoder Signals
Advanced-control timers (TIM1&TIM8) RM0090 configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 547: Figure 127. Example Of Counter Operation In Encoder Interface Mode
RM0090 Advanced-control timers (TIM1&TIM8) Figure 127. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down Figure 128 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 128.
Page 548: Interfacing With Hall Sensors
Advanced-control timers (TIM1&TIM8) RM0090 Section 17.3.18 below. 17.3.18 Interfacing with Hall sensors This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as “interfacing timer”...
Page 549: Figure 129. Example Of Hall Sensor Interface
RM0090 Advanced-control timers (TIM1&TIM8) Figure 129. Example of hall sensor interface TIH1 TIH2 TIH3 counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step ai17335 DocID018909 Rev 11 549/1731...
Page 550: Figure 130. Control Circuit In Reset Mode
Advanced-control timers (TIM1&TIM8) RM0090 17.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 551: Figure 131. Control Circuit In Gated Mode
RM0090 Advanced-control timers (TIM1&TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 552: Figure 132. Control Circuit In Trigger Mode
Advanced-control timers (TIM1&TIM8) RM0090 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 553: Figure 133. Control Circuit In External Clock Mode 2 + Trigger Mode
RM0090 Advanced-control timers (TIM1&TIM8) – CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edge only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag.
Page 554: Tim1&Tim8 Registers
Advanced-control timers (TIM1&TIM8) RM0090 17.4 TIM1&TIM8 registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits). 17.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 555: Tim1&Tim8 Control Register 2 (Timx_Cr2)
RM0090 Advanced-control timers (TIM1&TIM8) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 556 Advanced-control timers (TIM1&TIM8) RM0090 Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 557 RM0090 Advanced-control timers (TIM1&TIM8) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 558: Tim1&Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0090 17.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge.
Page 559 RM0090 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 560: Table 93. Timx Internal Trigger Connection
Advanced-control timers (TIM1&TIM8) RM0090 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 561 RM0090 Advanced-control timers (TIM1&TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled...
Page 562: Tim1&Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0090 17.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag...
Page 563: Tim1&Tim8 Event Generation Register (Timx_Egr)
RM0090 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 564 Advanced-control timers (TIM1&TIM8) RM0090 Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
Page 565: Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0090 Advanced-control timers (TIM1&TIM8) 17.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 566 Advanced-control timers (TIM1&TIM8) RM0090 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 567 RM0090 Advanced-control timers (TIM1&TIM8) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 568: Tim1&Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0090 Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 569: Tim1&Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0090 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 570 Advanced-control timers (TIM1&TIM8) RM0090 Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output:...
Page 571 RM0090 Advanced-control timers (TIM1&TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 572: Table 94. Output Control Bits For Complementary Ocx And Ocxn Channels With
Advanced-control timers (TIM1&TIM8) RM0090 Table 94. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the the timer), OCx=0, OCx_EN=0 timer), OCxN=0, OCxN_EN=0 Output Disabled (not driven by...
Page 573: Tim1&Tim8 Counter (Timx_Cnt)
RM0090 Advanced-control timers (TIM1&TIM8) Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. 17.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 17.4.11...
Page 574: Tim1&Tim8 Repetition Counter Register (Timx_Rcr)
Advanced-control timers (TIM1&TIM8) RM0090 17.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 575: Tim1&Tim8 Capture/Compare Register 2 (Timx_Ccr2)
RM0090 Advanced-control timers (TIM1&TIM8) 17.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 576: Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timers (TIM1&TIM8) RM0090 17.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 577 RM0090 Advanced-control timers (TIM1&TIM8) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 578: Tim1&Tim8 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1&TIM8) RM0090 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 579: Tim1&Tim8 Dma Address For Full Transfer (Timx_Dmar)
RM0090 Advanced-control timers (TIM1&TIM8) 17.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 580: Table 95. Tim1&Tim8 Register Map And Reset Values
Advanced-control timers (TIM1&TIM8) RM0090 17.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 95. TIM1&TIM8 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value MMS[2:0 TIMx_CR2 Reserved 0x04...
Page 581 RM0090 Advanced-control timers (TIM1&TIM8) Table 95. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_ARR ARR[15:0] Reserved 0x2C Reset value TIMx_RCR REP[7:0] Reserved 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value TIMx_CCR3 CCR3[15:0] Reserved 0x3C...
Page 582: Tim2 To Tim5 Introduction
General-purpose timers (TIM2 to TIM5) RM0090 General-purpose timers (TIM2 to TIM5) This section applies to the whole STM32F4xx family, unless otherwise specified. 18.1 TIM2 to TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler.
Page 583: Figure 134. General-Purpose Timer Block Diagram
RM0090 General-purpose timers (TIM2 to TIM5) Figure 134. General-purpose timer block diagram Internal Clock (CK_INT) TIMxCLK from RCC ETRF ETRP Polarity selection & edge TIMx_ETR Input filter detector & prescaler TRGO ITR0 Trigger to other timers ITR1 controller to DAC/ADC ITR2 TRGI Slave...
Page 584: Figure 135. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2 to TIM5) RM0090 The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 585: Figure 136. Counter Timing Diagram With Prescaler Division Change From 1 To 4
RM0090 General-purpose timers (TIM2 to TIM5) Figure 136. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter 18.3.2...
Page 586: Figure 137. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0090 Figure 137. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 138.
Page 587: Figure 140. Counter Timing Diagram, Internal Clock Divided By N
RM0090 General-purpose timers (TIM2 to TIM5) Figure 140. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN...
Page 588: Figure 142. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2 to TIM5) RM0090 Figure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 589: Figure 143. Counter Timing Diagram, Internal Clock Divided By 1
RM0090 General-purpose timers (TIM2 to TIM5) Figure 143. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 144.
Page 590: Figure 146. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0090 Figure 146. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 147. Counter timing diagram, Update event CK_INT CNT_EN Timer clock = CK_CNT Counter register...
Page 591: Figure 148. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0090 General-purpose timers (TIM2 to TIM5) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
Page 592: Figure 149. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 to TIM5) RM0090 Figure 149. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN TImer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 150.
Page 593: Figure 152. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
RM0090 General-purpose timers (TIM2 to TIM5) Figure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register 05 04 03 02 01 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR...
Page 594: Figure 154. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0090 Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically).
Page 595: Figure 156. Control Circuit In External Clock Mode 1
RM0090 General-purpose timers (TIM2 to TIM5) Note: The capture prescaler is not used for triggering, so you don’t need to configure it. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
Page 596: Figure 158. Control Circuit In External Clock Mode 2
General-purpose timers (TIM2 to TIM5) RM0090 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 597: Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0090 General-purpose timers (TIM2 to TIM5) Figure 159. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_Rising TI1F TI1FP1 filter Edge downcounter Detector TI1F_Falling TI2FP1 IC1PS divider /1, /2, /4, /8 ICF[3:0] CC1P/CC1NP (from slave mode TIMx_CCMR1 TIMx_CCER controller)
Page 598: Figure 161. Output Stage Of Capture/Compare Channel (Channel 1)
General-purpose timers (TIM2 to TIM5) RM0090 Figure 161. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 599: Pwm Input Mode
RM0090 General-purpose timers (TIM2 to TIM5) new level have been detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
Page 600: Figure 162. Pwm Input Mode Timing
General-purpose timers (TIM2 to TIM5) RM0090 For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): •...
Page 601: Output Compare Mode
RM0090 General-purpose timers (TIM2 to TIM5) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 18.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 602: Figure 163. Output Compare Mode, Toggle On Oc1
General-purpose timers (TIM2 to TIM5) RM0090 Figure 163. Output compare mode, toggle on OC1 Write B201h in the CC1R register 0039 003A B200 B201 TIMx_CNT 003B TIMx_CCR1 003A B201 OC1REF=OC1 Match detected on CCR1 Interrupt generated if enabled 18.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 603: Figure 164. Edge-Aligned Pwm Waveforms (Arr=8)
RM0090 General-purpose timers (TIM2 to TIM5) PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section : Upcounting mode on page 585. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low.
Page 604: Figure 165. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0090 Figure 165. Center-aligned PWM waveforms (ARR=8) Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register.
Page 605: Figure 166. Example Of One-Pulse Mode
RM0090 General-purpose timers (TIM2 to TIM5) 18.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 606: Clearing The Ocxref Signal On An External Event
General-purpose timers (TIM2 to TIM5) RM0090 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY •...
Page 607: Figure 167. Clearing Timx Ocxref
RM0090 General-purpose timers (TIM2 to TIM5) Figure 167. Clearing TIMx OCxREF (CCRx) counter (CNT) ETRF OCxREF (OCxCE=0) OCxREF (OCxCE=1) ETRF ETRF becomes high still high 1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow.
Page 608: Table 96. Counting Direction Versus Encoder Signals
General-purpose timers (TIM2 to TIM5) RM0090 Table 96. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count...
Page 609: Figure 169. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
RM0090 General-purpose timers (TIM2 to TIM5) Figure 169 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 169. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward Counter down...
Page 610: Figure 170. Control Circuit In Reset Mode
General-purpose timers (TIM2 to TIM5) RM0090 CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). • Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. •...
Page 611: Figure 171. Control Circuit In Gated Mode
RM0090 General-purpose timers (TIM2 to TIM5) Figure 171. Control circuit in gated mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 32 33 35 36 37 38 Write TIF=0 1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect in gated mode because gated mode acts on a level and not on an edge.
Page 612: Figure 173. Control Circuit In External Clock Mode 2 + Trigger Mode
General-purpose timers (TIM2 to TIM5) RM0090 In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: –...
Page 613: Figure 174. Master/Slave Timer Example
RM0090 General-purpose timers (TIM2 to TIM5) Using one timer as prescaler for another timer Figure 174. Master/Slave timer example TIM1 TIM2 Clock Master Slave CK_PSC TRGO1 ITR0 mode mode control Counter Prescaler Counter Prescaler control Input trigger selection For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 174.
Page 614: Figure 175. Gating Timer 2 With Oc1Ref Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0090 Figure 175. Gating timer 2 with OC1REF of timer 1 CK_INT TIMER1-OC1REF TIMER1-CNT TIMER2-CNT 3045 3046 3047 3048 TIMER 2-TIF Write TIF=0 In the example in Figure 241, the Timer 2 counter and prescaler are not initialized before being started.
Page 615: Figure 176. Gating Timer 2 With Enable Of Timer 1
RM0090 General-purpose timers (TIM2 to TIM5) Figure 176. Gating timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 174 for connections.
Page 616: Figure 178. Triggering Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0090 As in the previous example, you can initialize both counters before starting counting. Figure 178 shows the behavior with the same configuration as in Figure 241 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 178.
Page 617: Figure 179. Triggering Timer 1 And 2 With Timer 1 Ti1 Input
RM0090 General-purpose timers (TIM2 to TIM5) Figure 179. Triggering timer 1 and 2 with timer 1 TI1 input CK_INT TIMER 1-TI1 TIMER1-CEN=CNT_EN TIMER 1-CK_PSC TIMER1-CNT 02 03 04 05 06 07 08 09 TIMER1-TIF TIMER2-CEN=CNT_EN TIMER 2-CK_PSC TIMER2-CNT 02 03 04 05 06 07 08 09 TIMER2-TIF 18.3.16 Debug mode...
Page 618: Tim2 To Tim5 Registers
General-purpose timers (TIM2 to TIM5) RM0090 18.4 TIM2 to TIM5 registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits).
Page 619 RM0090 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 620: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2 to TIM5) RM0090 18.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 TI1S MMS[2:0] CCDS Reserved Reserved Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for...
Page 621: Timx Slave Mode Control Register (Timx_Smcr)
RM0090 General-purpose timers (TIM2 to TIM5) 18.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 622 General-purpose timers (TIM2 to TIM5) RM0090 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Page 623: Table 97. Timx Internal Trigger Connection
RM0090 General-purpose timers (TIM2 to TIM5) Table 97. TIMx internal trigger connection Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM2 TIM1_TRGO TIM8_TRGO TIM3_TRGO TIM4_TRGO TIM3 TIM1_TRGO TIM2_TRGO TIM5_TRGO TIM4_TRGO TIM4 TIM1_TRGO TIM2_TRGO...
Page 624: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2 to TIM5) RM0090 Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable...
Page 625 RM0090 General-purpose timers (TIM2 to TIM5) Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 626: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM2 to TIM5) RM0090 18.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 CC4G CC3G CC2G CC1G Reserved Res. Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 627: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0090 General-purpose timers (TIM2 to TIM5) 18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 628 General-purpose timers (TIM2 to TIM5) RM0090 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 629 RM0090 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 630: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM2 to TIM5) RM0090 18.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode...
Page 631: Timx Capture/Compare Enable Register (Timx_Ccer)
RM0090 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 632: Table 98. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM2 to TIM5) RM0090 Bit 8 CC3E: Capture/Compare 3 output enable. refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable.
Page 633: Timx Counter (Timx_Cnt)
RM0090 General-purpose timers (TIM2 to TIM5) Note: The state of the external IO pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. 18.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 CNT[31:16] (depending on timers) CNT[15:0] Bits 15:0 CNT[15:0]: Counter value...
Page 634: Timx Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM2 to TIM5) RM0090 18.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 CCR1[31:16] (depending on timers) CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5). Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 635: Timx Capture/Compare Register 3 (Timx_Ccr3)
RM0090 General-purpose timers (TIM2 to TIM5) 18.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 0000 CCR3[31:16] (depending on timers) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5). Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
Page 636: Timx Dma Control Register (Timx_Dcr)
General-purpose timers (TIM2 to TIM5) RM0090 18.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 DBL[4:0] DBA[4:0] Reserved Reserved Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 637: Tim2 Option Register (Tim2_Or)
RM0090 General-purpose timers (TIM2 to TIM5) This is done in the following steps: Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
Page 638: Tim5 Option Register (Tim5_Or)
General-purpose timers (TIM2 to TIM5) RM0090 18.4.20 TIM5 option register (TIM5_OR) Address offset: 0x50 Reset value: 0x0000 TI4_RMP Reserved Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:6 TI4_RMP: Timer Input 4 remap Set and cleared by software. 00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table in the datasheets.
Page 639: Table 99. Tim2 To Tim5 Register Map And Reset Values
RM0090 General-purpose timers (TIM2 to TIM5) 18.4.21 TIMx register map TIMx registers are mapped as described in the table below: Table 99. TIM2 to TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved...
Page 640 General-purpose timers (TIM2 to TIM5) RM0090 Table 99. TIM2 to TIM5 register map and reset values (continued) Offset Register ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x2C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved CCR1[31:16]...
Page 641: Tim9 To Tim14 Introduction
RM0090 General-purpose timers (TIM9 to TIM14) General-purpose timers (TIM9 to TIM14) This section applies to the whole STM32F4xx family, unless otherwise specified. 19.1 TIM9 to TIM14 introduction The TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
Page 642: Figure 180. General-Purpose Timer Block Diagram (Tim9 And Tim12)
General-purpose timers (TIM9 to TIM14) RM0090 Figure 180. General-purpose timer block diagram (TIM9 and TIM12) Internal clock (CK_INT) ITR0 Trigger controller ITR1 ITR2 TRGI Slave ITR3 Reset, Enable, Count mode TI1F_ED controller TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT Prescaler COUNTER CC1I...
Page 643: Figure 181. General-Purpose Timer Block Diagram (Tim10/11/13/14)
RM0090 General-purpose timers (TIM9 to TIM14) Figure 181. General-purpose timer block diagram (TIM10/11/13/14) DocID018909 Rev 11 643/1731...
Page 644: Tim9 To Tim14 Functional Description
General-purpose timers (TIM9 to TIM14) RM0090 19.3 TIM9 to TIM14 functional description 19.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 645: Figure 182. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0090 General-purpose timers (TIM9 to TIM14) Figure 182. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 183.
Page 646: Figure 184. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM9 to TIM14) RM0090 setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 647: Figure 186. Counter Timing Diagram, Internal Clock Divided By 4
RM0090 General-purpose timers (TIM9 to TIM14) Figure 186. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 187. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 648: Preloaded)
General-purpose timers (TIM9 to TIM14) RM0090 Figure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 649: Figure 190. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0090 General-purpose timers (TIM9 to TIM14) Figure 190. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1( TIM9 and TIM1 This mode is selected when SMS=’111’...
Page 650: Figure 192. Control Circuit In External Clock Mode 1
General-purpose timers (TIM9 to TIM14) RM0090 Figure 192. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 19.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 651: Figure 194. Capture/Compare Channel 1 Main Circuit
RM0090 General-purpose timers (TIM9 to TIM14) Figure 194. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/compare preload register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/compare shadow register CC1S[0]...
Page 652 General-purpose timers (TIM9 to TIM14) RM0090 cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 653: Figure 196. Pwm Input Mode Timing
RM0090 General-purpose timers (TIM9 to TIM14) 19.3.6 PWM input mode (only for TIM9/12) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. •...
Page 654: Forced Output Mode
General-purpose timers (TIM9 to TIM14) RM0090 19.3.7 Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
Page 655: Figure 197. Output Compare Mode, Toggle On Oc1
RM0090 General-purpose timers (TIM9 to TIM14) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 197.
Page 656: Figure 198. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM9 to TIM14) RM0090 PWM edge-aligned mode In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’.
Page 657: Figure 199. Example Of One Pulse Mode
RM0090 General-purpose timers (TIM9 to TIM14) Figure 199. Example of one pulse mode. OC1REF TIM1_ARR TIM1_CCR1 DELAY PULSE For example you may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin.
Page 658: Figure 200. Control Circuit In Reset Mode
General-purpose timers (TIM9 to TIM14) RM0090 In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t min we can get.
Page 659: Figure 201. Control Circuit In Gated Mode
RM0090 General-purpose timers (TIM9 to TIM14) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’).
Page 660: Figure 202. Control Circuit In Trigger Mode
General-purpose timers (TIM9 to TIM14) RM0090 The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 202. Control circuit in trigger mode cnt_en Counter clock = ck_cnt = ck_psc Counter register 35 36 37 38 19.3.12...
Page 661: Tim9 And Tim12 Registers
RM0090 General-purpose timers (TIM9 to TIM14) 19.4 TIM9 and TIM12 registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 662 General-purpose timers (TIM9 to TIM14) RM0090 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow –...
Page 663: Tim9/12 Slave Mode Control Register (Timx_Smcr)
RM0090 General-purpose timers (TIM9 to TIM14) 19.4.2 TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 TS[2:0] SMS[2:0] Reserved Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 664: Table 100. Timx Internal Trigger Connection
General-purpose timers (TIM9 to TIM14) RM0090 Bits 6:4 TS: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2)
Page 665 RM0090 General-purpose timers (TIM9 to TIM14) Reset value: 0x0000 CC2IE CC1IE Reserved Bits 15:7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled.
Page 666: Tim9/12 Status Register (Timx_Sr)
General-purpose timers (TIM9 to TIM14) RM0090 19.4.4 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC2OF CC1OF CC2IF CC1IF Reserved Reserved Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input...
Page 667: Tim9/12 Event Generation Register (Timx_Egr)
RM0090 General-purpose timers (TIM9 to TIM14) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software.
Page 668 General-purpose timers (TIM9 to TIM14) RM0090 Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled.
Page 669: Tim9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0090 General-purpose timers (TIM9 to TIM14) 19.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes.
Page 670 General-purpose timers (TIM9 to TIM14) RM0090 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
Page 671 RM0090 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 672: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM9 to TIM14) RM0090 19.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC2NP CC2P CC2E CC1NP CC1P CC1E Reserved Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, must be kept at reset value.
Page 673: Table 101. Output Control Bit For Standard Ocx Channels
RM0090 General-purpose timers (TIM9 to TIM14) Table 101. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 674: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0090 19.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit).
Page 675: Table 102. Tim9/12 Register Map And Reset Values
RM0090 General-purpose timers (TIM9 to TIM14) 19.4.13 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described below: Table 102. TIM9/12 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reserved Reserved Reset value TIMx_SMCR TS[2:0] SMS[2:0] 0x08 Reserved...
Page 676 General-purpose timers (TIM9 to TIM14) RM0090 Table 102. TIM9/12 register map and reset values (continued) Offset Register TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value 0x3C to Reserved 0x4C Refer to Section: Memory map for the register boundary addresses. 676/1731 DocID018909 Rev 11...
Page 677: Tim10/11/13/14 Registers
RM0090 General-purpose timers (TIM9 to TIM14) 19.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 19.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 678: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 to TIM14) RM0090 19.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC1IE Reserved Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled...
Page 679: Tim10/11/13/14 Event Generation Register (Timx_Egr)
RM0090 General-purpose timers (TIM9 to TIM14) Bits 8:2 Reserved, must be kept at reset value. Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software.
Page 680: Tim10/11/13/14 Capture/Compare Mode Register
General-purpose timers (TIM9 to TIM14) RM0090 19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 681 RM0090 General-purpose timers (TIM9 to TIM14) Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
Page 682 General-purpose timers (TIM9 to TIM14) RM0090 Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 683: Table 103. Output Control Bit For Standard Ocx Channels
RM0090 General-purpose timers (TIM9 to TIM14) 19.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC1NP CC1P CC1E Reserved Res. Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared.
Page 684: Tim10/11/13/14 Counter (Timx_Cnt)
General-purpose timers (TIM9 to TIM14) RM0090 19.5.7 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 19.5.8 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 685: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
RM0090 General-purpose timers (TIM9 to TIM14) 19.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 686: Table 104. Tim10/11/13/14 Register Map And Reset Values
General-purpose timers (TIM9 to TIM14) RM0090 19.5.12 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the tables below: Table 104. TIM10/11/13/14 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reserved Reserved Reset value TIMx_SMCR 0x08 Reserved...
Page 687 RM0090 General-purpose timers (TIM9 to TIM14) Table 104. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_OR 0x50 Reserved Reset value Note: The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Page 688: Figure 203. Basic Timer Block Diagram
Basic timers (TIM6&TIM7) RM0090 Basic timers (TIM6&TIM7) This section applies to the whole STM32F4xx family, unless otherwise specified. 20.1 TIM6&TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC).
Page 689: Tim6&Tim7 Functional Description
RM0090 Basic timers (TIM6&TIM7) 20.3 TIM6&TIM7 functional description 20.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 690: Figure 204. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6&TIM7) RM0090 Figure 204. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 205.
Page 691: Figure 206. Counter Timing Diagram, Internal Clock Divided By 1
RM0090 Basic timers (TIM6&TIM7) register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent). When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit): •...
Page 692: Figure 208. Counter Timing Diagram, Internal Clock Divided By 4
Basic timers (TIM6&TIM7) RM0090 Figure 208. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 209. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register...
Page 693: Preloaded)
RM0090 Basic timers (TIM6&TIM7) Figure 211. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 694: Tim6&Tim7 Registers
Basic timers (TIM6&TIM7) RM0090 20.4 TIM6&TIM7 registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 695: Tim6&Tim7 Control Register 2 (Timx_Cr2)
RM0090 Basic timers (TIM6&TIM7) 20.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 696: Tim6&Tim7 Status Register (Timx_Sr)
Basic timers (TIM6&TIM7) RM0090 20.4.4 TIM6&TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Reserved rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
Page 697: Tim6&Tim7 Prescaler (Timx_Psc)
RM0090 Basic timers (TIM6&TIM7) 20.4.7 TIM6&TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded into the active prescaler register at each update event. 20.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 698: Table 105. Tim6&Tim7 Register Map And Reset Values
Basic timers (TIM6&TIM7) RM0090 20.4.9 TIM6&TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 105. TIM6&TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved Reset value 0x08...
Page 699: Independent Watchdog (Iwdg)
RM0090 Independent watchdog (IWDG) Independent watchdog (IWDG) This section applies to the whole STM32F4xx family, unless otherwise specified. 21.1 IWDG introduction The devices have two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.
Page 700: Table 106. Min/Max Iwdg Timeout Period At 32 Khz (Lsi)
Independent watchdog (IWDG) RM0090 with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0xAAAA). A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going.
Page 701: Iwdg Registers
RM0090 Independent watchdog (IWDG) 21.4 IWDG registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 21.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode)
Page 702: Reload Register (Iwdg_Rlr)
Independent watchdog (IWDG) RM0090 21.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RL[11:0] Reserved rw rw rw...
Page 703: Table 107. Iwdg Register Map And Reset Values
RM0090 Independent watchdog (IWDG) 21.4.5 IWDG register map The following table gives the IWDG register map and reset values. Table 107. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] Reserved 0x00 Reset value IWDG_PR PR[2:0] Reserved 0x04 Reset value IWDG_RLR RL[11:0] Reserved...
Page 704: Window Watchdog (Wwdg)
Window watchdog (WWDG) RM0090 Window watchdog (WWDG) This section applies to the whole STM32F4xx family, unless otherwise specified. 22.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence.
Page 705: Figure 214. Watchdog Block Diagram
RM0090 Window watchdog (WWDG) Figure 214. Watchdog block diagram The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.
Page 706: Figure 215. Window Watchdog Timing Diagram
Window watchdog (WWDG) RM0090 In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.
Page 707: Table 108. Minimum And Maximum Timeout Values At 30 Mhz
RM0090 Window watchdog (WWDG) As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 1 24000 4096 21,85ms Refer to the table below for the minimum and maximum values of the t WWDG Table 108.
Page 708: Wwdg Registers
Window watchdog (WWDG) RM0090 22.6 WWDG registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 22.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F...
Page 709: Configuration Register (Wwdg_Cfr)
RM0090 Window watchdog (WWDG) 22.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Reserved WDGTB[1:0] W[6:0] Reserved Bit 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
Page 710: Table 109. Wwdg Register Map And Reset Values
Window watchdog (WWDG) RM0090 22.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 109. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reserved Reset value WWDG_CFR W[6:0] 0x04 Reserved Reset value WWDG_SR 0x08 Reserved...
Page 711: Table 110. Number Of Cycles Required To Process Each 128-Bit Block
RM0090 Cryptographic processor (CRYP) Cryptographic processor (CRYP) This section applies to STM32F415/417xx and STM32F43xxx devices. 23.1 CRYP introduction The cryptographic processor can be used to both encipher and decipher data using the DES, Triple-DES or AES (128, 192, or 256) algorithms. It is a fully compliant implementation of the following standards: •...
Page 712 Cryptographic processor (CRYP) RM0090 Table 111. Number of cycles required to process each 128-bit block (STM32F43xxx) 192b 256b • DES/TDES – Direct implementation of simple DES algorithms (a single key, K1, is used) – Supports the ECB and CBC chaining algorithms –...
Page 713: Figure 216. Block Diagram (Stm32F415/417Xx)
RM0090 Cryptographic processor (CRYP) 23.3 CRYP functional description The cryptographic processor implements a Triple-DES (TDES, that also supports DES) core and an AES cryptographic core. Section 23.3.1 Section 23.3.2 provide details on these cores. Since the TDES and the AES algorithms use block ciphers, incomplete input data blocks have to be padded prior to encryption (extra bits should be appended to the trailing end of the data string).
Page 714: Figure 217. Block Diagram (Stm32F43Xxx)
Cryptographic processor (CRYP) RM0090 Figure 217. Block diagram (STM32F43xxx) 23.3.1 DES/TDES cryptographic core The DES/Triple-DES cryptographic core consists of three components: • The DES algorithm (DEA) • Multiple keys (1 for the DES algorithm, 1 to 3 for the TDES algorithm) •...
Page 715 RM0090 Cryptographic processor (CRYP) The TDES allows three different keying options: • Three independent keys The first option specifies that all the keys are independent, that is, K1, K2 and K3 are independent. FIPS PUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to this option as the Keying Option 1 and, to the TDES as 3-key TDES.
Page 716: Figure 218. Des/Tdes-Ecb Mode Encryption
Cryptographic processor (CRYP) RM0090 Figure 218. DES/TDES-ECB mode encryption 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. Figure 219. DES/TDES-ECB mode decryption 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. 716/1731 DocID018909 Rev 11...
Page 717 RM0090 Cryptographic processor (CRYP) DES and TDES Cipher block chaining (DES/TDES-CBC) mode • DES/TDES-CBC mode encryption Figure 220 illustrates the DES and Triple-DES Cipher block chaining (DES/TDES- CBC) mode encryption. This mode begins by dividing a plaintext message into 64-bit data blocks.
Page 718: Figure 220. Des/Tdes-Cbc Mode Encryption
Cryptographic processor (CRYP) RM0090 Figure 220. DES/TDES-CBC mode encryption 1. K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: initialization vectors. 718/1731 DocID018909 Rev 11...
Page 719: Figure 221. Des/Tdes-Cbc Mode Decryption
RM0090 Cryptographic processor (CRYP) Figure 221. DES/TDES-CBC mode decryption 1. K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: initialization vectors. 23.3.2 AES cryptographic core The AES cryptographic core consists of three components: •...
Page 720: Figure 222. Aes-Ecb Mode Encryption
Cryptographic processor (CRYP) RM0090 ECB decryption, AES-CBC encryption and AES-CBC decryption.This reference manual only gives a brief explanation of each mode. AES Electronic codebook (AES-ECB) mode • AES-ECB mode encryption Figure 222 illustrates the AES Electronic codebook (AES-ECB) mode encryption. In AES-ECB encryption, a 128- bit plaintext data block (P) is used after bit/byte/half- word swapping (refer to Section 23.3.3: Data type on page...
Page 721: Figure 223. Aes-Ecb Mode Decryption
RM0090 Cryptographic processor (CRYP) Figure 223. AES-ECB mode decryption 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. 2. If Key size = 128 => Key = [K3 K2]. If Key size = 192 => Key = [K3 K2 K1] If Key size = 256 =>...
Page 722: Figure 224. Aes-Cbc Mode Encryption
Cryptographic processor (CRYP) RM0090 block of data.) The AES-CBC decryption process continues in this manner until the last complete ciphertext block has been decrypted. Ciphertext representing a partial data block must be decrypted in a manner specified for the application. Figure 224.
Page 723: Figure 225. Aes-Cbc Mode Decryption
RM0090 Cryptographic processor (CRYP) Figure 225. AES-CBC mode decryption 1. K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: Initialization vectors. 2. IVx=[IVxR IVxL], R=right, L=left. 3.
Page 724: Figure 226. Aes-Ctr Mode Encryption
Cryptographic processor (CRYP) RM0090 Figure 226 Figure 227 illustrate AES-CTR encryption and decryption, respectively. Figure 226. AES-CTR mode encryption 1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when encoding);...
Page 725: Figure 227. Aes-Ctr Mode Decryption
RM0090 Cryptographic processor (CRYP) Figure 227. AES-CTR mode decryption 1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when encoding);...
Page 726 Cryptographic processor (CRYP) RM0090 AES Galois/counter mode (GCM) The AES Galois/counter mode (GCM) allows encrypting and authenticating the plaintext, and generating the correspondent ciphertext and tag (also known as message authentication code or message integrity check). This algorithm is based on AES counter mode to ensure confidentiality.
Page 727 RM0090 Cryptographic processor (CRYP) GCM init phase During this first step, the HASH key is calculated and saved internally to be used for processing all the blocks. It is recommended to follow the sequence below: Make sure that the cryptographic processor is disabled by clearing the CRYPEN bit in the CRYP_CR register.
Page 728 Cryptographic processor (CRYP) RM0090 OFNE/OFFU flag of the CRYP_DOUT register can be monitored to check if the output FIFO is not empty. Repeat the previous step until all payload blocks have been encrypted or decrypted. Alternatively, DMA could be used. GCM final phase This step generates the authentication tag: Configure GCM_CCMPH[1:0] to ‘11’...
Page 729 RM0090 Cryptographic processor (CRYP) Note: The header part must precede the payload and the two parts cannot be mixed together. In CCM mode, 4 steps are required to perform and encryption or decryption: CCM init phase In this first step, the B0 packet of the CCM message (1st packet) is programmed into the CRYP_DIN register.
Page 730: Data Type
Cryptographic processor (CRYP) RM0090 Note: The first block B1 must be formatted with the header length. This task should be handled by software. Once all header data have been supplied, wait until the BUSY flag is cleared. CCM payload phase (encryption/decryption) This step must be performed after the CCM header phase.
Page 731: Table 112. Data Types
RM0090 Cryptographic processor (CRYP) The system memory organization is little-endian: whatever the data type (bit, byte, 16-bit half-word, 32-bit word) used, the least-significant data occupy the lowest address locations. A bit, byte, or half-word swapping operation (depending on the kind of data to be encrypted) therefore has to be performed on the data read from the IN FIFO before they enter the CRYP processor.
Page 732: Figure 229. 64-Bit Block Construction According To Datatype
Cryptographic processor (CRYP) RM0090 cryptographic algorithm (for the AES, the block length is four 32-bit words, but swapping only takes place at word level, so it is identical to the one described here for the TDES). Note: The same swapping is performed between the IN FIFO and the CRYP data block, and between the CRYP data block and the OUT FIFO.
Page 733: Initialization Vectors - Cryp_Iv0...1(L/R)
RM0090 Cryptographic processor (CRYP) 23.3.4 Initialization vectors - CRYP_IV0...1(L/R) Initialization vectors are considered as two 64-bit data items. They therefore do not have the same data format and representation in system memory as plaintext or cypher data, and they are not affected by the DATATYPE value. Initialization vectors are defined by two consecutive 32-bit words, CRYP_IVL (left part, noted as bits IV1...32) and CRYP_IVR (right part, noted as bits IV33...64).
Page 734: Figure 230. Initialization Vectors Use In The Tdes-Cbc Encryption
Cryptographic processor (CRYP) RM0090 Figure 230. Initialization vectors use in the TDES-CBC encryption 23.3.5 CRYP busy state When there is enough data in the input FIFO (at least 2 words for the DES or TDES algorithm mode, 4 words for the AES algorithm mode) and enough free-space in the output FIFO (at least 2 (DES/TDES) or 4 (AES) word locations), and when the bit CRYPEN = 1 in the CRYP_CR register, then the cryptographic processor automatically starts an encryption or decryption process (according to the value of the ALGODIR bit in the CRYP_CR...
Page 735: Procedure To Perform An Encryption Or A Decryption
RM0090 Cryptographic processor (CRYP) the CBC, CTR mode, the initialization vectors CRYP_IVx(L/R)R (x = 0..3) are updated as well. A write operation to the key registers (CRYP_Kx(L/R)R, x = 0..3), the initialization registers (CRYP_IVx(L/R)R, x = 0..3), or to bits [9:2] in the CRYP_CR register are ignored when the cryptographic processor is busy (bit BUSY = 1b in the CRYP_SR register), and the registers are not modified.
Page 736: Context Swapping
Cryptographic processor (CRYP) RM0090 the DES/TDES. The DMA should be configured to set an interrupt on transfer completion of the output data to indicate that the processing is finished. Enable the cryptographic processor by writing the CRYPEN bit to 1. Enable the DMA requests by setting the DIEN and DOEN bits in the CRYP_DMACR register.
Page 737 RM0090 Cryptographic processor (CRYP) Case of the AES and DES Context saving Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR register. Wait until both the IN and OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR register) and the BUSY bit is cleared.
Page 738: Cryp Interrupts
Cryptographic processor (CRYP) RM0090 the IN FIFO that have not been processed and save them in the memory until the FIFO is empty. Note: In GCM/GMAC or CCM/CMAC mode, bits [17:16] of the CRYP_CR register should also be saved. Configure and execute the other processing. Context restoration Configure the processor as in Section 23.3.6: Procedure to perform an encryption...
Page 739: Figure 231. Cryp Interrupt Mapping Diagram
RM0090 Cryptographic processor (CRYP) Figure 231. CRYP interrupt mapping diagram 23.5 CRYP DMA interface The cryptographic processor provides an interface to connect to the DMA controller. The DMA operation is controlled through the CRYP DMA control register, CRYP_DMACR. The burst and single transfer request signals are not mutually exclusive. They can both be asserted at the same time.
Page 740 Cryptographic processor (CRYP) RM0090 Bits 31:18 Reserved, must be kept at reset value Bits 17:16 Reserved, must be kept at reset value Bit 15 CRYPEN: Cryptographic processor enable 0: CRYP processor is disabled 1: CRYP processor is enabled Note: The CRYPEN bit is automatically cleared by hardware when the key preparation process ends (ALGOMODE=111b) or GCM_CCM init Phase Bit 14 FFLUSH: FIFO flush When CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is...
Page 741: Cryp Control Register (Cryp_Cr) For Stm32F415/417Xx
RM0090 Cryptographic processor (CRYP) Bits 5:3 ALGOMODE[2:0]: Algorithm mode 000: TDES-ECB (triple-DES Electronic codebook): no feedback between blocks of data. Initialization vectors (CRYP_IV0(L/R)) are not used, three key vectors (K1, K2, and K3) are used (K0 is not used). 001: TDES-CBC (triple-DES Cipher block chaining): output block is XORed with the subsequent input block before its entry into the algorithm.
Page 742 Cryptographic processor (CRYP) RM0090 ALGO MODE GCM_CCMPH Reserved Res. CRYPEN FFLUSH KEYSIZE DATATYPE ALGOMODE[2:0] ALGODIR Reserved Reserved Bits 31:20 Reserved, forced by hardware to 0. Bit 18 Reserved, forced by hardware to 0. Bits 17:16 GCM_CCMPH[1:0]: no effect if “GCM or CCM algorithm” is not set 00: GCM_CCM init Phase 01: GCM_CCM header phase 10: GCM_CCM payload phase...
Page 743 RM0090 Cryptographic processor (CRYP) Bits 19 and 5:3 ALGOMODE[3:0]: Algorithm mode 0000: TDES-ECB (triple-DES Electronic codebook): no feedback between blocks of data. Initialization vectors (CRYP_IV0(L/R)) are not used, three key vectors (K1, K2, and K3) are used (K0 is not used). 0001: TDES-CBC (triple-DES Cipher block chaining): output block is XORed with the subsequent input block before its entry into the algorithm.
Page 744: Cryp Status Register (Cryp_Sr)
Cryptographic processor (CRYP) RM0090 23.6.3 CRYP status register (CRYP_SR) Address offset: 0x04 Reset value: 0x0000 0003 Reserved BUSY OFFU OFNE IFNF IFEM Reserved Bits 31:5 Reserved, must be kept at reset value Bit 4 BUSY: Busy bit 0: The CRYP Core is not processing any data. The reason is either that: –...
Page 745: Cryp Data Input Register (Cryp_Din)
RM0090 Cryptographic processor (CRYP) 23.6.4 CRYP data input register (CRYP_DIN) Address offset: 0x08 Reset value: 0x0000 0000 The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter up to four 64-bit (TDES) or two 128-bit (AES) plaintext (when encrypting) or ciphertext (when decrypting) blocks into the input FIFO, one 32-bit word at a time.
Page 746: Cryp Data Output Register (Cryp_Dout)
Cryptographic processor (CRYP) RM0090 23.6.5 CRYP data output register (CRYP_DOUT) Address offset: 0x0C Reset value: 0x0000 0000 The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve up to four 64-bit (TDES mode) or two 128-bit (AES mode) ciphertext (when encrypting) or plaintext (when decrypting) blocks from the output FIFO, one 32-bit word at a time.
Page 747: Cryp Dma Control Register (Cryp_Dmacr)
RM0090 Cryptographic processor (CRYP) 23.6.6 CRYP DMA control register (CRYP_DMACR) Address offset: 0x10 Reset value: 0x0000 0000 Reserved DOEN DIEN Reserved Bits 31:2 Reserved, must be kept at reset value Bit 1 DOEN: DMA output enable 0: DMA for outgoing data transfer is disabled 1: DMA for outgoing data transfer is enabled Bit 0 DIEN: DMA input enable 0: DMA for incoming data transfer is disabled...
Page 748: Cryp Raw Interrupt Status Register (Cryp_Risr)
Cryptographic processor (CRYP) RM0090 23.6.8 CRYP raw interrupt status register (CRYP_RISR) Address offset: 0x18 Reset value: 0x0000 0001 The CRYP_RISR register is the raw interrupt status register. It is a read-only register. On a read, this register gives the current raw status of the corresponding interrupt prior to masking.
Page 749: Cryp Key Registers (Cryp_K0...3(L/R)R)
RM0090 Cryptographic processor (CRYP) Bits 31:2 Reserved, must be kept at reset value Bit 1 OUTMIS: Output FIFO service masked interrupt status Gives the interrupt state after masking of the output FIFO service interrupt. 0: Interrupt not pending 1: Interrupt pending Bit 0 INMIS: Input FIFO service masked interrupt status Gives the interrupt state after masking of the input FIFO service interrupt.
Page 750 Cryptographic processor (CRYP) RM0090 CRYP_K1LR (address offset: 0x28) k1.1 k1.2 k1.3 k1.4 k1.5 k1.6 k1.7 k1.8 k1.9 k1.10 k1.11 k1.12 k1.13 k1.14 k1.15 k1.16 b191 b190 b189 b188 b187 b186 b185 b184 b183 b182 b181 b180 b179 b178 b177 b176 k1.17 k1.18 k1.19...
Page 751: Cryp Initialization Vector Registers (Cryp_Iv0...1(L/R)R)
RM0090 Cryptographic processor (CRYP) CRYP_K3RR (address offset: 0x3C) k3.33 k3.34 k3.35 k3.36 k3.37 k3.38 k3.39 k3.40 k3.41 k3.42 k3.43 k3.44 k3.45 k3.46 k3.47 k3.48 k3.49 k3.50 k3.51 k3.52 k3.53 k3.54 k3.55 k3.56 k3.57 k3.58 k3.59 k3.60 k3.61 k3.62 k3.63 k3.64 Note: Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).
Page 752 Cryptographic processor (CRYP) RM0090 CRYP_IV1LR (address offset: 0x48) IV64 IV65 IV66 IV67 IV68 IV69 IV70 IV71 IV72 IV73 IV74 IV75 IV76 IV77 IV78 IV79 IV80 IV81 IV82 IV83 IV84 IV85 IV86 IV87 IV88 IV89 IV90 IV91 IV92 IV93 IV94 IV95 CRYP_IV1RR (address offset: 0x4C) IV96 IV97...
Page 753: Cryp Context Swap Registers (Cryp_Csgcmccm0..7R And Cryp_Csgcm0..7R) For Stm32F42Xxx And Stm32F43Xxx
RM0090 Cryptographic processor (CRYP) 23.6.12 CRYP context swap registers (CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx Address offset: • CRYP_CSGCMCCM0..7: 0x050 to 0x06C: used for GCM/GMAC or CCM/CMAC alogrithm only • CRYP_CSGCM0..7: 0x070 to 0x08C: used for GCM/GMAC algorithm only Reset value: 0x0000 0000 These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM/CMAC algorithm is selected.
Page 754: Table 113. Cryp Register Map And Reset Values For Stm32F415/417Xx
Cryptographic processor (CRYP) RM0090 23.6.13 CRYP register map Table 113. CRYP register map and reset values for STM32F415/417xx Register Offset name and reset value CRYP_CR 0x00 Reserved Reserved 0x00 Reset value 0 0 0 0 0 0 0 0 CRYP_SR 0x04 Reserved Reset value...
Page 755: Table 114. Cryp Register Map And Reset Values For Stm32F43Xxx
RM0090 Cryptographic processor (CRYP) Table 113. CRYP register map and reset values for STM32F415/417xx (continued) Register Offset name and reset value CRYP_IV0RR CRYP_IV0RR 0x44 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_IV1LR CRYP_IV1LR 0x48...
Page 756 Cryptographic processor (CRYP) RM0090 Table 114. CRYP register map and reset values for STM32F43xxx (continued) Register name Offset reset value CRYP_MISR 0x1C Reserved Reset value CRYP_K0LR CRYP_K0LR 0x20 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_K0RR CRYP_K0RR 0x24...
Page 757 RM0090 Cryptographic processor (CRYP) Table 114. CRYP register map and reset values for STM32F43xxx (continued) Register name Offset reset value CRYP_ CSGCMCCM CRYP_CSGCMCCM4R 0x60 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_ CSGCMCCM CRYP_CSGCMCCM5R...
Page 758: Figure 232. Block Diagram
Random number generator (RNG) RM0090 Random number generator (RNG) This section applies to the whole STM32F4xx family, unless otherwise specified. 24.1 RNG introduction The RNG processor is a random number generator, based on a continuous analog noise, that provides a random 32-bit value to the host when read. The RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.
Page 759: Operation
RM0090 Random number generator (RNG) The analog circuit is made of several ring oscillators whose outputs are XORed to generate the seeds. The RNG_LFSR is clocked by a dedicated clock (RNG_CLK) at a constant frequency, so that the quality of the random number is independent of the HCLK frequency. The contents of the RNG_LFSR are transferred into the data register (RNG_DR) when a significant number of seeds have been introduced into the RNG_LFSR.
Page 760: Rng Control Register (Rng_Cr)
Random number generator (RNG) RM0090 24.4.1 RNG control register (RNG_CR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved RNGEN Reserved Reserved Bits 31:4 Reserved, must be kept at reset value Bit 3 IE: Interrupt enable 0: RNG Interrupt is disabled 1: RNG Interrupt is enabled.
Page 761: Rng Data Register (Rng_Dr)
RM0090 Random number generator (RNG) Bit 2 SECS: Seed error current status 0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1: One of the following faulty sequences has been detected: –...
Page 762: Table 115. Rng Register Map And Reset Map
Random number generator (RNG) RM0090 24.4.4 RNG register map Table 115 gives the RNG register map and reset values. Table 115. RNG register map and reset map Register size Register name Offset reset value RNG_CR 0x00 Reserved 0x0000000 RNG_SR 0x04 Reserved 0x0000000 RNG_DR...
Page 763: Hash Introduction
RM0090 Hash processor (HASH) Hash processor (HASH) This section applies to STM32F415/417xx and STM32F43xxx devices. 25.1 HASH introduction The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.
Page 764: Figure 233. Block Diagram For Stm32F415/417Xx
Hash processor (HASH) RM0090 25.3 HASH functional description Figure 1 shows the block diagram of the hash processor. Figure 233. Block diagram for STM32F415/417xx 764/1731 DocID018909 Rev 11...
Page 765: Figure 234. Block Diagram For Stm32F43Xxx
RM0090 Hash processor (HASH) Figure 234. Block diagram for STM32F43xxx The FIPS PUB 180-2 standard and the IETF RFC 1321 publication specify the SHA-1, SHA- 224 and SHA-256 and MD5 secure hash algorithms, respectively, for computing a condensed representation of a message or data file. When a message of any length below bits is provided on input, the SHA-1, SHA-224 and SHA-256 and MD5 produce respective a 160-bit, 224 bit, 256 bit and 128-bit output string, respectively, called a message digest.
Page 766: Duration Of The Processing
Hash processor (HASH) RM0090 has length 0). You can consider that 32 bits of this bit string forms a 32-bit word. Note that the FIPS PUB 180-1 standard uses the convention that bit strings grow from left to right, and bits can be grouped as bytes (8 bits) or words (32 bits) (but some implementations also use half-words (16 bits), and implicitly, uses the big-endian byte (half-word) ordering.
Page 767: Figure 235. Bit, Byte And Half-Word Swapping
RM0090 Hash processor (HASH) Figure 235. Bit, byte and half-word swapping DocID018909 Rev 11 767/1731...
Page 768: Message Digest Computing
Hash processor (HASH) RM0090 The least significant bit of the message has to be at position 0 (right) in the first word entered into the hash processor, the 32nd bit of the bit string has to be at position 0 in the second word entered into the hash processor and so on.
Page 769: Message Padding
RM0090 Hash processor (HASH) Once this is done, writing into HASH_STR with bit DCAL = 1 starts the processing of the last entered block of message by the hash processor. This processing consists in: • Automatically performing the message padding operation: the purpose of this operation is to make the total length of a padded message a multiple of 512.
Page 770: Hash Operation
Hash processor (HASH) RM0090 value 0x0000 0001. Then an all zero word (0x0000 0000) is added and the message length in a two-word representation, to get a block of 16 x 32-bit words. The HASH computing is performed, and the message digest is then available in the HASH_Hx registers (x = 0...4) for the SHA-1 algorithm.
Page 771: Context Swapping
RM0090 Hash processor (HASH) The block is initialized by writing the INIT bit to ‘1’ with the MODE bit at ‘1’ and the ALGO bits set to the value corresponding to the desired algorithm. The LKEY bit must also be set during this phase if the key being used is longer than 64 bytes (in this case, the HMAC specifications specify that the hash of the key should be used in place of the real key).
Page 772 Hash processor (HASH) RM0090 Procedure where the data are loaded by software The context can be saved only when no block is currently being processed. That is, you must wait for DINIS = 1 (the last block has been processed and the input FIFO is empty) or NBW ≠...
Page 773: Figure 236. Hash Interrupt Mapping Diagram
RM0090 Hash processor (HASH) 25.3.8 HASH interrupt There are two individual maskable interrupt sources generated by the HASH processor. They are connected to the same interrupt vector. You can enable or disable the interrupt sources individually by changing the mask bits in the HASH_IMR register.
Page 774 Hash processor (HASH) RM0090 Bit 12 DINNE: DIN not empty This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1.
Page 775 RM0090 Hash processor (HASH) Bit 3 DMAE: DMA enable 0: DMA transfers disabled 1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is ready to receive data. Note: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal count signal (while transferring the last data of the message).
Page 776: Hash Control Register (Hash_Cr) For Stm32F43Xxx
Hash processor (HASH) RM0090 25.4.2 HASH control register (HASH_CR) for STM32F43xxx Address offset: 0x00 Reset value: 0x0000 0000 ALGO[1] LKEY Reserved MDMAT DINNE ALGO[0] MODE DATATYPE DMAE INIT Reserved Reserved Bits 31:19 Reserved, forced by hardware to 0. Bit 17 Reserved, forced by hardware to 0. Bit 16 LKEY: Long key selection This bit selects between short key (≤...
Page 777 RM0090 Hash processor (HASH) Bits 11:8 NBW: Number of words already pushed This bitfield reflects the number of words in the message that have already been pushed into the IN FIFO. NBW increments (+1) when a write access is performed to the HASH_DIN register while DINNE = 1.
Page 778 Hash processor (HASH) RM0090 Bit 3 DMAE: DMA enable 0: DMA transfers disabled 1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is ready to receive data. Note: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal count signal (while transferring the last data of the message).
Page 779: Hash Data Input Register (Hash_Din)
RM0090 Hash processor (HASH) 25.4.3 HASH data input register (HASH_DIN) Address offset: 0x04 Reset value: 0x0000 0000 HASH_DIN is the data input register. It is 32-bit wide. It is used to enter the message by blocks of 512 bits. When the HASH_DIN register is written to, the value presented on the AHB databus is ‘pushed’...
Page 780: Hash Start Register (Hash_Str)
Hash processor (HASH) RM0090 25.4.4 HASH start register (HASH_STR) Address offset: 0x08 Reset value: 0x0000 0000 The HASH_STR register has two functions: • It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written into the HASH_DIN register) •...
Page 781: Hash Digest Registers (Hash_Hr0..4/5/6/7)
RM0090 Hash processor (HASH) 25.4.5 HASH digest registers (HASH_HR0..4/5/6/7) Address offset: 0x0C to 0x1C (STM32F415/417xx), plus 0x310 to 0x32C (STM32F43xxx) Reset value: 0x0000 0000 These registers contain the message digest result named as: H0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description Note that in this case, the HASH_H5 to HASH_H7 register is not used, and is read as zero.
Page 782 Hash processor (HASH) RM0090 HASH_HR3 Address offset: 0x18 and 0x31C HASH_HR4 Address offset: 0x1C and 0x320 HASH_HR5 Address offset: 0x324 HASH_HR6 Address offset: 0x328 HASH_HR7 Address offset: 0x32C 782/1731 DocID018909 Rev 11...
Page 783: Hash Interrupt Enable Register (Hash_Imr)
RM0090 Hash processor (HASH) Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these registers assume their reset values. 25.4.6 HASH interrupt enable register (HASH_IMR) Address offset: 0x20 Reset value: 0x0000 0000 Reserved DCIE DINIE...
Page 784: Hash Status Register (Hash_Sr)
Hash processor (HASH) RM0090 25.4.7 HASH status register (HASH_SR) Address offset: 0x24 Reset value: 0x0000 0001 Reserved BUSY DMAS DCIS DINIS Reserved rc_w0 rc_w0 Bits 31:4 Reserved, forced by hardware to 0. Bit 3 BUSY: Busy bit 0: No block is currently being processed 1: The hash core is processing a block of data Bit 2 DMAS: DMA Status This bit provides information on the DMA interface activity.
Page 785: Hash Context Swap Registers (Hash_Csrx)
RM0090 Hash processor (HASH) 25.4.8 HASH context swap registers (HASH_CSRx) Address offset: 0x0F8 to 0x1C0 • For HASH_CSR0 register: Reset value is 0x0000 0002. • For others registers: Reset value is 0x0000 0000 , except for STM32F43xxx devices where the HASH_CSR2 register reset value is 0x2000 0000 Additional registers are available from 0x1C1 to 0x1CC on STM32F43xxx: •...
Page 786: Table 116. Hash Register Map And Reset Values On Stm32F415/417Xx
Hash processor (HASH) RM0090 25.4.9 HASH register map Table 9 gives the summary HASH register map and reset values. Table 116. HASH register map and reset values on STM32F415/417xx Register size Register Offset name reset value HASH_CR 0x00 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 HASH_DIN DATAIN...
Page 787: Table 117. Hash Register Map And Reset Values On Stm32F43Xxx
RM0090 Hash processor (HASH) Table 116. HASH register map and reset values on STM32F415/417xx (continued) Register size Register Offset name reset value HASH_HR1 0x314 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR2 0x318 Reset value...
Page 788 Hash processor (HASH) RM0090 Table 117. HASH register map and reset values on STM32F43xxx (continued) Register size Register Offse name reset value HASH_IMR Reserved 0x20 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_SR 0x24 Reserved...
Page 789: Introduction
RM0090 Real-time clock (RTC) Real-time clock (RTC) This section applies to the whole STM32F4xx family, unless otherwise specified. 26.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability.
Page 790: Rtc Main Features
Real-time clock (RTC) RM0090 26.2 RTC main features The RTC unit main features are the following (see Figure 237: RTC block diagram): • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. •...
Page 791: Figure 237. Rtc Block Diagram
RM0090 Real-time clock (RTC) Figure 237. RTC block diagram 1. On STM32F4xx devices, the RTC_AF1 and RTC_AF2 alternate functions are connected to PC13 and PI8, respectively. 26.3 RTC functional description 26.3.1 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock.
Page 792: Real-Time Clock And Calendar
Real-time clock (RTC) RM0090 The minimum division factor is 1 and the maximum division factor is 2 This corresponds to a maximum input frequency of around 4 MHz. is given by the following formula: ck_apre RTCCLK -------------------------------------- - CK_APRE PREDIV_A The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter.
Page 793: Periodic Auto-Wakeup
RM0090 Real-time clock (RTC) Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR and RTC_ALRMBR registers, and through the MASKSSx bits of the RTC_ALRMASSR and RTC_ALRMBSSR registers. The alarm interrupts are enabled through the ALRAIE and ALRBIE bits in the RTC_CR register. Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the RTC_ALARM output.
Page 794: Rtc Initialization And Configuration
Real-time clock (RTC) RM0090 26.3.5 RTC initialization and configuration RTC register access The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD=0. RTC register write protection After system reset, the RTC registers are protected against parasitic write access with the DBP bit of the PWR power control register (PWR_CR).
Page 795: Reading The Calendar
RM0090 Real-time clock (RTC) Daylight saving time The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register. Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure.
Page 796: Resetting The Rtc
Real-time clock (RTC) RM0090 RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers.
Page 797: Rtc Reference Clock Detection
RM0090 Real-time clock (RTC) In addition, the RTC keeps on running under system reset if the reset source is different from a backup domain reset. When a backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values. 26.3.8 RTC synchronization The RTC can be synchronized to a remote clock with a high degree of precision.
Page 798: Rtc Coarse Digital Calibration
Real-time clock (RTC) RM0090 The RTC detects if the reference clock source is present by using the 256 Hz clock (ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time window around each of the calendar updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge.
Page 799: Rtc Smooth Digital Calibration
RM0090 Real-time clock (RTC) Negative calibration can be performed with a resolution of about 2 ppm while positive calibration can be performed with a resolution of about 4 ppm. The maximum calibration ranges from −63 ppm to 126 ppm. The calibration can be performed either on the LSE or on the HSE clock. Caution: Digital calibration may not work correctly if PREDIV_A <...
Page 800 Real-time clock (RTC) RM0090 While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP to ‘1’ effectively inserts an extra RTCCLK pulse every 2 RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle.
Page 801: Timestamp Function
RM0090 Real-time clock (RTC) However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration. •...
Page 802: Tamper Detection
Real-time clock (RTC) RM0090 same moment, the application must not write ‘0’ into TSF bit unless it has already read it to ‘1’. Optionally, a tamper event can cause a timestamp to be recorded. See the description of the TAMPTS control bit in Section 26.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR).
Page 803: Calibration Clock Output
RM0090 Real-time clock (RTC) Caution: To avoid losing tamper detection events, the signal used for edge detection is logically ANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the TAMPERx pin is enabled. •...
Page 804: Table 118. Effect Of Low-Power Modes On Rtc
Real-time clock (RTC) RM0090 The RTC_CALIB output is not impacted by the calibration value programmed in RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges. If COSEL is set and (PREDIV_S+1) is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), the RTC_CALIB frequency is f /(256 * (PREDIV_A+1)).
Page 805: Table 119. Interrupt Control Bits
RM0090 Real-time clock (RTC) 26.5 RTC interrupts All RTC interrupts are connected to the EXTI controller. To enable the RTC Alarm interrupt, the following sequence is required: Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity.
Page 806: Rtc Registers
Real-time clock (RTC) RM0090 26.6 RTC registers Refer to Section: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 26.6.1 RTC time register (RTC_TR) The RTC_TR is the calendar time shadow register.
Page 807: Rtc Date Register (Rtc_Dr)
RM0090 Real-time clock (RTC) 26.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 794 Reading the calendar on page 795.
Page 808: Rtc Control Register (Rtc_Cr)
Real-time clock (RTC) RM0090 26.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected OSEL[1:0] COSEL SUB1H ADD1H Reserved BYPS TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE REFCKON TSEDGE WUCKSEL[2:0] Bits 31:24 Reserved, must be kept at reset value. Bit 23 COE: Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled...
Page 809 RM0090 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Timestamp interrupt enable 0: Timestamp Interrupt disable 1: Timestamp Interrupt enable...
Page 810: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0090 Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz) 0: Reference clock detection disabled 1: Reference clock detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Timestamp event active edge 0: TIMESTAMP rising edge generates a timestamp event 1: TIMESTAMP falling edge generates a timestamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection...
Page 811 RM0090 Real-time clock (RTC) Bits 31:17 Reserved Bit 16 RECALPF: Recalibration pending Flag The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to ‘0’.
Page 812 Real-time clock (RTC) RM0090 Bit 5 RSF: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1).
Page 813: Rtc Prescaler Register (Rtc_Prer)
RM0090 Real-time clock (RTC) 26.6.5 RTC prescaler register (RTC_PRER) Address offset: 0x10 Backup domain reset value: 0x007F 00FF System reset: not affected PREDIV_A[6:0] Reserved PREDIV_S[14:0] Res. Bits 31:24 Reserved Bit 23 Reserved, must be kept at reset value. Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value.
Page 814: Rtc Calibration Register (Rtc_Calibr)
Real-time clock (RTC) RM0090 Bits 31:16 Reserved Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer.
Page 815: Rtc Alarm A Register (Rtc_Alrmar)
RM0090 Real-time clock (RTC) Note: This register can be written in initialization mode only (RTC_ISR/INITF = ‘1’). This register is write protected. The write access procedure is described in RTC register write protection on page 794. 26.6.8 RTC alarm A register (RTC_ALRMAR) Address offset: 0x1C Backup domain reset value: 0x0000 0000 System reset: not affected...
Page 816: Rtc Alarm B Register (Rtc_Alrmbr)
Real-time clock (RTC) RM0090 Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 794.
Page 817: Rtc Write Protection Register (Rtc_Wpr)
RM0090 Real-time clock (RTC) Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 794.
Page 818: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0090 26.6.12 RTC shift control register (RTC_SHIFTR) Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Reserved Res. SUBFS[14:0] Bit 31 ADD1S: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero.
Page 819: Rtc Time Stamp Date Register (Rtc_Tsdr)
RM0090 Real-time clock (RTC) MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] Res. Res. Bits 31:23 Reserved, must be kept at reset value. Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format. Bits 19:16 HU[3:0]: Hour units in BCD format. Bit 15 Reserved, must be kept at reset value.
Page 820: Rtc Timestamp Sub Second Register (Rtc_Tsssr)
Real-time clock (RTC) RM0090 26.6.15 RTC timestamp sub second register (RTC_TSSSR) Address offset: 0x38 Backup domain reset value: 0x0000 0000 System reset: not affected Reserved SS[15:0] Bits 31:16 Reserved Bits 15:0 SS: Sub second value SS[15:0] is the value of the synchronous prescaler’s counter when the timestamp event occurred.
Page 821 RM0090 Real-time clock (RTC) Bits 31:16 Reserved Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 2 pulses (frequency increased by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution.
Page 822 Real-time clock (RTC) RM0090 26.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR) Address offset: 0x40 Backup domain reset value: 0x0000 0000 System reset: not affected ALARMOUT TSIN TAMP1 TYPE INSEL Reserved TAMP- TAMP- TAMPT TAMP2 TAMP2 TAMP1 TAMP1 TAMPFLT[1:0] TAMPFREQ[2:0] TAMPIE PUDIS...
Page 823 RM0090 Real-time clock (RTC) Bits 12:11 TAMPFLT[1:0]: Tamper filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) necessary to activate a Tamper event. TAMPFLT is valid for each of the tamper inputs. 0x0: Tamper is activated on edge of tamper input transitions to the active level (no internal pull-up on tamper input).
Page 824: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
Real-time clock (RTC) RM0090 Bit 1 TAMP1TRG: Active level for tamper 1 if TAMPFLT != 00 0: TAMPER1 staying low triggers a tamper detection event. 1: TAMPER1 staying high triggers a tamper detection event. if TAMPFLT = 00: 0: TAMPER1 rising edge triggers a tamper detection event. 1: TAMPER1 falling edge triggers a tamper detection event.
Page 825: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
RM0090 Real-time clock (RTC) Note: This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 794 26.6.19 RTC alarm B sub second register (RTC_ALRMBSSR) Address offset: 0x48...
Page 826: Table 120. Rtc Register Map And Reset Values
Real-time clock (RTC) RM0090 26.6.20 RTC backup registers (RTC_BKPxR) Address offset: 0x50 to 0x9C Backup domain reset value: 0x0000 0000 System reset: not affected BKP[31:16] BKP[15:0] Bits 31:0 BKP[31:0] The application can write or read data to and from these registers. They are powered-on by V when V is switched off, so that they are not reset by...
Page 827 RM0090 Real-time clock (RTC) Table 120. RTC register map and reset values (continued) Offset Register RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x1C Reset value RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x20 Reset value RTC_WPR KEY[7:0] 0x24 Reserved...
Page 828 Real-time clock (RTC) RM0090 Refer to Section: Memory map for the register boundary addresses. Caution: Table 120, the reset value is the value after a backup domain reset. The majority of the registers are not affected by a system reset. For more information, please refer to Section 26.3.7: Resetting the RTC.
Page 829: Inter-Integrated Circuit (I 2 C) Interface
RM0090 Inter-integrated circuit (I C) interface Inter-integrated circuit (I C) interface This section applies to the whole STM32F4xx family, unless otherwise specified. 27.1 C introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus.
Page 830: Mode Selection
Inter-integrated circuit (I C) interface RM0090 – 1 Interrupt for successful address/ data communication – 1 Interrupt for error condition • Optional clock stretching • 1-byte buffer with DMA capability • Configurable PEC (packet error checking) generation or verification: – PEC value can be transmitted as last byte in Tx mode –...
Page 831: Figure 238. I2C Bus Protocol
RM0090 Inter-integrated circuit (I C) interface Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter.
Page 832: Figure 239. I2C Block Diagram For Stm32F40X/41X
Inter-integrated circuit (I C) interface RM0090 Figure 239. I C block diagram for STM32F40x/41x Data register Data Data shift register control PEC calculation Comparator Own address register Dual address register Clock PEC register control Clock control Register (CCR) Control registers (CR1&CR2) Control Status registers...
Page 833: Figure 240. I2C Block Diagram For Stm32F42X/43X
RM0090 Inter-integrated circuit (I C) interface Figure 240. I C block diagram for STM32F42x/43x 1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled. 27.3.2 C slave mode By default the I C interface operates in Slave mode.
Page 834 Inter-integrated circuit (I C) interface RM0090 Header or address not matched: the interface ignores it and waits for another Start condition. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set and waits for the 8-bit slave address. Address matched: the interface generates in sequence: •...
Page 835: Figure 241. Transfer Sequence Diagram For Slave Transmitter
RM0090 Inter-integrated circuit (I C) interface Figure 241. Transfer sequence diagram for slave transmitter 7-bit slave transmitter S Address Data1 Data2 DataN NA P ..EV1 EV3-1 EV3 EV3-2 10-bit slave transmitter S Header Address Header A Data1 ..DataN NA P EV1 EV3_1 EV3-2...
Page 836: Figure 242. Transfer Sequence Diagram For Slave Receiver
Inter-integrated circuit (I C) interface RM0090 Figure 242. Transfer sequence diagram for slave receiver 7-bit slave receiver S Address Data1 Data2 DataN ..10-bit slav e receiver S Header Address Data1 DataN ..Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, EVx= Event (with interrupt if ITEVFEN=1) EV1: ADDR=1, cleared by reading SR1 followed by reading SR2 EV2: RxNE=1 cleared by reading DR register.
Page 837 RM0090 Inter-integrated circuit (I C) interface SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
Page 838 Inter-integrated circuit (I C) interface RM0090 The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
Page 839: Figure 243. Transfer Sequence Diagram For Master Transmitter
RM0090 Inter-integrated circuit (I C) interface Figure 243. Transfer sequence diagram for master transmitter 7-bit master transmitter Address Data1 Data2 DataN ..EV6 EV8_1 EV8_2 10-bit master transmitter Header Address Data1 DataN ..EV8_1 EV8_2 Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, EVx= Event (with interrupt if ITEVFEN = 1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
Page 840 Inter-integrated circuit (I C) interface RM0090 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 841: Figure 244. Transfer Sequence Diagram For Master Receiver
RM0090 Inter-integrated circuit (I C) interface Figure 244. Transfer sequence diagram for master receiver 1. If a single byte is received, it is NA. 2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 3.
Page 842: Error Conditions
Inter-integrated circuit (I C) interface RM0090 For N >2 -byte reception, from N-2 data reception • Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read) • Set ACK low •...
Page 843: Table 121. Maximum Dnf[3:0] Value To Be Compliant With Thd:dat(Max)
RM0090 Inter-integrated circuit (I C) interface Overrun/underrun error (OVR) An overrun error can occur in slave mode when clock stretching is disabled and the I interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface.
Page 844: Sda/Scl Line Control
Inter-integrated circuit (I C) interface RM0090 Table 121. Maximum DNF[3:0] value to be compliant with Thd:dat(max) (continued) Maximum DNF value PCLK1 frequency Sm mode Fm mode 30 < F <= 40 PCLK1 40 < F <= 50 PCLK1 Note: For each frequency range, the constraint is given based on the worst case which is the minimum frequency of the range.
Page 845: Table 122. Smbus Vs. I2C
RM0090 Inter-integrated circuit (I C) interface Differences between SMBus and I The following table describes the differences between SMBus and I Table 122. SMBus vs. I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low timeout No timeout...
Page 846 Inter-integrated circuit (I C) interface RM0090 For the details on 128 bit UDID and more information on ARP, refer to SMBus specification version 2.0 (http://smbus.org/). SMBus alert mode SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin.
Page 847: Dma Requests
RM0090 Inter-integrated circuit (I C) interface 27.3.8 DMA requests DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. The DMA must be initialized and enabled before the I2C data transfer. The DMAEN bit must be set in the I2C_CR2 register before the ADDR event.
Page 848: Packet Error Checking
Inter-integrated circuit (I C) interface RM0090 Reception using DMA DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 849: Table 123. I2C Interrupt Requests
RM0090 Inter-integrated circuit (I C) interface be set before the ACK of the CRC reception in slave mode. It must be set when the ACK is set low in master mode. • A PECERR error flag/interrupt is also available in the I2C_SR1 register. •...
Page 850: Figure 245. I2C Interrupt Mapping Diagram
Inter-integrated circuit (I C) interface RM0090 Figure 245. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBALERT 850/1731 DocID018909 Rev 11...
Page 851 RM0090 Inter-integrated circuit (I C) interface 27.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 38.16.2: Debug support for timers, watchdog, bxCAN and I2C on page...
Page 852 Inter-integrated circuit (I C) interface RM0090 Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 853 RM0090 Inter-integrated circuit (I C) interface Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
Page 854 Inter-integrated circuit (I C) interface RM0090 Bit 9 ITEVTEN: Event interrupt enable 0: Event interrupt disabled 1: Event interrupt enabled This interrupt is generated when: – SB = 1 (Master) – ADDR = 1 (Master/Slave) – ADD10= 1 (Master) – STOPF = 1 (Slave) –...
Page 855 RM0090 Inter-integrated circuit (I C) interface 27.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 ADD[9:8] ADD[7:1] ADD0 MODE Reserved Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
Page 856 Inter-integrated circuit (I C) interface RM0090 27.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 DR[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus. –...
Page 857 RM0090 Inter-integrated circuit (I C) interface Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
Page 858 Inter-integrated circuit (I C) interface RM0090 Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Page 859 RM0090 Inter-integrated circuit (I C) interface Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 860 Inter-integrated circuit (I C) interface RM0090 27.6.7 C Status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
Page 861 RM0090 Inter-integrated circuit (I C) interface Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 862 Inter-integrated circuit (I C) interface RM0090 Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) Controls the SCL clock in master mode.
Page 863 RM0090 Inter-integrated circuit (I C) interface 27.6.10 C FLTR register (I2C_FLTR) Address offset: 0x24 Reset value: 0x0000 The I2C_FLTR is available on STM32F42xxx and STM32F43xxx only. DNF[3:0] ANOFF Reserved Bits 15:5 Reserved, must be kept at reset value Bit 4 ANOFF: Analog noise filter OFF 0: Analog noise filter enable 1: Analog noise filter disable Note: ANOFF must be configured only when the I2C is disabled (PE = 0).
Page 864: Table 124. I2C Register Map And Reset Values
Inter-integrated circuit (I C) interface RM0090 27.6.11 C register map The table below provides the I C register map and reset values. Table 124. I C register map and reset values Offset Register I2C_CR1 0x00 Reserved Reset value I2C_CR2 FREQ[5:0] 0x04 Reserved Reset value...
Page 865: Spi Introduction
RM0090 Serial peripheral interface (SPI) Serial peripheral interface (SPI) This section applies to the whole STM32F4xx family, unless otherwise specified. 28.1 SPI introduction The SPI interface provides two main functions, supporting either the SPI protocol or the I audio protocol. By default, it is the SPI function that is selected. It is possible to switch the interface from SPI to I S by software.
Page 866: Spi Features
Serial peripheral interface (SPI) RM0090 28.2 SPI and I S main features 28.2.1 SPI features • Full-duplex synchronous transfers on three lines • Simplex synchronous transfers on two lines with or without a bidirectional data line • 8- or 16-bit transfer frame format selection •...
Page 867 RM0090 Serial peripheral interface (SPI) 28.2.2 S features • Full duplex communication • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) •...
Page 868: Figure 246. Spi Block Diagram
Serial peripheral interface (SPI) RM0090 28.3 SPI functional description 28.3.1 General description The block diagram of the SPI is shown in Figure 246. Figure 246. SPI block diagram Usually, the SPI is connected to external devices through 4 pins: • MISO: Master In / Slave Out data.
Page 869: Figure 247. Single Master/ Single Slave Application
RM0090 Serial peripheral interface (SPI) device is configured in slave mode (refer to Section 28.3.10: Error flags on page 889). A basic example of interconnections between a single master and a single slave is illustrated in Figure 247. Figure 247. Single master/ single slave application Master Slave MSBit...
Page 870 Serial peripheral interface (SPI) RM0090 the clock when no data is being transferred. This bit affects both master and slave modes. If CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a high-level idle state.
Page 871: Figure 248. Data Clock Timing Diagram
RM0090 Serial peripheral interface (SPI) Figure 248. Data clock timing diagram 1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register. Data frame format Data can be shifted out either MSB-first or LSB-first depending on the value of the LSBFIRST bit in the SPI_CR1 Register.
Page 872 Serial peripheral interface (SPI) RM0090 Procedure Set the DFF bit to define 8- or 16-bit data frame format Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 248).
Page 873: Figure 249. Ti Mode - Slave Mode, Single Transfer
RM0090 Serial peripheral interface (SPI) In Slave mode (Figure 249: TI mode - Slave mode, single transfer Figure 250: TI mode - Slave mode, continuous transfer), the SPI baud rate prescaler is used to control the moment when the MISO pin state changes to HI-Z. Any baud rate can be used thus allowing to determine this moment with optimal flexibility.
Page 874: Configuring The Spi In Master Mode
Serial peripheral interface (SPI) RM0090 28.3.3 Configuring the SPI in master mode In the master configuration, the serial clock is generated on the SCK pin. Procedure Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register). Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure...
Page 875: Figure 251. Ti Mode - Master Mode, Single Transfer
RM0090 Serial peripheral interface (SPI) SPI TI protocol in master mode In master mode, the SPI interface is compatible with the TI protocol. The FRF bit of the SPI_CR2 register can be used to configure the master SPI serial communications to be compliant with this protocol.
Page 876: Configuring The Spi For Half-Duplex Communication
Serial peripheral interface (SPI) RM0090 28.3.4 Configuring the SPI for half-duplex communication The SPI is capable of operating in half-duplex mode in 2 configurations. • 1 clock and 1 bidirectional data wire • 1 clock and 1 data wire (receive-only or transmit-only) 1 clock and 1 bidirectional data wire (BIDIMODE=1) This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register.
Page 877 RM0090 Serial peripheral interface (SPI) Start sequence in master mode • In full-duplex (BIDIMODE=0 and RXONLY=0) – The sequence begins when data are written into the SPI_DR register (Tx buffer). – The data are then parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission and then shifted out serially to the MOSI pin.
Page 878 Serial peripheral interface (SPI) RM0090 software must have written the data to be sent before the SPI master device initiates the transfer. – No data are received. • In bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0) – The sequence begins when the slave device receives the clock signal and the first bit of the data on its MISO pin.
Page 879: Figure 253. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0 And Rxonly=0) In The Case Of Continuous Transfers
RM0090 Serial peripheral interface (SPI) Figure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers Example in Master mode with CPOL=1, CPHA=1 DATA1 = 0xF1 DATA2 = 0xF2 DATA3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware...
Page 880: Figure 255. Txe/Bsy Behavior In Master Transmit-Only Mode (Bidimode=0 And Rxonly=0) In
Serial peripheral interface (SPI) RM0090 Transmit-only procedure (BIDIMODE=0 RXONLY=0) In this mode, the procedure can be reduced as described below and the BSY bit can be used to wait until the completion of the transmission (see Figure 255 Figure 256). Enable the SPI by setting the SPE bit to 1.
Page 881: Figure 256. Txe/Bsy In Slave Transmit-Only Mode (Bidimode=0 And Rxonly=0) In The Case Of
RM0090 Serial peripheral interface (SPI) Figure 256. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers Example in slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware...
Page 882: Figure 257. Rxne Behavior In Receive-Only Mode (Bidirmode=0 And Rxonly=1)
Serial peripheral interface (SPI) RM0090 Figure 257. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of continuous transfers Example with CPOL=1, CPHA=1, RXONLY=1 DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3 MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware cleared by software...
Page 883: Figure 258. Txe/Bsy Behavior When Transmitting (Bidirmode=0 And Rxonly=0)
RM0090 Serial peripheral interface (SPI) Figure 258. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of discontinuous transfers Example with CPOL=1, CPHA=1 DATA 1 = 0xF1 MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 TXE flag Tx buffer...
Page 884 Serial peripheral interface (SPI) RM0090 Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values. Program the polynomial in the SPI_CRCPR register. Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also clears the SPI_RXCRCR and SPI_TXCRCR registers. Enable the SPI by setting the SPE bit in the SPI_CR1 register.
Page 885: Status Flags
RM0090 Serial peripheral interface (SPI) 28.3.7 Status flags Four status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can be loaded into the buffer.
Page 886: Disabling The Spi
Serial peripheral interface (SPI) RM0090 28.3.8 Disabling the SPI When a transfer is terminated, the application can stop the communication by disabling the SPI peripheral. This is done by clearing the SPE bit. For some configurations, disabling the SPI and entering the Halt mode while a transfer is ongoing can cause the current transfer to be corrupted and/or the BSY flag might become unreliable.
Page 887: Spi Communication Using Dma (Direct Memory Addressing)
RM0090 Serial peripheral interface (SPI) In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0) You can disable the SPI (write SPE=1) at any time: the current transfer will complete before the SPI is effectively disabled Then, if you want to enter the Halt mode, you must first wait until BSY = 0 before entering the Halt mode (or disabling the peripheral clock).
Page 888: Figure 259. Transmission Using Dma
Serial peripheral interface (SPI) RM0090 Figure 259. Transmission using DMA Example with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware cleared by DMA write...
Page 889: Error Flags
RM0090 Serial peripheral interface (SPI) DMA capability with CRC When SPI communication is enabled with CRC communication and DMA mode, the transmission and reception of the CRC at the end of communication are automatic that is without using the bit CRCNEXT. After the CRC reception, the CRC must be read in the SPI_DR register to clear the RXNE flag.
Page 890: Table 125. Spi Interrupt Requests
Serial peripheral interface (SPI) RM0090 CRC error This flag is used to verify the validity of the value received when the CRCEN bit in the SPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value received in the shift register does not match the receiver SPI_RXCRCR value.
Page 891: Figure 262. I 2 S Block Diagram
RM0090 Serial peripheral interface (SPI) 28.4 S functional description 28.4.1 S general description The block diagram of the I S is shown in Figure 262. Figure 262. I S block diagram 1. I2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I S full duplex mode.
Page 892: Figure 263. I2S Full Duplex Block Diagram
Serial peripheral interface (SPI) RM0090 The I S shares three common pins with the SPI: • SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in half-duplex mode only). • WS: Word Select (mapped on the NSS pin) is the data control signal output in master mode and input in slave mode.
Page 893: Supported Audio Protocols
RM0090 Serial peripheral interface (SPI) I2Sx can operate in master mode. As a result: • Only I2Sx can output SCK and WS in half duplex mode • Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full duplex mode. The extended I2Ss (I2Sx_ext) can be used only in full duplex mode.
Page 894: Figure 264. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
Serial peripheral interface (SPI) RM0090 Figure 264. I S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) Transmission Reception May be 16-bit, 32-bit LSB MSB Channel left Channel right Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver).
Page 895: Figure 266. Transmitting 0X8Eaa33
RM0090 Serial peripheral interface (SPI) Figure 266. Transmitting 0x8EAA33 Second write to Data register First write to Data register 0x8EAA 0x33XX Only the 8 MSBs are sent to complete the 24 bits 8 LSB bits have no meaning and could be anything •...
Page 896: Figure 269. Example
Serial peripheral interface (SPI) RM0090 Figure 269. Example Only one access to SPI_DR 0X76A3 For transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its interrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.
Page 897: Figure 271. Msb Justified 24-Bit Frame Length With Cpol = 0
RM0090 Serial peripheral interface (SPI) Figure 271. MSB Justified 24-bit frame length with CPOL = 0 Reception Transmission 8-bit remaining 24-bit data 0 forced Channel left 32-bit Channel right Figure 272. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 Transmission Reception 16-bit remaining...
Page 898: Figure 274. Lsb Justified 24-Bit Frame Length With Cpol = 0
Serial peripheral interface (SPI) RM0090 Figure 274. LSB Justified 24-bit frame length with CPOL = 0 Reception Transmission 24-bit remaining 8-bit data 0 forced Channel left 32-bit Channel right • In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register are required from software or by DMA.
Page 899: Figure 277. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
RM0090 Serial peripheral interface (SPI) Figure 277. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 Transmission Reception 16-bit remaining 16-bit data 0 forced Channel left 32-bit Channel right When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, Only one access to SPI_DR is required.
Page 900: Figure 279. Pcm Standard Waveforms (16-Bit)
Serial peripheral interface (SPI) RM0090 PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPI_I2SCFGR. Figure 279. PCM standard waveforms (16-bit) short frame fixed to 13-bit...
Page 901: Figure 281. Audio Sampling Frequency Definition
RM0090 Serial peripheral interface (SPI) 28.4.4 Clock generator The I S bitrate determines the dataflow on the I S data line and the I S clock signal frequency. S bitrate = number of bits per channel × number of channels × sampling audio frequency For a 16-bit audio, left and right channel, the I S bitrate is calculated as follows: S bitrate = 16 ×...
Page 902: Table 126. Audio Frequency Precision (For Pllm Vco = 1 Mhz Or 2 Mhz)
Serial peripheral interface (SPI) RM0090 When the master clock is disabled (MCKOE bit cleared): = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide Table 126 provides example precision values for different clock configurations. Note: Other configurations are possible that allow optimum clock precision.
Page 903 RM0090 Serial peripheral interface (SPI) 28.4.5 S master mode The I S can be configured as follows: • In master mode for transmission or reception (half-duplex mode using I2Sx) • In master mode transmission and reception (full duplex mode using I2Sx and I2Sx_ext).
Page 904 Serial peripheral interface (SPI) RM0090 To ensure a continuous audio data transmission, it is mandatory to write the SPI_DR with the next data to transmit before the end of the current transmission. To switch off the I S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0. Reception sequence The operating mode is the same as for the transmission mode except for the point 3 (refer to the procedure described in...
Page 905 RM0090 Serial peripheral interface (SPI) 28.4.6 S slave mode The I S can be configured as follows: • In slave mode for transmission or reception (half-duplex mode using I2Sx) • In slave mode transmission and reception (full duplex mode using I2Sx and I2Sx_ext). The operating mode is following mainly the same rules as described for the I S master configuration.
Page 906: Status Flags
Serial peripheral interface (SPI) RM0090 to the software that the transferred data are wrong. If the ERRIE bit is set into the SPI_CR2 register, an interrupt is generated when the UDR flag in the SPI_SR register goes high. In this case, it is mandatory to switch off the I S and to restart a data transfer starting from the left channel.
Page 907: Error Flags
RM0090 Serial peripheral interface (SPI) The BSY flag is cleared: • when a transfer completes (except in master transmit mode, in which the communication is supposed to be continuous) • when the I S is disabled When communication is continuous: •...
Page 908: Table 127. I
Serial peripheral interface (SPI) RM0090 Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from SPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE bit is set in SPI_CR2.
Page 909 RM0090 Serial peripheral interface (SPI) 28.5 SPI and I S registers Refer to Section: List of abbreviations for registers. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 28.5.1 SPI control register 1 (SPI_CR1) (not used in I S mode) Address offset: 0x00 Reset value: 0x0000...
Page 910 Serial peripheral interface (SPI) RM0090 Bit 10 RXONLY: Receive only This bit combined with the BIDImode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. 0: Full duplex (Transmit and receive) 1: Output disabled (Receive-only mode) Note: This bit is not used in I...
Page 911: Spi Control Register 2 (Spi_Cr2)
RM0090 Serial peripheral interface (SPI) Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 912: Spi Status Register (Spi_Sr)
Serial peripheral interface (SPI) RM0090 Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 913: Spi Data Register (Spi_Dr)
RM0090 Serial peripheral interface (SPI) Bit 4 CRCERR: CRC error flag 0: CRC value received matches the SPI_RXCRCR value 1: CRC value received does not match the SPI_RXCRCR value This flag is set by hardware and cleared by software writing 0. Note: This bit is not used in I S mode.
Page 914 Serial peripheral interface (SPI) RM0090 28.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I mode) Address offset: 0x10 Reset value: 0x0007 CRCPOLY[15:0] Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required.
Page 915 RM0090 Serial peripheral interface (SPI) Bits 15:0 TXCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register.
Page 916 Serial peripheral interface (SPI) RM0090 Bits 5:4 I2SSTD: I2S standard selection 00: I S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I S standards, refer to Section 28.4.3 on page 893.
Page 917 RM0090 Serial peripheral interface (SPI) Bits 15:10 Reserved, must be kept at reset value. Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled.
Page 918: Table 128. Spi Register Map And Reset Values
Serial peripheral interface (SPI) RM0090 28.5.10 SPI register map The table provides shows the SPI register map and reset values. Table 128. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] 0x00 Reserved Reset value SPI_CR2 0x04 Reserved Reset value SPI_SR 0x08...
Page 919: Serial Audio Interface (Sai)
RM0090 Serial audio interface (SAI) Serial audio interface (SAI) This section applies to the STM32F42xxx and STM32F43xxx family. 29.1 Introduction The SAI interface (serial audio interface) offers a wide set of audio protocols due to its flexibility and wide range of configurations. Many stereo or mono audio applications may be targeted.
Page 920: Main Features
Serial audio interface (SAI) RM0090 29.2 Main features • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. •...
Page 921: Figure 283. Functional Block Diagram
RM0090 Serial audio interface (SAI) 29.3 Functional block diagram The block diagram of the SAI is shown in Figure 283. Figure 283. Functional block diagram The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each audio block integrates a 32-bit shift register controlled by their own functional state machine.
Page 922: Main Sai Modes
Serial audio interface (SAI) RM0090 mode definition. In AC’97 protocol, it will be an SAI output even if the SAI (link controller) is set-up to consume the SCK clock (and so to be in Slave mode). 29.4 Main SAI modes Each audio sub-block of the SAI can be configured to be master or slave via bit MODE[0] in the SAI_xCR1 register of the selected audio block.
Page 923: Figure 284. Audio Frame
RM0090 Serial audio interface (SAI) 29.5 SAI synchronization mode Internal synchronization An audio block can be declared synchronous with the second audio block. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication.
Page 924: Frame Length
Serial audio interface (SAI) RM0090 In AC’97 mode (bit PRTCFG[1:0] = 10 in the SAI_xCR1 register), the frame synchronization shape is forced to be configured to target these protocols. The SAI_xFRCR register value is ignored. Each audio block is independent and so each requires a specific configuration. 29.7.1 Frame length •...
Page 925: Frame Synchronization Active Level Length
RM0090 Serial audio interface (SAI) flow. 29.7.3 Frame synchronization active level length Bit FSALL[6:0] in the SAI_xFRCR register configures the length of the active level of the Frame synchronization signal. The length can be set from 1 to 128 bit clock SCK. The active length may be half of the frame length in I2S, LSB or MSB-justified modes for instance, or one-bit wide for PCM/DSP or TDM mode, or even 16-bit length in AC’97.
Page 926: Figure 285. Fs Role Is Start Of Frame + Channel Side Identification (Fsdef = Tris = 1)
Serial audio interface (SAI) RM0090 Figure 285. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) 1. The frame length should be even. If bit FSDEF in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and if the number of slots defined in bit NBSLOT[3:0] in SAI_xSLOTR multiplied by the number of bits by slot configured in bit SLOTSZ[1:0] in SAI_xSLOTR is less than the frame size (bit FRL[7:0] in the SAI_xFRCR register), then,...
Page 927: Figure 287. Slot Size Configuration With Fboff = 0 In Sai_Xslotr
RM0090 Serial audio interface (SAI) Each slot can be defined as a valid slot, or not, by setting bit SLOTEN[15:0] in the SAI_xSLOTR register. In an audio frame, during the transfer of a non-valid slot, 0 value will be forced on the data line or the SD data line will be released to HI-z (refer to Section 29.12.4) if the audio block is transmitter, or the received value from the end of this slot will be ignored.
Page 928: Figure 289. Audio Block Clock Generator Overview
Serial audio interface (SAI) RM0090 It is mandatory to respect the following conditions in order to avoid bad SAI behavior: FBOFF ≤ (SLOTSZ - DS), DS ≤ SLOTSZ, NBSLOT x SLOTSZ ≤ FRL (frame length), The number of slots should be even when bit FSDEF in the SAI_xFRCR register is set. In AC’97 (bit PRTCFG[1:0] = 10), the slot size is automatically set as defined in Section 29.11.
Page 929: Table 129. Example Of Possible Audio Frequency Sampling Range
RM0090 Serial audio interface (SAI) Table 129. Example of possible audio frequency sampling range Input SAI_CK_x clock Most usual audio frequency MCKDIV[3:0] frequency sampling achievable 192 kHz MCKDIV[3:0] = 0000 96 kHz MCKDIV[3:0] = 0001 192 kHz x 256 48 kHz MCKDIV[3:0] = 0010 16 kHz MCKDIV[3:0] = 0100...
Page 930 Serial audio interface (SAI) RM0090 An interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on: • FIFO threshold setting (FLTH bits in SAI_CR2) • Communication direction transmitter or receiver (see Section : Interrupt generation in transmitter mode Section : Interrupt generation in reception mode)
Page 931 RM0090 Serial audio interface (SAI) (FLTH[2:0] bits in SAI_xSR is higher or equal to 010b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by hardware when less than a quarter of the FIFO data locations become available (FLTH[2:0] bits in SAI_xSR is less than 010b). •...
Page 932: Figure 290. Ac'97 Audio Frame
Serial audio interface (SAI) RM0090 29.11 AC’97 link controller The SAI is able to work as an AC’97 link controller. In this protocol: • The slot number and the slot size are fixed. • The frame synchronization signal is perfectly defined and has a fixed shape. To select this protocol, set bit PRTCFG[1:0] in the SAI_xCR1 register to 10.
Page 933: Specific Features
RM0090 Serial audio interface (SAI) 29.12 Specific features The SAI has some specific functions which can be useful depending on the audio protocol selected. These functions are accessible through specific bits in the SAI_xCR2 register. 29.12.1 Mute mode Mute mode may be used when the audio block is a transmitter or receiver. Transmitter In transmitter mode, Mute mode can be selected at anytime.
Page 934: Figure 291. Data Companding Hardware In An Audio Block In The Sai
Serial audio interface (SAI) RM0090 with a distinct and different left and right data, bit MONO has no meaning. The conversion from the output stereo file to the equivalent mono file is done by software. Note: To enable Mono mode, NBSLOT and SLOTEN must equal two and MONO bit set to 1. 29.12.3 Companding mode Telecommunication applications may require to process the data to transmit or to receive...
Page 935: Output Data Line Management On An Inactive Slot
RM0090 Serial audio interface (SAI) Expansion or compression mode is automatically selected by the SAI configuration. • If the SAI audio block is configured to be a transmitter, and if the COMP[1] bit is set in the SAI_xCR2 register, the compression mode will be applied. •...
Page 936: Figure 292. Tristate Strategy On Sd Output Line On An Inactive Slot
Serial audio interface (SAI) RM0090 Figure 292. Tristate strategy on SD output line on an inactive slot When the selected audio protocol uses the FS signal as a start of frame and a channel side identification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed according to Figure 293 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and...
Page 937: Figure 293. Tristate On Output Data Line In A Protocol Like I2S
RM0090 Serial audio interface (SAI) Figure 293. Tristate on output data line in a protocol like I2S If the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD output line on Figure 292 Figure 293 are replaced by a drive with a value of 0.
Page 938: Figure 294. Overrun Detection Error
Serial audio interface (SAI) RM0090 was stored internally when the overrun condition was detected, and this, to avoid data slot de-alignment in the destination memory (refer to Figure 294). The OVRUDR flag is cleared when bit COVRUDR is set in the SAI_xCLRFR register. Figure 294.
Page 939: Figure 295. Fifo Underrun Event
RM0090 Serial audio interface (SAI) Figure 295. FIFO underrun event 29.13.2 Anticipated frame synchronisation detection (AFSDET) This flag AFSDET is used only in Slave mode. In master mode, it is never asserted. It informs about the detection of a frame synchronisation (FS) earlier than expected since the frame length, the frame polarity, the frame offset are defined and known.
Page 940: Codec Not Ready (Cnrdy Ac'97)
Serial audio interface (SAI) RM0090 The late frame synchronisation detection flag is set when the error is detected, SAI needs to be resynchronized with the master (the four steps described above should be respected). This detection and flag assertion can detect glitches on the SCK clock in a noisy environment, detected by the state machine of the audio block.
Page 941: Table 130. Interrupt Sources
RM0090 Serial audio interface (SAI) 29.14 Interrupt sources The SAI has 7 possible interrupt sources as illustrated by Table Table 130. Interrupt sources Interru Interrupt Audio block mode Interrupt enable Interrupt clear source group Depend on: - FIFO threshold setting (FLTH bits in SAI_CR2) Master or Slave FREQIE in...
Page 942: Sai Dma Interface
Serial audio interface (SAI) RM0090 If there is an audio block in the SAI synchronous with the other one, the one which is the master must be disabled first. 29.16 SAI DMA interface In order to free the CPU and to optimize the bus bandwidth, each SAI audio block has an independent DMA interface in order to read or to write into the SAI_xDR register (to hit the internal FIFO).
Page 943: Sai Registers
RM0090 Serial audio interface (SAI) 29.17 SAI registers 29.17.1 SAI xConfiguration register 1 (SAI_xCR1) where x is A or B Address offset: Block A: 0x004 Address offset: Block B: 0x024 Reset value: 0x0000 0040 MCKDIV[3:0] NODIV DMAEN SAIxEN Reserved Res. OutDri LSBFIR MONO...
Page 944 Serial audio interface (SAI) RM0090 Bit 12 MONO: Mono mode. This bit is set and cleared by software. 0: Stereo mode 1: Mono mode. This bit has a meaning only when the number of slots is equal to 2. When the Mono mode is selected, the data of the slot 0 data is duplicated on the slot 1 when the audio block is a transmitter.
Page 945 RM0090 Serial audio interface (SAI) Bit 4 Reserved, always read as 0. Bits 3:2 PRTCFG[1:0]: Protocol configuration. These bits are set and cleared by software. 00: Free protocol 01: Not used 10: AC’97 protocol 11: Not used Free protocol selection allows to use the powerful configuration of the audio block to address a specific audio protocol (like I2S, LSB/MSB justified, TDM, PCM/DSP...) setting most of the configuration register bits as well as frame configuration register.
Page 946: Sai Xconfiguration Register 2 (Sai_Xcr2) Where X Is A Or B
Serial audio interface (SAI) RM0090 29.17.2 SAI xConfiguration register 2 (SAI_xCR2) where x is A or B Address offset: Block A: 0x008 Address offset: Block B: 0x028 Reset value: 0x0000 0000 Reserved MUTE COMP[1:0] MUTECNT[5:0] Mute TRIS FFLUS Bits 31:16 Reserved, always read as 0 Bits 15:14 COMP[1:0]: Companding mode.
Page 947 RM0090 Serial audio interface (SAI) Bit 6 MUTEVAL: Mute value. This bit is set and cleared by software.This bit has to be written before enabling the audio block: SAIxEN. 0: Bit value 0 is sent during the MUTE mode. 1: Last values are sent during the MUTE mode. This bit has a meaning only when the audio block is a transmitter and when the number of slots is lower or equal to 2 and if the MUTE bit is set.
Page 948: Sai Xframe Configuration Register (Sai_Xfrcr) Where X Is A Or B
Serial audio interface (SAI) RM0090 29.17.3 SAI xFrame configuration register (SAI_XFRCR) where x is A or B Address offset: Block A: 0x00C Address offset: Block B: 0x02C Reset value: 0x0000 0007 Note: This register has no meaning in AC’97 audio protocol FSOFF FSPOL FSDEF Reserved FSALL[6:0]...
Page 949 RM0090 Serial audio interface (SAI) Bit 15 Reserved, always read as 0. Bits 14:8 FSALL[6:0]: Frame synchronization active level length. These bits are set and cleared by software The value set in these bits specifies the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits have no meaning and are not used in AC’97 audio block configuration.
Page 950: Sai Xslot Register (Sai_Xslotr) Where X Is A Or B
Serial audio interface (SAI) RM0090 29.17.4 SAI xSlot register (SAI_xSLOTR) where x is A or B Address offset: Block A: 0x010 Address offset: Block B: 0x030 Reset value: 0x0000 0000 Note: This register has no meaning in AC’97 audio protocol SLOTEN[15:0] NBSLOT[3:0] SLOTSZ[1:0]...
Page 951: Sai Xinterrupt Mask Register2(Sai_Xim) Where X Is A Or B
RM0090 Serial audio interface (SAI) 29.17.5 SAI xInterrupt mask register2(SAI_xIM) where x is A or B Address offset: blockA: 0x014 Address offset: block B: 0x034 Reset value: 0x0000 0000 Reserved LFSDETI AFSDET CNRDY FREQI WCKC OVRU EDET FGIE DRIE Reserved Bits 31:7 Reserved, always read as 0.
Page 952 Serial audio interface (SAI) RM0090 Bit 2 WCKCFGIE: Wrong clock configuration interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled This bit is considered only if the audio block is configured as master (MODE[1] = 0 in the SAI_ACR1 register) and bit NODIV = 0 in the SAI_xCR1 register.
Page 953: Sai Xstatus Register (Sai_Xsr) Where X Is A Or B
RM0090 Serial audio interface (SAI) 29.17.6 SAI xStatus register (SAI_xSR) where x is A or B Address offset: block A: 0x018 Address offset: block B: 0x038 Reset value: 0x0000 0008 FLTH Reserved MUTED LFSDET AFSDET CNRDY FREQ WCKCFG OVRUDR Reserved Bits 31:19 Reserved, always read as 0.
Page 954 Serial audio interface (SAI) RM0090 Bit 4 CNRDY: Codec not ready. This bit is read only. 0: The external AC’97 codec is ready 1: The external AC’97 codec is not ready This bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register and is configured in receiver mode.
Page 955: Sai Xclear Flag Register (Sai_Xclrfr) Where X Is A Or B
RM0090 Serial audio interface (SAI) 29.17.7 SAI xClear flag register (SAI_xCLRFR) where X is A or B Address offset: block A: 0x01C Address offset: block B: 0x03C Reset value: 0x0000 0000 Reserved CAFSDE CMUTE COVRUD CLFSDET CCNRDY CWCKCFG Reserved Reserved Bits 31:7 Reserved, always read as 0.
Page 956: Table 131. Sai Register Map And Reset Values
Serial audio interface (SAI) RM0090 29.17.8 SAI xData register (SAI_xDR) where x is A or B Address offset: block A: 0x020 Address offset: block B: 0x040 Reset value: 0x0000 0000 DATA[31:16] DATA[15:0] Bits 31:0 DATA[31:0]: Data A write into this register has the effect of loading the FIFO if the FIFO is not full. A read from this register has to effect of draining-up the FIFO if the FIFO is not empty.
Page 957 RM0090 Serial audio interface (SAI) Table 131. SAI register map and reset values (continued) Register Offset and reset value 0x001C SAI_xCLRFR or 0x003C Reset value DATA[31:0] 0x0020 SAI_xDR or 0x0040 Reset value Refer to Section: Memory map for the register boundary addresses. DocID018909 Rev 11 957/1731...
Page 958: Transmitter (Usart)
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Universal synchronous asynchronous receiver transmitter (USART) This section applies to the whole STM32F4xx family, unless otherwise specified. 30.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
Page 959: Usart Functional Description
RM0090 Universal synchronous asynchronous receiver transmitter (USART) • Transfer detection flags: – Receive buffer full – Transmit buffer empty – End of transmission flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Four error detection flags: –...
Page 960 Universal synchronous asynchronous receiver transmitter (USART) RM0090 Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: • An Idle Line prior to transmission or reception • A start bit • A data word (8 or 9 bits) least significant bit first •...
Page 961: Figure 296. Usart Block Diagram
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Figure 296. USART block diagram PWDATA PRDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA Receive Shift Register Transmit Shift Register ENDEC SW_RX block...
Page 962: Figure 297. Word Length Programming
Universal synchronous asynchronous receiver transmitter (USART) RM0090 30.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 297). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”...
Page 963: Transmitter
RM0090 Universal synchronous asynchronous receiver transmitter (USART) 30.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 964: Figure 298. Configurable Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Figure 298. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible...
Page 965: Figure 299. Tc/Txe Behavior When Transmitting
RM0090 Universal synchronous asynchronous receiver transmitter (USART) When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 966: Figure 300. Start Bit Detection When Oversampling By 16 Or 8
Universal synchronous asynchronous receiver transmitter (USART) RM0090 30.3.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized.
Page 967 RM0090 Universal synchronous asynchronous receiver transmitter (USART) Character reception During an USART reception, data shifts in least significant bit first through the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the received shift register.
Page 968 Universal synchronous asynchronous receiver transmitter (USART) RM0090 Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
Page 969: Figure 301. Data Sampling When Oversampling By 16
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options: • the majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set •...
Page 970: Table 132. Noise Detection From Sampled Data
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Figure 302. Data sampling when oversampling by 8 RX LINE sampled values Sample clock(x8) One bit time Table 132. Noise detection from sampled data Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise.
Page 971: Fractional Baud Rate Generation
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode. 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit.
Page 972 Universal synchronous asynchronous receiver transmitter (USART) RM0090 How to derive USARTDIV from USART_BRR register values when OVER8=0 Example 1: If DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then Mantissa (USARTDIV) = 0d27 Fraction (USARTDIV) = 12/16 = 0d0.75 Therefore USARTDIV = 0d27.75 Example 2: To program USARTDIV = 0d25.62...
Page 973: Table 133. Error Calculation For Programmed Baud Rates At F
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Then, USART_BRR = 0x195 => USARTDIV = 0d25.625 Example 3: To program USARTDIV = 0d50.99 This leads to: DIV_Fraction = 8*0d0.99 = 0d7.92 The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x0330 =>...
Page 974: Oversampling By 8
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Table 134. Error calculation for programmed baud rates at f = 8 MHz or f =12 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK PCLK...
Page 975: Oversampling By 8
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Table 135. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8 = 0) Baud rate = 16 MHz = 24 MHz f PCLK f PCLK...
Page 976: Oversampling By 16
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Table 137. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 16 MHz PCLK PCLK Value...
Page 977: Oversampling By 16
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Table 138. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 8 MHz = 16 MHz PCLK PCLK...
Page 978: Oversampling By 8
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Table 139. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1)(2) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 30 MHz = 60 MHz PCLK PCLK...
Page 979: Oversampling By 16
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Table 140. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1) (2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 30 MHz =60 MHz PCLK PCLK...
Page 980: Oversampling By 8
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Table 141. Error calculation for programmed baud rates at f = 42 MHz or f = 84 Hz, PCLK PCLK (1)(2) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 42 MHz = 84 MHz PCLK PCLK...
Page 981: Usart Receiver Tolerance To Clock Deviation
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Table 142. Error calculation for programmed baud rates at f = 42 MHz or f = 84 MHz, PCLK PCLK (1)(2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 42 MHz = 84 MHz PCLK PCLK...
Page 982: Table 143. Usart Receiver's Tolerance When Div Fraction Is 0
Universal synchronous asynchronous receiver transmitter (USART) RM0090 The USART receiver’s tolerance to properly receive data is equal to the maximum tolerated deviation and depends on the following choices: • 10- or 11-bit character length defined by the M bit in the USART_CR1 register •...
Page 983: Figure 303. Mute Mode Using Idle Line Detection
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Idle line detection (WAKE=0) The USART enters mute mode when the RWU bit is written to 1. It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_SR register.
Page 984: Table 145. Frame Formats
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Figure 304. Mute mode using address mark detection In this example, the current address of the receiver is 1 RXNE RXNE RXNE (programmed in the USART_CR2 register) IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4...
Page 985: Lin (Local Interconnection Network) Mode
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Note: In case of wakeup by an address mark: the MSB bit of the data is taken into account to identify an address but not the parity bit. And the receiver does not check the parity of the address data (PE is not set in case of a parity error).
Page 986: Figure 305. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous asynchronous receiver transmitter (USART) RM0090 The behavior of the break detector state machine and the break flag is shown on the Figure 305: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 986.
Page 987: Figure 306. Break Detection In Lin Mode Vs. Framing Error Detection
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Figure 306. Break detection in LIN mode vs. Framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK...
Page 988: Figure 307. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0090 has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 989: Figure 309. Usart Data Clock Timing Diagram (M=1)
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Figure 309. USART data clock timing diagram (M=1) Idle or preceding Start M=1 (9 data bits) Idle or next transmission Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop...
Page 990: Figure 311. Iso 7816-3 Asynchronous Protocol
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Apart from this, the communications are similar to what is done in normal USART mode. The conflicts on the line must be managed by the software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TE bit is set.
Page 991: Figure 312. Parity Error Detection Using The 1.5 Stop Bits
RM0090 Universal synchronous asynchronous receiver transmitter (USART) (configured with 1.5 stop bits). The application can handle re-sending of data according to the protocol. A parity error is ‘NACK’ed by the receiver if the NACK control bit is set, otherwise a NACK is not transmitted. •...
Page 992: Irda Sir Endec Block
Universal synchronous asynchronous receiver transmitter (USART) RM0090 30.3.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: • LINEN, STOP and CLKEN bits in the USART_CR2 register, •...
Page 993: Figure 313. Irda Sir Endec- Block Diagram
RM0090 Universal synchronous asynchronous receiver transmitter (USART) IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <...
Page 994: Continuous Communication Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0090 30.3.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register.
Page 995: Figure 315. Transmission Using Dma
RM0090 Universal synchronous asynchronous receiver transmitter (USART) Figure 315. Transmission using DMA Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 996: Figure 316. Reception Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0090 Figure 316. Reception using DMA Error flagging and interrupt generation in multibuffer communication In case of multibuffer communication if any error occurs during the transaction the error flag will be asserted after the current byte. An interrupt will be generated if the interrupt enable flag is set.
Page 997: Figure 318. Rts Flow Control
RM0090 Universal synchronous asynchronous receiver transmitter (USART) RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 998: Table 146. Usart Interrupt Requests
Universal synchronous asynchronous receiver transmitter (USART) RM0090 30.4 USART interrupts Table 146. USART interrupt requests Enable control Interrupt event Event flag Transmit Data Register Empty TXEIE CTS flag CTSIE Transmission Complete TCIE Received Data Ready to be Read RXNE RXNEIE Overrun Error Detected Idle Line Detected IDLE...
Page 999: Table 147. Usart Mode Configuration
RM0090 Universal synchronous asynchronous receiver transmitter (USART) 30.5 USART mode configuration Table 147. USART mode configuration USART USART USART USART USART modes UART4 UART5 Asynchronous mode Hardware flow control Multibuffer communication (DMA) Multiprocessor communication Synchronous Smartcard Half-duplex (single-wire mode) IrDA 1.
Page 1000 Universal synchronous asynchronous receiver transmitter (USART) RM0090 Bits 31:10 Reserved, must be kept at reset value Bit 9 CTS: CTS flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).

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