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STM32F439
STMicroelectronics STM32F439 Controller Manuals
Manuals and User Guides for STMicroelectronics STM32F439 Controller. We have
2
STMicroelectronics STM32F439 Controller manuals available for free PDF download: Reference Manual, Manual
STMicroelectronics STM32F439 Reference Manual (1731 pages)
advanced ARM-based 32-bit MCUs
Brand:
STMicroelectronics
| Category:
Controller
| Size: 24.2 MB
Table of Contents
Table of Contents
2
Documentation Conventions
57
List of Abbreviations for Registers
57
Glossary
58
Peripheral Availability
58
Memory and Bus Architecture
59
System Architecture
59
Figure 1. System Architecture for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx Devices
60
D-Bus
62
Figure 2. System Architecture for Stm32F42Xxx and Stm32F43Xxx Devices
62
I-Bus
62
S-Bus
62
Busmatrix
63
DMA Memory Bus
63
DMA Peripheral Bus
63
DMA2D Bus
63
Ethernet DMA Bus
63
LCD-TFT Controller DMA Bus
63
USB OTG HS DMA Bus
63
AHB/APB Bridges (APB)
64
Memory Organization
64
Memory Map
64
Table 1
64
Table 1. Stm32F4Xx Register Boundary Addresses
64
Bit Banding
68
Embedded SRAM
68
Flash Memory Overview
68
Boot Configuration
69
Table 2. Boot Modes
69
Table 3. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
71
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F42Xxx and Stm32F43Xxx
71
Embedded Flash Memory Interface
73
Introduction
73
Main Features
73
Figure 3. Flash Memory Interface Connection Inside System Architecture (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
73
Embedded Flash Memory in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
74
Figure 4. Flash Memory Interface Connection Inside System Architecture (Stm32F42Xxx and Stm32F43Xxx)
74
Table 5. Flash Module Organization (Stm32F40X and Stm32F41X)
75
Embedded Flash Memory in Stm32F42Xxx and Stm32F43Xxx
76
Table 6. Flash Module - 2 Mbyte Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)
77
Mbyte Flash Memory Single Bank Vs Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)
78
Mbyte Single Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)
78
Table 9. 1 Mbyte Dual Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)
79
Read Interface
80
Relation between CPU Clock Frequency and Flash Memory Read Time
80
Table 10. Number of Wait States According to CPU Clock (HCLK) Frequency (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
80
Table 11. Number of Wait States According to CPU Clock (HCLK) Frequency (Stm32F42Xxx and Stm32F43Xxx)
81
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
82
Figure 5. Sequential 32-Bit Instruction Execution
83
Erase and Program Operations
84
Unlocking the Flash Control Register
84
Program/Erase Parallelism
85
Erase
85
Table 12. Program/Erase Parallelism
85
Programming
86
Read-While-Write (RWW)
87
Interrupts
88
Option Bytes
88
Description of User Option Bytes
88
Table 13. Flash Interrupt Request
88
Table 14. Option Byte Organization
88
Table 15. Description of the Option Bytes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
89
Table 16. Description of the Option Bytes (Stm32F42Xxx and Stm32F43Xxx)
90
Programming User Option Bytes
92
Read Protection (RDP)
93
Write Protections
94
Table 17. Access Versus Read Protection Level
94
Figure 6. RDP Levels
94
Proprietary Code Readout Protection (PCROP)
95
Figure 7. PCROP Levels
96
One-Time Programmable Bytes
97
Table 18. OTP Area Organization
97
Flash Interface Registers
98
Flash Access Control Register (FLASH_ACR)
98
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
98
Flash Access Control Register (FLASH_ACR)
99
For Stm32F42Xxx and Stm32F43Xxx
99
Flash Key Register (FLASH_KEYR)
100
Flash Option Key Register (FLASH_OPTKEYR)
100
Flash Status Register (FLASH_SR) for
101
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
101
Stm32F42Xxx and Stm32F43Xxx
102
Flash Control Register (FLASH_CR) for
103
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
103
Flash Control Register (FLASH_CR) for
105
Stm32F42Xxx and Stm32F43Xxx
105
Flash Option Control Register (FLASH_OPTCR) for
106
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
106
Flash Option Control Register (FLASH_OPTCR)
108
For Stm32F42Xxx and Stm32F43Xxx
108
Flash Option Control Register (FLASH_OPTCR1)
110
For Stm32F42Xxx and Stm32F43Xxx
110
Flash Interface Register Map
111
Table 19. Flash Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
111
Table 20. Flash Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
111
CRC Calculation Unit
113
CRC Introduction
113
CRC Main Features
113
Figure 8. CRC Calculation Unit Block Diagram
113
CRC Functional Description
114
CRC Registers
114
Data Register (CRC_DR)
114
Independent Data Register (CRC_IDR)
114
Control Register (CRC_CR)
115
CRC Register Map
115
Table 21. CRC Calculation Unit Register Map and Reset Values
115
Power Controller (PWR)
116
Power Supplies
116
Figure 9. Power Supply Overview for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
116
Figure 10. Power Supply Overview for Stm32F42Xxx and Stm32F43Xxx
117
Independent A/D Converter Supply and Reference Voltage
117
Battery Backup Domain
118
Figure 11. Backup Domain
120
Voltage Regulator for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
120
Voltage Regulator for Stm32F42Xxx and Stm32F43Xxx
121
Table 22. Voltage Regulator Configuration Mode Versus Device Operating Mode
122
Power Supply Supervisor
124
Power-On Reset (Por)/Power-Down Reset (PDR)
124
Figure 12. Power-On Reset/Power-Down Reset Waveform
124
Brownout Reset (BOR)
125
Programmable Voltage Detector (PVD)
125
Figure 13. BOR Thresholds
125
Low-Power Modes
126
Figure 14. PVD Thresholds
126
Peripheral Clock Gating
128
Slowing down System Clocks
128
Table 23. Low-Power Mode Summary
128
Sleep Mode
129
Table 24. Sleep-Now Entry and Exit
129
Stop Mode (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
130
Table 25. Sleep-On-Exit Entry and Exit
130
Table 26. Stop Operating Modes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
131
Table 27. Stop Mode Entry and Exit (for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
132
Stop Mode (Stm32F42Xxx and Stm32F43Xxx)
133
Table 28. Stop Operating Modes (Stm32F42Xxx and Stm32F43Xxx)
134
Standby Mode
136
Table 29. Stop Mode Entry and Exit (Stm32F42Xxx and Stm32F43Xxx)
136
Table 30. Standby Mode Entry and Exit
137
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
138
Power Control Registers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
141
PWR Power Control Register (PWR_CR)
141
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
141
PWR Power Control/Status Register (PWR_CSR)
142
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
142
Power Control Registers (Stm32F42Xxx and Stm32F43Xxx)
144
PWR Power Control Register (PWR_CR)
144
For Stm32F42Xxx and Stm32F43Xxx
144
PWR Power Control/Status Register (PWR_CSR)
147
For Stm32F42Xxx and Stm32F43Xxx
147
PWR Register Map
149
Table 31. PWR - Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
149
Table 32. PWR - Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
149
Reset and Clock Control for Stm32F42Xxx and Stm32F43Xxx (RCC)
150
Reset
150
System Reset
150
Power Reset
150
Backup Domain Reset
151
Clocks
151
Figure 15. Simplified Diagram of the Reset Circuit
151
Figure 16. Clock Tree
152
Figure 17. HSE/ LSE Clock Sources
154
HSE Clock
154
HSI Clock
155
PLL Configuration
155
LSE Clock
156
LSI Clock
156
System Clock (SYSCLK) Selection
156
Clock Security System (CSS)
157
RTC/AWU Clock
157
Clock-Out Capability
158
Internal/External Clock Measurement Using TIM5/TIM11
158
Watchdog Clock
158
Figure 18. Frequency Measurement with TIM5 in Input Capture Mode
159
Figure 19. Frequency Measurement with TIM11 in Input Capture Mode
160
RCC Registers
161
RCC Clock Control Register (RCC_CR)
161
RCC PLL Configuration Register (RCC_PLLCFGR)
163
RCC Clock Configuration Register (RCC_CFGR)
165
RCC Clock Interrupt Register (RCC_CIR)
167
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
170
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
173
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
174
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
174
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
178
RCC AHB1 Peripheral Clock Register (RCC_AHB1ENR)
180
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
182
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
183
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
183
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
187
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
189
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
192
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
193
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
193
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
197
RCC Backup Domain Control Register (RCC_BDCR)
199
RCC Clock Control & Status Register (RCC_CSR)
200
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
202
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
203
RCC PLL Configuration Register (RCC_PLLSAICFGR)
206
RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
207
RCC Register Map
210
Table 33. RCC Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
210
Reset and Clock Control for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC)
213
Reset
213
System Reset
213
Power Reset
214
Backup Domain Reset
214
Figure 20. Simplified Diagram of the Reset Circuit
214
Clocks
215
Figure 21. Clock Tree
216
HSE Clock
217
Figure 22. HSE/ LSE Clock Sources
218
HSI Clock
218
LSE Clock
219
PLL Configuration
219
Clock Security System (CSS)
220
LSI Clock
220
System Clock (SYSCLK) Selection
220
RTC/AWU Clock
221
Watchdog Clock
221
Clock-Out Capability
222
Internal/External Clock Measurement Using TIM5/TIM11
222
Figure 23. Frequency Measurement with TIM5 in Input Capture Mode
223
Figure 24. Frequency Measurement with TIM11 in Input Capture Mode
223
RCC Registers
224
RCC Clock Control Register (RCC_CR)
224
RCC PLL Configuration Register (RCC_PLLCFGR)
226
RCC Clock Configuration Register (RCC_CFGR)
228
RCC Clock Interrupt Register (RCC_CIR)
230
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
233
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
236
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
237
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
237
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
240
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
242
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
244
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
245
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
245
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
248
RCC APB2 Peripheral Clock Enable Register(RCC_APB2ENR)
250
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
252
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
254
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
255
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
256
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
259
RCC Backup Domain Control Register (RCC_BDCR)
261
RCC Clock Control & Status Register (RCC_CSR)
262
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
264
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
265
RCC Register Map
267
Table 34. RCC Register Map and Reset Values
267
General-Purpose I/Os (GPIO)
269
GPIO Introduction
269
GPIO Main Features
269
GPIO Functional Description
269
Figure 25. Basic Structure of a Five-Volt Tolerant I/O Port Bit
270
Table 35. Port Bit Configuration Table
270
General-Purpose I/O (GPIO)
271
I/O Pin Multiplexer and Mapping
272
Table 36. Flexible SWJ-DP Pin Assignment
273
Figure 26. Selecting an Alternate Function on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
274
Figure 27. Selecting an Alternate Function on Stm32F42Xxx and Stm32F43Xxx
275
GPIO Locking Mechanism
276
I/O Data Bitwise Handling
276
I/O Port Control Registers
276
I/O Port Data Registers
276
External Interrupt/Wakeup Lines
277
I/O Alternate Function Input/Output
277
Input Configuration
277
Figure 28. Input Floating/Pull Up/Pull down Configurations
278
Output Configuration
278
Alternate Function Configuration
279
Figure 29. Output Configuration
279
Figure 30. Alternate Function Configuration
279
Analog Configuration
280
Figure 31. High Impedance-Analog Configuration
280
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
280
Port Pins
280
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
280
Selection of RTC_AF1 and RTC_AF2 Alternate Functions
281
Table 38. RTC_AF2 Pin
282
GPIO Registers
283
GPIO Port Mode Register (Gpiox_Moder) (X = A..I/J/K
283
GPIO Port Output Type Register (Gpiox_Otyper)
283
(X = a
283
(X = a
284
GPIO Port Input Data Register (Gpiox_Idr) (X = a
285
GPIO Port Output Data Register (Gpiox_Odr) (X = a
285
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = a
286
(X = a
286
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a
287
(X = a
288
GPIO Register Map
288
Table 39. GPIO Register Map and Reset Values
288
System Configuration Controller (SYSCFG)
291
I/O Compensation Cell
291
SYSCFG Registers for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
291
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
291
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
292
SYSCFG External Interrupt Configuration Register 1
293
(Syscfg_Exticr1)
293
(Syscfg_Exticr2)
293
SYSCFG External Interrupt Configuration Register 3
294
(Syscfg_Exticr3)
294
Compensation Cell Control Register (SYSCFG_CMPCR)
295
Table 40. SYSCFG Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
296
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
298
SYSCFG External Interrupt Configuration Register
299
SYSCFG External Interrupt Configuration Register
300
Compensation Cell Control Register (SYSCFG_CMPCR)
302
Table 41. SYSCFG Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
303
SYSCFG Register Maps for Stm32F42Xxx and Stm32F43Xxx
303
DMA Introduction
304
Figure 32. DMA Block Diagram
306
DMA Functional Description
306
Figure 33. System Implementation of the Two DMA Controllers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx )
307
DMA Transactions
308
Figure 34. System Implementation of the Two DMA Controllers (Stm32F42Xxx and Stm32F43Xxx)
308
Figure 35. Channel Selection
309
Table 42. DMA1 Request Mapping
309
Arbiter
310
Table 43. DMA2 Request Mapping
310
DMA Streams
311
Table 44. Source and Destination Address
311
Figure 36. Peripheral-To-Memory Mode
312
Figure 37. Memory-To-Peripheral Mode
313
Figure 38. Memory-To-Memory Mode
314
Pointer Incrementation
314
Circular Mode
315
Programmable Data Width, Packing/Unpacking, Endianess
316
Table 45. Source and Destination Address Registers in Double Buffer Mode (DBM=1)
316
Table 46. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
317
Single and Burst Transfers
318
Table 47. Restriction on NDT Versus PSIZE and MSIZE
318
Figure 39. FIFO Structure
319
Table 48. FIFO Threshold Configurations
320
DMA Transfer Completion
321
DMA Transfer Suspension
322
Flow Controller
323
Summary of the Possible DMA Configurations
324
Table 49. Possible DMA Configurations
324
Error Management
325
DMA Interrupts
326
Table 50. DMA Interrupt Requests
326
DMA Registers
327
DMA High Interrupt Status Register (DMA_HISR)
328
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
329
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0..7)
330
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0..7)
333
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0..7)
334
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0..7)
335
Table 51. DMA Register Map and Reset Values
337
DMA2D Introduction
341
DMA2D Main Features
342
DMA2D Control
343
Table 52. Supported Color Mode in Input
344
DMA2D Foreground and Background Pixel Format Converter (PFC)
344
Table 53. Data Order in Memory
345
DMA2D Foreground and Background CLUT Interface
346
Table 56. CLUT Data Order in Memory
347
DMA2D Blender
347
Table 57. Supported Color Mode in Output
348
Table 58. Data Order in Memory
348
DMA2D Output FIFO
348
DMA2D Transactions
349
DMA2D Transfer Control (Start, Suspend, Abort and Completion)
352
Table 59. DMA2D Interrupt Requests
353
Watermark
353
DMA2D Registers
354
DMA2D Interrupt Status Register (DMA2D_ISR)
356
DMA2D Interrupt Flag Clear Register (DMA2D_IFCR)
357
DMA2D Foreground Memory Address Register (DMA2D_FGMAR)
358
DMA2D Background Memory Address Register (DMA2D_BGMAR)
359
DMA2D Foreground Color Register (DMA2D_FGCOLR)
362
DMA2D Background PFC Control Register (DMA2D_BGPFCCR)
363
DMA2D Background Color Register (DMA2D_BGCOLR)
365
DMA2D Output PFC Control Register (DMA2D_OPFCCR)
366
DMA2D Output Color Register (DMA2D_OCOLR)
367
DMA2D Output Memory Address Register (DMA2D_OMAR)
368
DMA2D Output Offset Register (DMA2D_OOR)
369
DMA2D Line Watermark Register (DMA2D_LWR)
370
Table 60. DMA2D Register Map and Reset Values
371
Nested Vectored Interrupt Controller (NVIC)
373
Table 61. Vector Table for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
374
Table 62. Vector Table for Stm32F42Xxx and Stm32F43Xxx
377
EXTI Main Features
381
EXTI Block Diagram
382
Figure 41. External Interrupt/Event Controller Block Diagram
382
Figure 42. External Interrupt/Event GPIO Mapping (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
384
Figure 43. External Interrupt/Event GPIO Mapping (Stm32F42Xxx and Stm32F43Xxx)
385
Interrupt Mask Register (EXTI_IMR)
386
Rising Trigger Selection Register (EXTI_RTSR)
387
Software Interrupt Event Register (EXTI_SWIER)
388
EXTI Register Map
389
Table 63. External Interrupt/Event Controller Register Map and Reset Values
389
Table 64. External Interrupt/Event Controller Register Map and Reset Values
389
ADC Introduction
390
ADC Functional Description
391
Figure 44. Single ADC Block Diagram
392
ADC On-Off Control
393
Table 65. ADC Pins
393
Single Conversion Mode
394
Continuous Conversion Mode
395
Figure 45. Timing Diagram
395
Figure 46. Analog Watchdog's Guarded Area
396
Scan Mode
396
Table 66. Analog Watchdog Channel Selection
396
Figure 47. Injected Conversion Latency
397
Injected Channel Management
397
Discontinuous Mode
398
Figure 48. Right Alignment of 12-Bit Data
399
Figure 49. Left Alignment of 12-Bit Data
399
Figure 50. Left Alignment of 6-Bit Data
399
Table 67. Configuring the Trigger Polarity
400
Channel-Wise Programmable Sampling Time
400
Table 68. External Trigger for Regular Channels
401
Table 69. External Trigger for Injected Channels
402
Fast Conversion Mode
402
Data Management
403
Conversions Without DMA and Without Overrun Detection
404
Figure 51. Multi ADC Block Diagram (1)
405
Injected Simultaneous Mode
407
Figure 52. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
408
Figure 53. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
408
Regular Simultaneous Mode
408
Figure 54. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
409
Figure 55. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
409
Figure 56. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
410
Figure 57. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
411
Alternate Trigger Mode
411
Figure 58. Alternate Trigger: Injected Group of each ADC
412
Figure 59. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
413
Figure 60. Alternate Trigger: Injected Group of each ADC
413
Combined Regular/Injected Simultaneous Mode
413
Figure 61. Alternate + Regular Simultaneous
414
Combined Regular Simultaneous + Alternate Trigger Mode
414
Figure 62. Case of Trigger Occurring During Injected Conversion
415
Temperature Sensor
415
Figure 63. Temperature Sensor and VREFINT Channel Block Diagram
416
Table 70. ADC Interrupts
417
Battery Charge Monitoring
417
ADC Registers
418
ADC Control Register 1 (ADC_CR1)
419
ADC Control Register 2 (ADC_CR2)
421
ADC Sample Time Register 1 (ADC_SMPR1)
423
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1..4)
424
ADC Watchdog Lower Threshold Register (ADC_LTR)
425
ADC Regular Sequence Register 2 (ADC_SQR2)
426
ADC Injected Sequence Register (ADC_JSQR)
427
ADC Regular Data Register (ADC_DR)
428
ADC Common Control Register (ADC_CCR)
429
Table 71. ADC Global Register Map
432
Table 72. ADC Register Map and Reset Values for each ADC
432
Table 73. ADC Register Map and Reset Values (Common ADC Registers)
434
Digital-To-Analog Converter (DAC)
435
Table 74. DAC Pins
436
Figure 64. DAC Channel Block Diagram
436
DAC Functional Description
437
DAC Conversion
438
Figure 65. Data Registers in Single DAC Channel Mode
438
Figure 66. Data Registers in Dual DAC Channel Mode
438
DAC Output Voltage
439
Figure 67. Timing Diagram for Conversion with Trigger Disabled TEN = 0
439
Table 75. External Triggers
439
DMA Request
440
Figure 68. DAC LFSR Register Calculation Algorithm
441
Figure 69. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
441
Triangle-Wave Generation
441
Figure 70. DAC Triangle Wave Generation
442
Figure 71. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
442
Dual DAC Channel Conversion
442
Independent Trigger with Single LFSR Generation
443
Independent Trigger with Single Triangle Generation
444
Simultaneous Trigger Without Wave Generation
445
Simultaneous Trigger with Single Triangle Generation
446
DAC Registers
447
DAC Software Trigger Register (DAC_SWTRIGR)
450
DAC Channel1 Data Output Register (DAC_DOR1)
454
Table 76. DAC Register Map
455
DAC Status Register (DAC_SR)
455
Table 77. DCMI Pins
457
Digital Camera Interface (DCMI)
457
Figure 72. DCMI Block Diagram
458
Figure 73. Top-Level Block Diagram
458
DCMI Functional Overview
458
DMA Interface
459
Figure 74. DCMI Signal Waveforms
459
Table 78. DCMI Signals
459
Table 79. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
460
Table 80. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
460
Table 81. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
460
Figure 75. Timing Diagram
461
Synchronization
461
Table 82. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
461
Capture Modes
463
Figure 76. Frame Capture Waveforms in Snapshot Mode
463
Crop Feature
464
Figure 77. Frame Capture Waveforms in Continuous Grab Mode
464
Figure 78. Coordinates and Size of the Window after Cropping
464
Figure 79. Data Capture Waveforms
465
JPEG Format
465
Figure 80. Pixel Raster Scan Order
466
Table 83. Data Storage in Monochrome Progressive Video Format
466
Data Format Description
466
Table 84. Data Storage in RGB Progressive Video Format
467
Table 85. Data Storage in Ycbcr Progressive Video Format
467
Table 86. DCMI Interrupts
467
DCMI Register Description
468
DCMI Status Register (DCMI_SR)
470
DCMI Raw Interrupt Status Register (DCMI_RIS)
471
DCMI Interrupt Enable Register (DCMI_IER)
472
DCMI Masked Interrupt Status Register (DCMI_MIS)
473
DCMI Interrupt Clear Register (DCMI_ICR)
474
DCMI Embedded Synchronization Code Register (DCMI_ESCR)
475
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)
476
DCMI Crop Window Start (DCMI_CWSTRT)
477
Table 87. DCMI Register Map and Reset Values
478
DCMI Data Register (DCMI_DR)
478
LCD-TFT Controller (LTDC)
480
Figure 81. LTDC Block Diagram
481
LTDC Functional Description
481
Table 88. LCD-TFT Pins and Signal Interface
482
Figure 82. LCD-TFT Synchronous Timings
483
Figure 83. Layer Window Programmable Parameters
485
Table 89. Pixel Data Mapping Versus Color Format
486
Figure 84. Blending Two Layers with Background
488
Figure 85. Interrupt Events
489
LTDC Interrupts
489
Table 90. LTDC Interrupt Requests
490
LTDC Programming Procedure
490
LTDC Registers
491
LTDC Active Width Configuration Register (LTDC_AWCR)
492
LTDC Total Width Configuration Register (LTDC_TWCR)
493
LTDC Shadow Reload Configuration Register (LTDC_SRCR)
495
LTDC Interrupt Enable Register (LTDC_IER)
496
LTDC Interrupt Status Register (LTDC_ISR)
497
LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)
498
LTDC Current Display Status Register (LTDC_CDSR)
499
LTDC Layerx Control Register (Ltdc_Lxcr) (Where X=1..2)
500
Ltdc_Lxwvpcr) (Where X=1..2)
501
Ltdc_Lxcfblnr) (Where X=1..2)
507
Table 91. LTDC Register Map and Reset Values
509
TIM1&TIM8 Introduction
512
TIM1&TIM8 Main Features
513
Figure 86. Advanced-Control Timer Block Diagram
514
TIM1&TIM8 Functional Description
515
Figure 87. Counter Timing Diagram with Prescaler Division Change from 1 to 2
516
Figure 88. Counter Timing Diagram with Prescaler Division Change from 1 to 4
516
Counter Modes
516
Figure 89. Counter Timing Diagram, Internal Clock Divided by 1
517
Figure 90. Counter Timing Diagram, Internal Clock Divided by 2
517
Figure 91. Counter Timing Diagram, Internal Clock Divided by 4
518
Figure 92. Counter Timing Diagram, Internal Clock Divided by N
518
Figure 93. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
518
Figure 94. Counter Timing Diagram, Update Event When ARPE=1
519
(Timx_Arr Preloaded)
519
Figure 95. Counter Timing Diagram, Internal Clock Divided by 1
520
Figure 96. Counter Timing Diagram, Internal Clock Divided by 2
520
Figure 97. Counter Timing Diagram, Internal Clock Divided by 4
520
Figure 98. Counter Timing Diagram, Internal Clock Divided by N
521
Figure 99. Counter Timing Diagram, Update Event When Repetition Counter
521
Is Not Used
521
Figure 100. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
522
Figure 101. Counter Timing Diagram, Internal Clock Divided by 2
523
Figure 102. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
523
Figure 103. Counter Timing Diagram, Internal Clock Divided by N
523
Figure 104. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
524
Figure 105. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
524
Repetition Counter
524
Figure 106. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
525
Figure 107. Control Circuit in Normal Mode, Internal Clock Divided by 1
526
Figure 108. TI2 External Clock Connection Example
526
Clock Selection
526
Figure 109. Control Circuit in External Clock Mode 1
527
Figure 110. External Trigger Input Block
528
Figure 111. Control Circuit in External Clock Mode 2
528
Capture/Compare Channels
528
Figure 112. Capture/Compare Channel (Example: Channel 1 Input Stage)
529
Figure 113. Capture/Compare Channel 1 Main Circuit
529
Figure 114. Output Stage of Capture/Compare Channel (Channel 1 to 3)
530
Figure 115. Output Stage of Capture/Compare Channel (Channel 4)
530
Input Capture Mode
530
Figure 116. PWM Input Mode Timing
532
Forced Output Mode
533
Figure 117. Output Compare Mode, Toggle on OC1
534
PWM Mode
534
Figure 118. Edge-Aligned PWM Waveforms (ARR=8)
535
Figure 119. Center-Aligned PWM Waveforms (ARR=8)
536
Complementary Outputs and Dead-Time Insertion
537
Figure 120. Complementary Output with Dead-Time Insertion
538
Figure 121. Dead-Time Waveforms with Delay Greater than the Negative Pulse
538
Figure 122. Dead-Time Waveforms with Delay Greater than the Positive Pulse
538
Using the Break Function
539
Figure 123. Output Behavior in Response to a Break
541
Figure 124. Clearing Timx Ocxref
542
Clearing the Ocxref Signal on an External Event
542
Figure 125. 6-Step Generation, COM Example (OSSR=1)
543
Step PWM Generation
543
Figure 126. Example of One Pulse Mode
544
Encoder Interface Mode
545
Table 92. Counting Direction Versus Encoder Signals
546
Figure 127. Example of Counter Operation in Encoder Interface Mode
547
Figure 128. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
547
Timer Input XOR Function
547
Interfacing with Hall Sensors
548
Figure 129. Example of Hall Sensor Interface
549
Figure 130. Control Circuit in Reset Mode
550
Timx and External Trigger Synchronization
550
Figure 131. Control Circuit in Gated Mode
551
Figure 132. Control Circuit in Trigger Mode
552
Figure 133. Control Circuit in External Clock Mode 2 + Trigger Mode
553
Table 93. Timx Internal Trigger Connection
560
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
560
TIM1&TIM8 Status Register (Timx_Sr)
562
TIM1&TIM8 Event Generation Register (Timx_Egr)
563
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
565
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
568
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
569
Break Feature
572
Table 94. Output Control Bits for Complementary Ocx and Ocxn Channels with
572
TIM1&TIM8 Counter (Timx_Cnt)
573
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
574
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
575
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
576
TIM1&TIM8 DMA Control Register (Timx_Dcr)
578
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
579
Table 95. TIM1&TIM8 Register Map and Reset Values
580
Timer Synchronization
553
TIM1&TIM8 Registers
554
TIM1&TIM8 Control Register 2 (Timx_Cr2)
555
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
558
TIM2 to TIM5 Introduction
582
Figure 134. General-Purpose Timer Block Diagram
583
TIM2 to TIM5 Functional Description
583
Figure 135. Counter Timing Diagram with Prescaler Division Change from 1 to 2
584
Figure 136. Counter Timing Diagram with Prescaler Division Change from 1 to 4
585
Counter Modes
585
Figure 137. Counter Timing Diagram, Internal Clock Divided by 1
586
Figure 138. Counter Timing Diagram, Internal Clock Divided by 2
586
Figure 139. Counter Timing Diagram, Internal Clock Divided by 4
586
Figure 140. Counter Timing Diagram, Internal Clock Divided by N
587
Figure 141. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
587
Figure 142. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
588
Figure 143. Counter Timing Diagram, Internal Clock Divided by 1
589
Figure 144. Counter Timing Diagram, Internal Clock Divided by 2
589
Figure 145. Counter Timing Diagram, Internal Clock Divided by 4
589
Figure 146. Counter Timing Diagram, Internal Clock Divided by N
590
Figure 147. Counter Timing Diagram, Update Event
590
Figure 148. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
591
Figure 149. Counter Timing Diagram, Internal Clock Divided by 2
592
Figure 150. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
592
Figure 151. Counter Timing Diagram, Internal Clock Divided by N
592
Clock Selection
593
Figure 152. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
593
Figure 153. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
593
Figure 154. Control Circuit in Normal Mode, Internal Clock Divided by 1
594
Figure 155. TI2 External Clock Connection Example
594
Figure 156. Control Circuit in External Clock Mode 1
595
Figure 157. External Trigger Input Block
595
Capture/Compare Channels
596
Figure 158. Control Circuit in External Clock Mode 2
596
Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage)
597
Figure 160. Capture/Compare Channel 1 Main Circuit
597
Figure 161. Output Stage of Capture/Compare Channel (Channel 1)
598
Input Capture Mode
598
PWM Input Mode
599
Figure 162. PWM Input Mode Timing
600
Forced Output Mode
600
Output Compare Mode
601
Figure 163. Output Compare Mode, Toggle on OC1
602
PWM Mode
602
Figure 164. Edge-Aligned PWM Waveforms (ARR=8)
603
Figure 165. Center-Aligned PWM Waveforms (ARR=8)
604
Figure 166. Example of One-Pulse Mode
605
Clearing the Ocxref Signal on an External Event
606
Encoder Interface Mode
607
Figure 167. Clearing Timx Ocxref
607
Figure 168. Example of Counter Operation in Encoder Interface Mode
608
Table 96. Counting Direction Versus Encoder Signals
608
Figure 169. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
609
Timer Input XOR Function
609
Figure 170. Control Circuit in Reset Mode
610
Figure 171. Control Circuit in Gated Mode
611
Figure 172. Control Circuit in Trigger Mode
611
Figure 173. Control Circuit in External Clock Mode 2 + Trigger Mode
612
Timer Synchronization
612
Figure 174. Master/Slave Timer Example
613
Figure 175. Gating Timer 2 with OC1REF of Timer 1
614
Figure 176. Gating Timer 2 with Enable of Timer 1
615
Figure 177. Triggering Timer 2 with Update of Timer 1
615
Figure 178. Triggering Timer 2 with Enable of Timer 1
616
Debug Mode
617
Figure 179. Triggering Timer 1 and 2 with Timer 1 TI1 Input
617
TIM2 to TIM5 Registers
618
Timx Control Register 2 (Timx_Cr2)
620
Timx Slave Mode Control Register (Timx_Smcr)
621
Table 97. Timx Internal Trigger Connection
623
Timx Dma/Interrupt Enable Register (Timx_Dier)
623
Timx Status Register (Timx_Sr)
624
Timx Event Generation Register (Timx_Egr)
626
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
627
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
630
Timx Capture/Compare Enable Register (Timx_Ccer)
631
Table 98. Output Control Bit for Standard Ocx Channels
632
Timx Counter (Timx_Cnt)
633
Timx Capture/Compare Register 1 (Timx_Ccr1)
634
Timx Capture/Compare Register 3 (Timx_Ccr3)
635
Timx DMA Control Register (Timx_Dcr)
636
TIM2 Option Register (TIM2_OR)
637
TIM5 Option Register (TIM5_OR)
638
Table 99. TIM2 to TIM5 Register Map and Reset Values
639
Timx Register Map
639
TIM9 to TIM14 Introduction
641
Figure 180. General-Purpose Timer Block Diagram (TIM9 and TIM12)
642
TIM10/TIM11 and TIM13/TIM14 Main Features
642
Figure 181. General-Purpose Timer Block Diagram (TIM10/11/13/14)
643
TIM9 to TIM14 Functional Description
644
Counter Modes
645
Figure 182. Counter Timing Diagram with Prescaler Division Change from 1 to 2
645
Figure 183. Counter Timing Diagram with Prescaler Division Change from 1 to 4
645
Figure 184. Counter Timing Diagram, Internal Clock Divided by 1
646
Figure 185. Counter Timing Diagram, Internal Clock Divided by 2
646
Figure 186. Counter Timing Diagram, Internal Clock Divided by 4
647
Figure 187. Counter Timing Diagram, Internal Clock Divided by N
647
Preloaded)
647
Clock Selection
648
Preloaded)
648
Figure 190. Control Circuit in Normal Mode, Internal Clock Divided by 1
649
Figure 191. TI2 External Clock Connection Example
649
Capture/Compare Channels
650
Figure 192. Control Circuit in External Clock Mode 1
650
Figure 193. Capture/Compare Channel (Example: Channel 1 Input Stage)
650
Figure 194. Capture/Compare Channel 1 Main Circuit
651
Figure 195. Output Stage of Capture/Compare Channel (Channel 1)
651
Input Capture Mode
651
Figure 196. PWM Input Mode Timing
653
PWM Input Mode (Only for TIM9/12)
653
Forced Output Mode
654
Figure 197. Output Compare Mode, Toggle on OC1
655
PWM Mode
655
Figure 198. Edge-Aligned PWM Waveforms (ARR=8)
656
One-Pulse Mode
656
Figure 199. Example of One Pulse Mode
657
Figure 200. Control Circuit in Reset Mode
658
TIM9/12 External Trigger Synchronization
658
Figure 201. Control Circuit in Gated Mode
659
Figure 202. Control Circuit in Trigger Mode
660
Timer Synchronization (TIM9/12)
660
TIM9 and TIM12 Registers
661
TIM9/12 Slave Mode Control Register (Timx_Smcr)
663
Table 100. Timx Internal Trigger Connection
664
TIM9/12 Interrupt Enable Register (Timx_Dier)
664
TIM9/12 Status Register (Timx_Sr)
666
TIM9/12 Event Generation Register (Timx_Egr)
667
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
669
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
672
Table 101. Output Control Bit for Standard Ocx Channels
673
TIM9/12 Counter (Timx_Cnt)
673
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
674
Table 102. TIM9/12 Register Map and Reset Values
675
TIM10/11/13/14 Registers
677
TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)
678
TIM10/11/13/14 Event Generation Register (Timx_Egr)
679
TIM10/11/13/14 Capture/Compare Mode Register
680
Table 103. Output Control Bit for Standard Ocx Channels
683
TIM10/11/13/14 Counter (Timx_Cnt)
684
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
685
Table 104. TIM10/11/13/14 Register Map and Reset Values
686
Basic Timers (TIM6&TIM7)
688
Figure 203. Basic Timer Block Diagram
688
TIM6&TIM7 Functional Description
689
Figure 204. Counter Timing Diagram with Prescaler Division Change from 1 to 2
690
Figure 205. Counter Timing Diagram with Prescaler Division Change from 1 to 4
690
Counting Mode
690
Figure 206. Counter Timing Diagram, Internal Clock Divided by 1
691
Figure 207. Counter Timing Diagram, Internal Clock Divided by 2
691
Figure 208. Counter Timing Diagram, Internal Clock Divided by 4
692
Figure 209. Counter Timing Diagram, Internal Clock Divided by N
692
Preloaded)
692
Preloaded)
693
Figure 212. Control Circuit in Normal Mode, Internal Clock Divided by 1
693
Clock Source
693
TIM6&TIM7 Registers
694
TIM6&TIM7 Control Register 2 (Timx_Cr2)
695
TIM6&TIM7 Status Register (Timx_Sr)
696
TIM6&TIM7 Prescaler (Timx_Psc)
697
Table 105. TIM6&TIM7 Register Map and Reset Values
698
Independent Watchdog (IWDG)
699
Table 106. Min/Max IWDG Timeout Period at 32 Khz (LSI)
700
Figure 213. Independent Watchdog Block Diagram
700
Debug Mode
700
IWDG Registers
701
Reload Register (IWDG_RLR)
702
Table 107. IWDG Register Map and Reset Values
703
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STMicroelectronics STM32F439 Manual (36 pages)
Brand:
STMicroelectronics
| Category:
Microcontrollers
| Size: 0.43 MB
Table of Contents
Table 1. Device Identification
1
Table 2. Device Summary
1
Table of Contents
2
ARM 32-Bit Cortex-M4 with FPU Limitations
7
Cortex-M4 Interrupted Loads to Stack Pointer Can Cause
7
Erroneous Behavior
7
Table 3. Cortex-M4 Core Limitations and Impact on Microcontroller Behavior
7
Stm32F42Xx and Stm32F43Xx Silicon Limitations
8
Table 4. Summary of Silicon Limitations
8
System Limitations
10
Debugging Stop Mode and System Tick Timer
10
Debugging Stop Mode with WFE Entry
10
Wakeup Sequence from Standby Mode When Using more than
11
One Wakeup Source
11
Full JTAG Configuration Without NJTRST Pin Cannot be Used
11
MPU Attribute to RTC and IWDG Registers Could be Managed
12
Incorrectly
12
Delay after an RCC Peripheral Clock Enabling
12
Internal Noise Impacting the ADC Accuracy
12
Over-Drive and Under-Drive Modes Unavailability
13
IWDG Peripheral Limitation
13
RVU and PVU Flags Are Not Reset in STOP Mode
13
I2C Peripheral Limitations
13
Smbus Standard Not Fully Supported
13
Start Cannot be Generated after a Misplaced Stop
14
Mismatch on the "Setup Time for a Repeated Start Condition" Timing Parameter
14
Data Valid Time (T VD;DAT ) Violated Without the OVR Flag Being Set
14
Higher than ((VDD+0.3) / 0.7) V
15
I2S Peripheral Limitation
15
In I2S Slave Mode, WS Level Must be Set by the External Master When Enabling the I2S
15
USART Peripheral Limitations
16
Idle Frame Is Not Detected if Receiver Clock Speed Is Deviated
16
In Full Duplex Mode, the Parity Error (PE) Flag Can be Cleared by Writing to the Data Register
16
Parity Error (PE) Flag Is Not Set When Receiving in Mute Mode Using Address Mark Detection
16
Break Frame Is Transmitted Regardless of Ncts Input Line Status
17
Nrts Signal Abnormally Driven Low after a Protocol Violation
17
OTG_FS Peripheral Limitations
17
Data in Rxfifo Is Overwritten When All Channels Are Disabled
17
Simultaneously
17
OTG Host Blocks the Receive Channel When Receiving in Packets and no
18
Txfifo Is Configured
18
Host Channel-Halted Interrupt Not Generated When the Channel Is
18
Disabled
18
Error in Software-Read OTG_FS_DCFG Register Values
18
Ethernet Peripheral Limitations
19
Incorrect Layer 3 (L3) Checksum Is Inserted in Transmitted Ipv6 Packets Without TCP, UDP or ICMP Payloads
19
The Ethernet MAC Processes Invalid Extension Headers in the Received
19
Ipv6 Frames
19
MAC Stuck in the Idle State on Receiving the Txfifo Flush Command Exactly 1 Clock Cycle after a Transmission Completes
19
Transmit Frame Data Corruption
20
Successive Write Operations to the same Register Might Not be Fully
20
Taken into Account
20
Table 5. Impacted Registers and Bits
20
FMC Peripheral Limitation
23
Dummy Read Cycles Inserted When Reading Synchronous Memories
23
FMC Synchronous Mode and NWAIT Signal Disabled
23
Read Access to a Non-Initialized FMC_SDRAM Bank
23
Corruption of Data Read from the FMC
24
Interruption of CPU Read Burst Access to an End of SDRAM Row
24
FMC NOR/PSRAM Controller: Asynchronous Read Access on Bank 2 to 4
24
Returns Wrong Data When Bank 1 Is in Synchronous Mode
24
(BURSTEN Bit Is Set)
24
FMC Dynamic and Static Banks Switching
25
SDIO Peripheral Limitations
25
SDIO HW Flow Control
25
Wrong CCRCFAIL Status after a Response Without CRC Is Received
25
Data Corruption in SDIO Clock Dephasing (NEGEDGE) Mode
26
CE-ATA Multiple Write Command and Card Busy Signal Management
26
No Underrun Detection with Wrong Data Transmission
26
ADC Peripheral Limitations
27
ADC Sequencer Modification During Conversion
27
DAC Peripheral Limitations
27
DMA Underrun Flag Management
27
Figure 1. TFBGA216 Top Package View
29
Figure 2. WLCSP143 Top Package View
30
Figure 3. LQFP208 Top Package View
30
Figure 4. UFBGA176 Top Package View
31
Figure 5. LQFP176 Top Package View
32
Figure 6. LQFP144 Top Package View
33
Figure 7. LQFP100 Top Package View
34
Table 6. Document Revision History
35
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