Hitachi SH7750 Hardware Manual page 467

Sh7750 series superh risc engine

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Precharge-sel

(SA: IO ← memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.28 Basic Timing for Synchronous DRAM Burst Read

In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the start of the data

transfer cycle corresponding to the READ or READA command. The order of access is as

follows: in a fill operation in the event of a cache miss, 64-bit boundary data including the missed

data is read first, then 16-byte boundary data including the missed data is read in wraparound

mode. The remaining 16 bytes of the 32-byte boundary data are read by the READA command

issued next.

Rev. 6.0, 07/02, page 417 of 986

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