Hitachi SH7750 Hardware Manual page 25

9.4.2 Exit from Deep Sleep Mode ................................................................................ 231
9.5 Standby Mode ................................................................................................................... 231
9.5.1 Transition to Standby Mode................................................................................. 231
9.5.2 Exit from Standby Mode...................................................................................... 232
9.5.3 Clock Pause Function .......................................................................................... 232
9.6 Module Standby Function................................................................................................. 233
9.6.1 Transition to Module Standby Function .............................................................. 233
9.6.2 Exit from Module Standby Function ................................................................... 234
9.7 Hardware Standby Mode (SH7750S, SH7750R Only) ..................................................... 235
9.7.1 Transition to Hardware Standby Mode................................................................ 235
9.7.2 Exit from Hardware Standby Mode ..................................................................... 235
9.7.3 Usage Notes ......................................................................................................... 235
9.8 STATUS Pin Change Timing ........................................................................................... 236
9.8.1 In Reset ................................................................................................................ 237
9.8.2 In Exit from Standby Mode ................................................................................. 238
9.8.3 In Exit from Sleep Mode...................................................................................... 240
9.8.4 In Exit from Deep Sleep Mode ............................................................................ 242
9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) ........................... 244
Section 10 Clock Oscillation Circuits
10.1 Overview........................................................................................................................... 247
10.1.1 Features................................................................................................................ 247
10.2 Overview of CPG.............................................................................................................. 249
10.2.1 Block Diagram of CPG........................................................................................ 249
10.2.2 CPG Pin Configuration ........................................................................................ 252
10.2.3 CPG Register Configuration ................................................................................ 252
10.3 Clock Operating Modes .................................................................................................... 253
10.4 CPG Register Description ................................................................................................. 254
10.4.1 Frequency Control Register (FRQCR)................................................................. 254
10.5 Changing the Frequency ................................................................................................... 257
10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off) ........... 257
10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On) ............ 257
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) ...................... 258
10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)...................... 258
10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ............................... 258
10.6 Output Clock Control........................................................................................................ 258
10.7 Overview of Watchdog Timer .......................................................................................... 259
10.7.1 Block Diagram..................................................................................................... 259
10.7.2 Register Configuration......................................................................................... 260
10.8 WDT Register Descriptions .............................................................................................. 260
10.8.1 Watchdog Timer Counter (WTCNT)................................................................... 260
10.8.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 261
10.8.3 Notes on Register Access..................................................................................... 263
........................................................................... 247
Rev. 6.0, 07/02, page xxv of I