Number Of Bus Cycle States And Dreq Pin Sampling Timing - Hitachi SH7750 Hardware Manual

CPU DMAC CH1
CPU DMAC channel 1
burst mode
Priority system: Round robin mode
Channel 0:
Channel 1:
Figure 14.11 Bus Handling with Two DMAC Channels Operating
Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the
bus is passed to the CPU during a break in requests.
Number of Bus Cycle States and DREQ
14.3.5
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. See section 13, Bus State Controller (BSC), for details.
DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled at the rising DREQ DREQ DREQ
edge of CKIO clock pulses. When DREQ input is detected, a DMAC bus cycle is generated and
DMA transfer executed after four CKIO cycles at the earliest.
The second and subsequent DREQ sampling operations are performed one cycle after the start of
the first DMAC transfer bus cycle (in the case of single address mode).
DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer
mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in
the first cycle only, and so DRAK is output in the first cycle only .
Operation: Figures 14.12 to 14.22 show the timing in each mode.
1. Cycle Steal Mode
In cycle steal mode, The DREQ sampling timing differs for dual address mode and single
address mode, and for level detection and edge detection of DREQ.
For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC
transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second
sampling operation is performed one cycle after the start of the first DMAC transfer write
cycle. If DREQ is not detected at this time, sampling is executed in every subsequent cycle.
DMAC CH1 DMAC CH0
CH0
DMAC channel 0 and
channel 1 round robin
mode
Cycle steal mode
Burst mode (edge-sensing)
DREQ Pin Sampling Timing DREQ DREQ
DMAC CH1 DMAC CH0
CH1 CH0
Rev. 6.0, 07/02, page 527 of 986
DMAC CH1 DMAC CH1
DMAC channel 1
burst mode
CPU
CPU