Hardware Standby Mode Timing (Sh7750S, Sh7750R Only); Figure 9.12 Hardware Standby Mode Timing (When Ca = Low In Normal Operation) - Hitachi SH7750 Hardware Manual

9.8.5

Hardware Standby Mode Timing (SH7750S, SH7750R Only)

Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode.
The CA pin level must be kept low while in hardware standby mode.
After setting the RESET pin level low, the clock starts when the CA pin level is switched to high.
CKIO
SCK2
STATUS
Notes: *1 Same at sleep and reset.
*2 Undefined
*3 High impedance when STBCR2. STHZ = 0
Rev. 6.0, 07/02, page 244 of 986
CA
(High)
*1
Normal
0–10 Bcyc
Waiting for end of bus cycle
Figure 9.12 Hardware Standby Mode Timing
(When CA = Low in Normal Operation)
*3
Standby
*2
0–10 Bcyc
Reset