HP 3000 III Series Manual page 82

System/CPU Overview
and W special use bits go to the Preadder Control. (The W bit
also goes to the Mapper Control.) The JULI special
USE
bit goes
to the BMUX Control and CMUX Control.
The 12-bit microprogram starting addreES from LUT is applied to
the
VBns
HUX. The VBDS MUX outputs 16 bits to the RO~1 and In-
crement (INC). The 16 bits applied to the ROM is the starting
address for the microcode instruction providing no special con-
ditions such as stack pre-adjust are needed. The 32-bit ROM
output is clocked into RORI. At the same time that the ROM is
being accessed, the starting address is being sent to the INC
circuit. During the same clock cycle that clocks the ROM output
to RORl, the address-pIus-one is applied to the Address l~gister
(RAR). rrhe output of RAR goes back to the VBUSMUX. When, doing
the next clock cycle, the incremented address goes to ROH, the
new microcode instruction
gOES
to RORl and the original microcode
instruction goes from RORI to ROR2. The microcode pipeline is
now packed, functioning, and incrementing one step at a time
through the microcode. (Refer to paragraph 2-86 for microcode
jump information.)
2-75. CPU Component Descriptions
The logical component.s of the CPU shown in figure 2-20 are des-
cribed in paragraphs 2-76 through 2-128.
2-76. NIR. The NIR is a l6-bit register that is loaded with an
instruction from Main Memory and provides storage for that in-
struction until the current instruction has been executed. This
allows an instruction to be fetched from memory concurrently with
the execution of the current instruction. The NIR is loaded by
an NIP signal from the Meu operation decoder. The NIP signal is
generated as a result of a microcode instruction Skip field code
NEXT or the HCU fie ld code NIR as des cr ibed in
Se
ction V.
2-77e CIR. The CIR is a l6-bit register that contains the in-
struction currently being executed by the CPU. The CIR is loaded
by an NIRTOCIR signal from the Next. Control. The NIRTOCIR signal
is generated as a result of a microcode instruction Skip field
code
NEXT
or by the clock cycle after a Special field code CCPX
as described in Section V. As previously discussed, if the pipe-
line has not been filled, the contents of the NIR goes directly
to both the CIR and c~mx to save one clock cycle. The NIR and
crR allow one clock cycle to fetch one instruction from memory
while the previous clock cycle is still executing an instruction.
Instr uction tr'anslat ion is accompl ished f rom the
eIR
two clock
cycles after the execution has begun until the execution is com-
plete unless it is the right instruction of a stack-op. In the
case of a Right Stack-Op instruction, the entire translation is
accomplished from the CIR. The controlling factor concerning the
execution of a Right Stack-Op instruction is the BMUX Control.
2-50