HP 3000 III Series Manual page 297

I/O System
sent to the lOP along with INT ACK. On receipt of INT ACK, the
lOP generates an Interrupt signal to the CPU.
7-54. Jump. The Jump order may be specified to be either
conditional or unconditional. It is the function of an uncondi-
tioned jump or a successful condi tional jump to transfer the con-
tents of the IOAW Buffer (the jump address) to the I/O Program
Counter. (The IOAW Buffer and IOAW Active Register contain iden-
tical contents at this time.) In the case of a conditional jump
order, the Selector Channel issues a Set Jump command to the De-
vice Controller, with CHANSO, via the Selector Channel Bus. The
Device Controller returns a true or false Jump Met signal. If
the jump is not met, operation returns to the fetch sequence. If
the jump is met for an Unconditional Jump order, the channel con-
trol logic gates the contents of the IOAW Active Register into
the I/O Program Counter. Thus, subsequent ordeis will be fetched
and executed from a new I/O program area.
7-55. Control. The Control order routes both the IOCW and the
IOAW to the Device Controller. The Selector Channel first reads
out the contents of the IOCW Active Register to the channel DATA
lines and issues a PCMDl (Programmed Command One) signal, with
CHANSO, for the Device Controller to load the data word. The
Device Controller accordingly loads the word into its Cbntrol
Register and then issues a request (CHAN SR) back to the selector
Channel to send the second word. The Selector Channel reads out
the contents of the IOAW Active Register to the DATA lines and
issues a second command (P CONT STB), with CHANSO, for the Device
Controller to load this new word. When the Device Controller has
loaded the new word and is ready for the next order, it returns
the appropriate response (another CHAN SR) signal to the Selector
Channel.
7-56. Set Bank. When requesting a memory Read or Write (for
data words only), an IOAW word goes into the Selector Channel
(figure 7-19) on the PCD lines and the four least significant
bits are loaded into the Bank Register by the Set Bank order.
Two b its from the Bank Registe r (TOl-l and TOl-2) are ga ted
through the MOD select switches and Port Controller to become the
memory module TO signal on the CTL Bus. The remaining two bits
from the Bank Register (PB14 and PB15) are applied back through
the Port Controller via the PC Bus to become part of the memory
module 18-bit address (see figures 6-2 and 7-17 through 7-19) on
the CTL Bus.
7-57. Read. The Read order causes a block of data to be trans-
ferred from the device to memory. The block size in words is
specified in two's complement form by the word count (IOCW bits 4
through 15) and the absolute starting address in memory is speci-
fied by the IOAW. While the block transfer is in progress, there
are two separate, simultaneous operations taking place: the
device-to-channel transfer and the channel-to-rnernory transfer.
To begin the Read execute sequence, the Selector Channel issues
CHANSO to the Device Controller. (See figure 7-18 and 7-19.) When
the controller returns CHAN ACK, the Selector Channel issues the
7-43