Lcd Panel; March 2005 © Toshiba Tec - Toshiba e-STUDIO520 Service Manual

2) Block diagram
HV
NC
NC
GND
Temperature compensated circuit
VEE
VLCD
FRM
LOAD
DF
DISP
CP
D3-D0
e-STUDIO520/600/720/850 CONTROL PANEL
Rth
Bias ratio generation circuit
V0
V1
V2
IC1
V3
V4
VDD
VSS
(1, 1) (1, 2) ······················································ (1, 640)
D101
(2, 1) (2, 2) ······················································ (2, 640)
120 Out
D102
Com1
D101
120 Out
D102
(240, 1) (240, 2) ·········································· (240, 640)
Com2
VDD,
160 Out
V0,
V1,
Seg1
E102
V4,
VSS
VDD, V0, V2, V3, VSS
Fig.5-6
5 - 14
CCFT

LCD panel

640 x 240 Dots
160 Out
Seg4
E101 E102 E101
March 2005 © TOSHIBA TEC