Strongarm Sa-1110 Register Configuration - Epson S1D13706 Technical Manual

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4.3 StrongARM SA-1110 Register Configuration

Table 4-3: RDFx Parameter Value versus CPU Maximum Frequency
Interfacing to the Intel StrongARM SA-1110 Microprocessor
Issue Date: 02/06/26
The SA-1110 requires configuration of several of its internal registers to interface to the
S1D13706 Generic #2 Host Bus Interface.
• The Static Memory Control Registers (MSC[2:0]) are read/write registers containing
control bits for configuring static memory or variable-latency IO devices. These regis-
ters correspond to chip select pairs nCS[5:4], nCS[3:2], and nCS[1:0] respectively. Each
of the three registers contains two identical CNFG fields, one for each chip select within
the pair. Since only nCS[5:3] controls variable-latency IO devices, MSC2 and MSC1
should be programmed based on the chip select used.
Parameter RTx<1:0> should be set to 01b (selects variable-latency IO mode).
Parameter RBWx should be set to 1 (selects 16-bit bus width).
Parameter RDFx<4:0> should be set according to the maximum desired CPU
frequency as indicated in the table below.
CPU Frequency (MHz)
57.3 - 85.9
88.5 - 143.2
147.5 - 200.5
206.4 - 221.2
Parameter RDNx<4:0> should be set to 0 (minimum command precharge time).
Parameter RRRx<2:0> should be set to 0 (minimum nCSx precharge time).
• The S1D13706 endian mode is set to little endian. To program the SA-1110 for little
endian set bit 7 of the control register (register 1) to 0.
• The CLKI signal input to the S1D13706 from one of the SDCLK[2:1] pins is a deriva-
tive of the SA-1110 internal processor speed (either divide by 2 or 4). The S1D13706
Generic #2 Host Bus Interface has a maximum BCLK of 50MHz. Therefore, if the
processor clock is higher than 100MHz, either divide the BCLK input using the
S1D13706 configuration pins CNF[7:6] (see Table 4-2: "CLKI to BCLK Divide Selec-
tion" ) or set SDCLK1/SDCLK2 to CPU clock divided by four using the DRAM
Refresh Control Register (MDREFR bit 26 = 1 for SDCLK2, MDREFR bit 22 = 1 for
SDCLK1).
RDFx
1
2
3
4
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