Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 TECHNICAL MANUAL X31B-Q-001-06 Issue Date: 01/04/17...
Page 3: Riesstrasse
Epson Research and Development Page 3 Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation • Technical manuals • Evaluation/Demonstration board manual Evaluation/Demonstration Board •...
Page 4 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 TECHNICAL MANUAL X31B-Q-001-06 Issue Date: 01/04/17...
Page 5 The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer. While supporting all other panel types, the S1D13706 is the only LCD controller to directly interface to both the Epson D-TFD and the Sharp HR-TFT family of products thus removing the requirement of an external Timing Control IC.
Page 6 Copyright © 2000, 2001 Epson Research and Development, Inc. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/ EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
Page 7: Hardware Functional Specification
The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners...
Page 8 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Hardware Functional Specification X31B-A-001-08 Issue Date: 01/11/13...
Page 9: Table Of Contents
Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........11 Scope .
Page 10 6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) ..80 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) ....82 6.4.13 320x240 Epson D-TFD Panel Timing (e.g.
Page 11 Epson Research and Development Page 5 Vancouver Design Center 8.3.6 Picture-in-Picture Plus (PIP+) Registers ..... . . 115 8.3.7 Miscellaneous Registers ....... . 120 8.3.8...
Page 12 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Hardware Functional Specification X31B-A-001-08 Issue Date: 01/11/13...
Page 13 Epson Research and Development Page 7 Vancouver Design Center List of Tables Table 4-1: CFLGA Pin Mapping ........19 Table 4-2: Pinout Assignments - Die Form (S1D13706D00A) .
Page 14 Table 8-1: S1D13706 Register Set ........
Page 15 Epson Research and Development Page 9 Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram (Generic #1 Bus) ......14 Figure 3-2: Typical System Diagram (Generic #2 Bus) .
Page 16 Figure 6-35: 160x240 Epson D-TFD Panel GCP Horizontal Timing ....84 Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing ..... . .85 Figure 6-37: 320x240 Epson D-TFD Panel Horizontal Timing .
Page 17: Introduction
The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer. While supporting all other panel types, the S1D13706 is the only LCD controller to directly interface to both the Epson D-TFD and the Sharp HR-TFT family of products thus removing the requirement of an external Timing Control IC.
Page 18: Features
• Single-panel, single-drive passive displays. • 4/8-bit monochrome LCD interface. • 4/8/16-bit color LCD interface. • Active Matrix TFT interface. • 9/12/18-bit interface. • ‘Direct’ support for 18-bit Epson D-TFD interface. • ‘Direct’ support for 18-bit Sharp HR-TFT interface. S1D13706 Hardware Functional Specification X31B-A-001-08...
Page 19: Display Modes
Epson Research and Development Page 13 Vancouver Design Center 2.4 Display Modes • 1/2/4/8/16 bit-per-pixel (bpp) color depths. • Up to 64 gray shades using Frame Rate Modulation (FRM) and dithering on mono- chrome passive LCD panels. • Up to 64K colors on passive STN panels.
Page 20: Figure 3-1: Typical System Diagram (Generic #1 Bus)
Page 14 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Oscillator Generic #1 HIOVDD 16-bit Single FPDAT[15:0] D[15:0] M/R# A[27:17] Decoder FPFRAME FPFRAME Display CSn# FPLINE FPLINE A[16:1] AB[16:1] FPSHIFT FPSHIFT D[15:0] DB[15:0] DRDY S1D13706 WE0#...
Page 21: Figure 3-3: Typical System Diagram (Hitachi Sh-4 Bus)
Epson Research and Development Page 15 Vancouver Design Center Oscillator SH-4 12-bit A[25:17] M/R# Decoder FPDAT15 FPDAT12 Display CSn# FPDAT[9:0] D[9:0] FPFRAME FPFRAME A[16:1] AB[16:1] FPLINE FPLINE D[15:0] DB[15:0] FPSHIFT FPSHIFT WE0# WE0# DRDY DRDY WE1# WE1# S1D13706 RD/WR# RD/WR#...
Page 22: Figure 3-5: Typical System Diagram (Mc68K # 1, Motorola 16-Bit 68000)
Page 16 Epson Research and Development Vancouver Design Center Oscillator MC68K #1 HIOVDD FPDAT[17:0] D[17:0] 18-bit WE0# FPFRAME HR-TFT A[23:17] FPLINE M/R# Decoder Display FC0, FC1 FPSHIFT GPIO0 Decoder GPIO1 A[16:1] AB[16:1] GPIO2 D[15:0] DB[15:0] GPIO3 S1D13706 LDS# UDS# WE1#...
Page 23: Figure 3-7: Typical System Diagram (Motorola Redcap2 Bus)
Epson Research and Development Page 17 Vancouver Design Center Oscillator REDCAP2 HIOVDD 4-bit M/R# A[21:17] Decoder Single FPDAT[7:4] D[3:0] FPSHIFT FPSHIFT Display A[16:1] AB[16:1] FPFRAME FPFRAME D[15:0] DB[15:0] FPLINE FPLINE DRDY S1D13706 RD/WR# WE0# WE1# CLKI RESET_OUT RESET# *Note: CSn# can be any of CS0-CS4...
Page 24: Pinout Diagram - Tqfp15 - 100Pin
Page 18 Epson Research and Development Vancouver Design Center 4 Pins 4.1 Pinout Diagram - TQFP15 - 100pin NIOVDD CLKI2 NIOVDD CNF7 DRDY CNF6 CNF5 CVOUT CNF4 GPIO0 CNF3 GPIO1 CNF2 GPIO2 CNF1 GPIO3 CNF0 GPIO4 TESTEN GPIO5 AB16 GPIO6...
Page 25: Table 4-1: Cflga Pin Mapping
Epson Research and Development Page 19 Vancouver Design Center 4.2 Pinout Diagram - CFLGA - 104pin 10 11 BOTTOM VIEW Figure 4-2: Pinout Diagram - CFLGA - 104pin (S1D13706B00A) Table 4-1: CFLGA Pin Mapping NIOVDD GPIO0 GPIO4 COREVDD GPIO2 GPIO6...
Page 26: Pinout Diagram - Die Form
Page 20 Epson Research and Development Vancouver Design Center 4.3 Pinout Diagram - Die Form DIE No. X5534D Unusable Pad (0,0) Unusable Pad Figure 4-3: Pinout Diagram - Die Form (S1D13706D00A) Chip Size: 5.88 x 6.55 mm µ PAD size: 68 x 68...
Page 27: Table 4-2: Pinout Assignments - Die Form (S1D13706D00A)
Epson Research and Development Page 21 Vancouver Design Center Table 4-2: Pinout Assignments - Die Form (S1D13706D00A) Pin No. Pad No. Pin Name X (µm) Y (µm) Pin No. Pad No. Pin Name X (µm) Y (µm) LVDD -2331 -3149...
Page 28: Table 4-3: Host Interface Pin Descriptions
Page 22 Epson Research and Development Vancouver Design Center 4.4 Pin Descriptions Key: Input Output Bi-Directional (Input/Output) Power pin LVTTL Schmitt input LVTTL input LB2A LVTTL IO buffer (6mA/-6mA@3.3V) LB3P Low noise LVTTL IO buffer (12mA/-12mA@3.3V) Low noise LVTTL Output buffer (12mA/-12mA@3.3V) LB3M Low noise LVTTL IO buffer with input mask (12mA/-12mA@3.3V)
Page 29 HIOVDD on page 30 for summary. This input pin is used to select between the display buffer and register address spaces of the S1D13706. M/R# is set high to M/R# HIOVDD access the display buffer and low to access the registers. See Table 4-9: “Host Bus Interface Pin Mapping,”...
Page 30 (RD1#). • For Generic #2, this pin must be tied to HIO V • For SH-3/SH-4, this pin inputs the RD/WR# signal. The S1D13706 needs this signal for early decode of the bus cycle. RD/WR# HIOVDD • For MC68K #1, this pin inputs the R/W# signal.
Page 31 Epson Research and Development Page 25 Vancouver Design Center Table 4-3: Host Interface Pin Descriptions RESET# Pin Name Type Pin # Cell Description Voltage State During a data transfer, this output pin is driven active to force the system to insert wait states. It is driven inactive to indicate the completion of a data transfer.
Page 32: Table 4-4: Lcd Interface Pin Descriptions
• Frame Pulse • SPS for Sharp HR-TFT FPFRAME LB3P NIOVDD • DY for Epson D-TFD See Table 4-10: “LCD Interface Pin Mapping,” on page 31 for summary. This output pin has multiple functions. • Line Pulse • LP for Sharp HR-TFT...
Page 33 Cell Description Voltage State This pin has multiple functions. • REV for Sharp HR-TFT • FR for Epson D-TFD GPIO2 LB3M NIOVDD • General purpose IO pin 2 (GPIO2) See Table 4-10: “LCD Interface Pin Mapping,” on page 31 for summary.
Page 34: Table 4-5: Clock Input Pin Descriptions
RESET# Pin Name Type Pin # Cell Description Voltage State These inputs are used to configure the S1D13706 - see Table 4-8: “Summary of Power-On/Reset Options,” on page 29. CNF[7:0] 78-85 NIOVDD — Note: These pins are used for configuration of the S1D13706...
Page 35: Table 4-8: Summary Of Power-On/Reset Options
Page 29 Vancouver Design Center 4.5 Summary of Configuration Options These pins are used for configuration of the S1D13706 and must be connected directly to NIOV or V . The state of CNF[6:0] is latched on the rising edge of RESET#. Changing state at any other time has no effect.
Page 36: Table 4-9: Host Bus Interface Pin Mapping
RESET# RESET_OUT RESET Note A0 for these busses is not used internally by the S1D13706 and should be connected to V If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. S1D13706 Hardware Functional Specification...
Page 37: Table 4-10: Lcd Interface Pin Mapping
When the HR-TFT interface is selected (REG[10h] bits 1-0 = 10), this GPO can be used to control the HR-TFT MOD signal. Note this is not the same signal as the S1D13706 DRDY(MOD) signal used for passive panels. Hardware Functional Specification...
Page 38: Table 5-1: Absolute Maximum Ratings
= 0 V Input Voltage IO V ° C Operating Temperature Note The S1D13706 requires that Core VDD ≤ HIO VDD and Core VDD ≤ NIO VDD. Table 5-3: Electrical Characteristics for VDD = 3.3V typical Symbol Parameter Condition Units µA...
Page 39: Table 6-1: Clock Input Requirements For Clki When Clki To Bclk Divide > 1
Epson Research and Development Page 33 Vancouver Design Center 6 A.C. Characteristics Conditions: HIO V = 2.0V ± 10% and HIO V = 3.3V ± 10% NIO V = 3.3V ± 10% = -40° C to 85° C and T for all inputs must be <...
Page 40: Table 6-2: Clock Input Requirements For Clki When Clki To Bclk Divide = 1
Page 34 Epson Research and Development Vancouver Design Center Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 2.0V 3.3V Symbol Parameter Units Input Clock Frequency (CLKI) Input Clock period (CLKI) Input Clock Pulse Width High (CLKI)
Page 41: Table 6-4: Internal Clock Requirements
Epson Research and Development Page 35 Vancouver Design Center 6.1.2 Internal Clocks Table 6-4: Internal Clock Requirements 2.0V 3.3V Symbol Parameter Units Bus Clock frequency BCLK Memory Clock frequency MCLK Pixel Clock frequency PCLK PWM Clock frequency PWMCLK Note For further information on internal clocks, refer to Section 7, “Clocks” on page 90.
Page 42: Cpu Interface Timing
Page 36 Epson Research and Development Vancouver Design Center 6.2 CPU Interface Timing The following section includes CPU interface AC Timing for both 2.0V and 3.3V. The 2.0V timings are based on HIO V = Core V = 2.0V. The 3.3V timings are based on...
Page 43: Table 6-5: Generic #1 Interface Timing
Epson Research and Development Page 37 Vancouver Design Center Table 6-5: Generic #1 Interface Timing 2.0V 3.3V Symbol Parameter Unit Bus Clock frequency Bus Clock period Clock pulse width high 22.5 Clock pulse width low 22.5 A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and...
Page 44: Figure 6-3: Generic #2 Interface Timing
Page 38 Epson Research and Development Vancouver Design Center 6.2.2 Generic #2 Interface Timing (e.g. ISA) BUSCLK BUSCLK SA[16:0] M/R#, SBHE# MEMR# MEMW# IOCHRDY SD[15:0] (write) SD[15:0] (read) VALID Figure 6-3: Generic #2 Interface Timing S1D13706 Hardware Functional Specification X31B-A-001-08...
Page 45: Table 6-6: Generic #2 Interface Timing
Epson Research and Development Page 39 Vancouver Design Center Table 6-6: Generic #2 Interface Timing 2.0V 3.3V Symbol Parameter Unit Bus Clock frequency BUSCLK Bus Clock period BUSCLK BUSCLK BUSCLK Clock pulse width high 22.5 Clock pulse width low 22.5...
Page 46: Figure 6-4: Hitachi Sh-4 Interface Timing
Page 40 Epson Research and Development Vancouver Design Center 6.2.3 Hitachi SH-4 Interface Timing CKIO CKIO A[16:1], M/R# RD/WR# CSn# WEn# Hi-Z Hi-Z RDY# D[15:0] Hi-Z Hi-Z (write) D[15:0] Hi-Z Hi-Z VALID (read) Figure 6-4: Hitachi SH-4 Interface Timing S1D13706...
Page 47: Table 6-7: Hitachi Sh-4 Interface Timing
Epson Research and Development Page 41 Vancouver Design Center Table 6-7: Hitachi SH-4 Interface Timing 2.0V 3.3V Symbol Parameter Unit Clock frequency CKIO Clock period CKIO CKIO CKIO 22.5 Clock pulse width low 22.5 Clock pulse width high A[16:1], M/R#, RD/WR# setup to CKIO...
Page 48: Figure 6-5: Hitachi Sh-3 Interface Timing
Page 42 Epson Research and Development Vancouver Design Center 6.2.4 Hitachi SH-3 Interface Timing CKIO CKIO A[16:1], M/R# RD/WR# CSn# WEn# Hi-Z Hi-Z WAIT# D[15:0] Hi-Z Hi-Z (write) D[15:0] Hi-Z Hi-Z VALID (read) Figure 6-5: Hitachi SH-3 Interface Timing S1D13706...
Page 49: Table 6-8: Hitachi Sh-3 Interface Timing
Epson Research and Development Page 43 Vancouver Design Center Table 6-8: Hitachi SH-3 Interface Timing 2.0V 3.3V Symbol Parameter Unit Bus Clock frequency CKIO Bus Clock period CKIO CKIO CKIO 22.5 Bus Clock pulse width low 22.5 Bus Clock pulse width high...
Page 50: Figure 6-6: Motorola Mc68K #1 Interface Timing
Page 44 Epson Research and Development Vancouver Design Center 6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000) A[16:1] M/R# UDS# LDS# R/W# DTACK# D[15:0](write) D[15:0](read) VALID Figure 6-6: Motorola MC68K #1 Interface Timing S1D13706 Hardware Functional Specification X31B-A-001-08 Issue Date: 01/11/13...
Page 51: Table 6-9: Motorola Mc68K #1 Interface Timing
Epson Research and Development Page 45 Vancouver Design Center Table 6-9: Motorola MC68K #1 Interface Timing 2.0V 3.3V Symbol Parameter Unit Bus Clock Frequency Bus Clock period Clock pulse width high 22.5 Clock pulse width low 22.5 A[16:1], M/R# setup to first CLK rising edge where CS# = 0,...
Page 52: Figure 6-7: Motorola Mc68K #2 Interface Timing
Page 46 Epson Research and Development Vancouver Design Center 6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030) A[16:0] M/R#, SIZ[1:0] R/W# DSACK1# D[31:16](write) D[31:16](read) VALID Figure 6-7: Motorola MC68K #2 Interface Timing Note For information on the implementation of the Motorola 68K #2 Host Bus Interface, see Interfacing To The Motorola MC68030 Microprocessor, document number X31B-G-013-xx.
Page 53: Table 6-10: Motorola Mc68K #2 Interface Timing
Epson Research and Development Page 47 Vancouver Design Center Table 6-10: Motorola MC68K #2 Interface Timing 2.0V 3.3V Symbol Parameter Unit Bus Clock frequency Bus Clock period Clock pulse width high 22.5 Clock pulse width low 22.5 A[16:0], SIZ[1:0], M/R# setup to first CLK rising edge where...
Page 54: Figure 6-8: Motorola Redcap2 Interface Timing
Page 48 Epson Research and Development Vancouver Design Center 6.2.7 Motorola REDCAP2 Interface Timing M/R# A[16:1] (write) D[15:0] Hi-Z Hi-Z VALID (write) (read) D[15:0] Hi-Z Hi-Z VALID (read) Note: CSn may be any of CS0 - CS4. Figure 6-8: Motorola REDCAP2 Interface Timing...
Page 55: Table 6-11: Motorola Redcap2 Interface Timing
Epson Research and Development Page 49 Vancouver Design Center Table 6-11: Motorola REDCAP2 Interface Timing 2.0V 3.3V Symbol Parameter Units Bus Clock frequency Bus Clock period Bus Clock pulse width low Bus Clock pulse width high A[16:1], M/R#, R/W, CSn setup to CKO rising edge...
Page 56: Figure 6-9: Motorola Dragonball Interface With Dtack Timing
Page 50 Epson Research and Development Vancouver Design Center 6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) CLKO CLKO A[16:1] UWE/LWE (write) (read) D[15:0] Hi-Z Hi-Z (write) Hi-Z Hi-Z D[15:0] VALID (read) DTACK Figure 6-9: Motorola DragonBall Interface with DTACK Timing...
Page 57: Table 6-12: Motorola Dragonball Interface With Dtack Timing
Epson Research and Development Page 51 Vancouver Design Center Table 6-12: Motorola DragonBall Interface with DTACK Timing MC68EZ328 MC68VZ328 Symbol Parameter 2.0V 3.3V 2.0V 3.3V Unit Bus Clock frequency CLKO Bus Clock period CLKO CLKO CLKO CLKO CLKO Clock pulse width high 28.1...
Page 58: Figure 6-10: Motorola Dragonball Interface Without Dtack# Timing
Page 52 Epson Research and Development Vancouver Design Center 6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328) CLKO CLKO A[16:1] UWE/LWE (write) (read) D[15:0] Hi-Z Hi-Z (write) Hi-Z D[15:0] Hi-Z VALID (read) Figure 6-10: Motorola DragonBall Interface without DTACK# Timing...
Page 59: Table 6-13: Motorola Dragonball Interface Without Dtack Timing
Epson Research and Development Page 53 Vancouver Design Center Table 6-13: Motorola DragonBall Interface without DTACK Timing MC68EZ328 MC68VZ328 Symbol Parameter 2.0V 3.3V 2.0V 3.3V Unit Bus Clock frequency CLKO Bus Clock period CLKO CLKO CLKO CLKO CLKO Clock pulse width high 28.1...
Page 60: Lcd Power Sequencing
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected. Note For HR-TFT Power-On/Off sequence information, see Connecting to the Sharp HR-TFT Panels, document number X31B-G-011-xx. For D-TFD Power-On/Off sequence information, see Connecting to the Epson D-TFD Panels, document number X31B-G-012-xx. S1D13706 Hardware Functional Specification X31B-A-001-08...
Page 61: Table 6-15: Passive/Tft Power-Off Sequence Timing
Epson Research and Development Page 55 Vancouver Design Center 6.3.2 Passive/TFT Power-Off Sequence GPO* Power Save Mode Enable** (REG[A0h] bit 0) LCD Signals*** *It is recommended to use the general purpose output pin GPO to control the LCD bias power.
Page 62: Figure 6-13: Panel Timing Parameters
Page 56 Epson Research and Development Vancouver Design Center 6.4 Display Interface The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section.
Page 63: Table 6-16: Panel Timing Parameter Definition And Register Summary
Epson Research and Development Page 57 Vancouver Design Center Table 6-16: Panel Timing Parameter Definition and Register Summary Symbol Description Derived From Units Horizontal Total ((REG[12h] bits 6-0) + 1) x 8 Horizontal Display Period ((REG[14h] bits 6-0) + 1) x 8...
Page 64: Figure 6-14: Generic Stn Panel Timing
Page 58 Epson Research and Development Vancouver Design Center 6.4.1 Generic STN Panel Timing VT (= 1 Frame) FPFRAME FPLINE (DRDY) FPDAT[17:0] HT (= 1 Line) FPLINE FPSHIFT 1PCLK (DRDY) HDPS FPDAT[17:0] Figure 6-14: Generic STN Panel Timing S1D13706 Hardware Functional Specification...
Page 65: Issue Date: 01/11/13 Page
Epson Research and Development Page 59 Vancouver Design Center = Vertical Total = [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines = FPFRAME Pulse Start Position = 0 lines, because (REG[27h] bits 1-0, REG[26h] bits 7-0) = 0 = FPFRAME Pulse Width...
Page 66: Figure 6-15: Single Monochrome 4-Bit Panel Timing
Page 60 Epson Research and Development Vancouver Design Center 6.4.2 Single Monochrome 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 Invalid FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 Invalid 1-317 Invalid...
Page 67: Table 6-17: Single Monochrome 4-Bit Panel A.c. Timing
Epson Research and Development Page 61 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing Symbol Parameter Units FPFRAME setup to FPLINE falling edge...
Page 68: Figure 6-17: Single Monochrome 8-Bit Panel Timing
Page 62 Epson Research and Development Vancouver Design Center 6.4.3 Single Monochrome 8-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 Invalid Invalid FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 Invalid 1-633 Invalid...
Page 69: Table 6-18: Single Monochrome 8-Bit Panel A.c. Timing
Epson Research and Development Page 63 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing Symbol Parameter Units FPFRAME setup to FPLINE falling edge...
Page 70: Figure 6-19: Single Color 4-Bit Panel Timing
Page 64 Epson Research and Development Vancouver Design Center 6.4.4 Single Color 4-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 Invalid Invalid FPLINE DRDY (MOD) HNDP .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts...
Page 71: Table 6-19: Single Color 4-Bit Panel A.c. Timing
Epson Research and Development Page 65 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 6-20: Single Color 4-Bit Panel A.C. Timing Table 6-19: Single Color 4-Bit Panel A.C. Timing Symbol Parameter Units FPFRAME setup to FPLINE falling edge...
Page 72: Figure 6-21: Single Color 8-Bit Panel Timing (Format 1)
Page 66 Epson Research and Development Vancouver Design Center 6.4.5 Single Color 8-Bit Panel Timing (Format 1) VNDP FPFRAME FPLINE FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2 Invalid FPLINE HNDP FPSHIFT FPSHIFT2 FPDAT7 Invalid Invalid 1-R1 1-G1...
Page 73: Table 6-20: Single Color 8-Bit Panel A.c. Timing (Format 1)
Epson Research and Development Page 67 Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 t12 t13 t12 t13 FPDAT[7:0] Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1) Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1)
Page 74: Single Color 8-Bit Panel Timing (Format 2)
Page 68 Epson Research and Development Vancouver Design Center 6.4.6 Single Color 8-Bit Panel Timing (Format 2) VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 Invalid FPLINE DRDY (MOD) HNDP FPSHIFT FPDAT7 Invalid...
Page 75: Table 6-21: Single Color 8-Bit Panel A.c. Timing (Format 2)
Epson Research and Development Page 69 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2) Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2)
Page 76: Figure 6-25: Single Color 16-Bit Panel Timing
Page 70 Epson Research and Development Vancouver Design Center 6.4.7 Single Color 16-Bit Panel Timing VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE DRDY (MOD) HNDP FPSHIFT Invalid 1-G6 1-B11 1-G635...
Page 77: Table 6-22: Single Color 16-Bit Panel A.c. Timing
Epson Research and Development Page 71 Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0] Figure 6-26: Single Color 16-Bit Panel A.C. Timing Table 6-22: Single Color 16-Bit Panel A.C. Timing Symbol Parameter Units FPFRAME setup to FPLINE falling edge...
Page 78: Figure 6-27: Generic Tft Panel Timing
Page 72 Epson Research and Development Vancouver Design Center 6.4.8 Generic TFT Panel Timing VT (= 1 Frame) FPFRAME VDPS FPLINE DRDY FPDAT[17:0] HT (= 1 Line) FPLINE FPSHIFT DRDY HDPS FPDAT[17:0] invalid invalid Figure 6-27: Generic TFT Panel Timing...
Page 79: Figure 6-28: 18-Bit Tft Panel Timing
Epson Research and Development Page 73 Vancouver Design Center 6.4.9 9/12/18-Bit TFT Panel Timing VNDP VNDP FPFRAME FPLINE FPDAT[17:0] LINE240 LINE1 LINE480 DRDY FPLINE HNDP HNDP FPSHIFT DRDY FPDAT[17:0] 1-320 invalid invalid Note: DRDY is used to indicate the first pixel...
Page 80: Figure 6-29: Tft A.c. Timing
Page 74 Epson Research and Development Vancouver Design Center FPFRAME FPLINE FPLINE DRDY t10 t11 FPSHIFT t15 t16 invalid invalid FPDAT[17:0] Note: DRDY is used to indicate the first pixel Figure 6-29: TFT A.C. Timing S1D13706 Hardware Functional Specification X31B-A-001-08...
Page 81: Table 6-23: Tft A.c. Timing
Epson Research and Development Page 75 Vancouver Design Center Table 6-23: TFT A.C. Timing Symbol Parameter Units FPFRAME cycle time Lines FPFRAME pulse width low Lines FPFRAME falling edge to FPLINE falling edge phase difference Ts (note 1) FPLINE cycle time...
Page 82: Figure 6-30: 160X160 Sharp 'Direct' Hr-Tft Panel Horizontal Timing
Page 76 Epson Research and Development Vancouver Design Center 6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) t5 t6 D160 FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) GPIO0 (PS) GPIO2 (REV) Figure 6-30: 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing...
Page 83: Table 6-24: 160X160 Sharp 'Direct' Hr-Tft Horizontal Timing
Epson Research and Development Page 77 Vancouver Design Center Table 6-24: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing Symbol Parameter Units FPLINE start position Ts (note 1) Horizontal total period FPLINE width FPSHIFT period Data setup to FPSHIFT rising edge Data hold from FPSHIFT rising edge...
Page 84: Figure 6-31: 160X160 Sharp 'Direct' Hr-Tft Panel Vertical Timing
Page 78 Epson Research and Development Vancouver Design Center FPDAT[17:0] LINE1 LINE2 LINE160 FPFRAME (SPS) GPIO1 (CLS) GPIO0 (PS) FPLINE (LP) FPSHIFT (CLK) GPIO1 (CLS) GPIO0 (PS) Figure 6-31: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing S1D13706 Hardware Functional Specification...
Page 85: Table 6-25: 160X160 Sharp 'Direct' Hr-Tft Panel Vertical Timing
Epson Research and Development Page 79 Vancouver Design Center Table 6-25: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing Symbol Parameter Units Vertical total period Lines Vertical display start position Lines Vertical display period Lines Vertical sync pulse width Lines FPFRAME falling edge to GPIO1 alternate timing start...
Page 86: Figure 6-32: 320X240 Sharp 'Direct' Hr-Tft Panel Horizontal Timing
Page 80 Epson Research and Development Vancouver Design Center 6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) D320 FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) GPIO0 (PS) GPIO2 (REV) Figure 6-32: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing...
Page 87: Table 6-26: 320X240 Sharp 'Direct' Hr-Tft Panel Horizontal Timing
Epson Research and Development Page 81 Vancouver Design Center Table 6-26: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing Symbol Parameter Units FPLINE start position Ts (note 1) Horizontal total period FPLINE width FPSHIFT period Data setup to FPSHIFT rising edge...
Page 88: Figure 6-34: 160X240 Epson D-Tfd Panel Horizontal Timing
Page 82 Epson Research and Development Vancouver Design Center 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) FPLINE (LP) FPSHIFT (XSCL) FPDAT[17:0] (R,G,B) GPIO4 (RES) GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 (DD_P1) Figure 6-34: 160x240 Epson D-TFD Panel Horizontal Timing...
Page 89: Table 6-28: 160X240 Epson D-Tfd Panel Horizontal Timing
Epson Research and Development Page 83 Vancouver Design Center Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing Symbol Parameter Units FPLINE pulse width Ts (note 1) FPLINE falling edge to FPSHIFT start position FPSHIFT active period FPSHIFT start to first data...
Page 90: Table 6-29: 160X240 Epson D-Tfd Panel Gcp Horizontal Timing
Index 00h Index 01h Index 00h Figure 6-35: 160x240 Epson D-TFD Panel GCP Horizontal Timing Table 6-29: 160x240 Epson D-TFD Panel GCP Horizontal Timing Symbol Parameter Units Half of the horizontal total period Ts (note 1) GCP clock period 1.
Page 91: Table 6-30: 160X240 Epson D-Tfd Panel Vertical Timing
FPDAT[17:0] line2 line1 (R,G,B) GPIO2 (FR) (odd frame) GPIO2 (FR) (even frame) Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing Symbol Parameter Units FPFRAME pulse width Ts (note 1) Horizontal total period Vertical display start 1.
Page 92: Figure 6-37: 320X240 Epson D-Tfd Panel Horizontal Timing
Page 86 Epson Research and Development Vancouver Design Center 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) FPLINE (LP) FPSHIFT (XSCL) FPDAT[17:0] (R,G,B) GPIO4 (RES) GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 (DD_P1) Figure 6-37: 320x240 Epson D-TFD Panel Horizontal Timing...
Page 93: Table 6-31: 320X240 Epson D-Tfd Panel Horizontal Timing
Epson Research and Development Page 87 Vancouver Design Center Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing Symbol Parameter Units FPLINE pulse width Ts (note 1) FPLINE falling edge to FPSHIFT start position FPSHIFT active period FPSHIFT start to first data...
Page 94: Table 6-32: 320X240 Epson D-Tfd Panel Gcp Horizontal Timing
Index 00h Index 00h Index 01h Figure 6-38: 320x240 Epson D-TFD Panel GCP Horizontal Timing Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing Symbol Parameter Units Half of the horizontal total period Ts (note 1) GCP clock period 1.
Page 95: Table 6-33: 320X240 Epson D-Tfd Panel Vertical Timing
FPDAT[17:0] line2 line1 (R,G,B) GPIO2 (FR) (odd frame) GPIO2 (FR) (even frame) Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing Symbol Parameter Units FPFRAME pulse width Ts (note 1) Horizontal total period Vertical display start 1.
Page 96: Table 7-1: Bclk Clock Selection
7.1.2 MCLK MCLK provides the internal clock required to access the embedded SRAM. The S1D13706 is designed with efficient power saving control for clocks (clocks are turned off when not used); reducing the frequency of MCLK does not necessarily save more power.
Page 97: Table 7-3: Pclk Clock Selection
Epson Research and Development Page 91 Vancouver Design Center 7.1.3 PCLK PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match the optimum frame rate of the LCD panel. See Section 9, “Frame Rate Calculation” on page 130 for details on the relationship between PCLK and frame rate.
Page 98: Table 7-4: Relationship Between Mclk And Pclk
Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers” on page 126. Note The S1D13706 provides Pulse Width Modulation output on the pin PWMOUT. PWMOUT can be used to control LCD panels which support PWM control of the back- light inverter.
Page 99: Figure 7-1: Clock Selection
Epson Research and Development Page 93 Vancouver Design Center 7.2 Clock Selection The following diagram provides a logical representation of the S1D13706 internal clocks. CLKI ÷2 BCLK ÷3 ÷4 CNF[7:6] REG[04h] bits 5,4 ÷2 MCLK ÷3 ÷4 ÷2 CLKI2 ÷3 PCLK ÷4...
Page 100: Table 7-6: S1D13706 Internal Clock Requirements
Page 94 Epson Research and Development Vancouver Design Center 7.3 Clocks versus Functions Table 7-6: “S1D13706 Internal Clock Requirements”, lists the internal clocks required for the following S1D13706 functions. Table 7-6: S1D13706 Internal Clock Requirements Bus Clock Memory Clock Pixel Clock...
Page 101: Registers
Page 95 Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13706 registers. It also provides detailed information about the layout and usage of each register. 8.1 Register Mapping The S1D13706 registers are memory-mapped. When the system decodes the input pins as CS# = 0 and M/R# = 0, the registers may be accessed.
Page 102: Register Descriptions
REG[00h] Read Only Product Code Bits 5-0 Revision Code Bits 1-0 Note The S1D13706 returns a value of 28h. bits 7-2 Product Code These are read-only bits that indicates the product code. The product code is 001010. bits 1-0 Revision Code These are read-only bits that indicates the revision code.
Page 103: Table 8-2: Mclk Divide Selection
Display Buffer Size Bits [7:0] This is a read-only register that indicates the size of the SRAM display buffer measured in 4K byte increments. The S1D13706 display buffer is 80K bytes and therefore this register returns a value of 20 (14h).
Page 104: Table 8-3: Pclk Divide Selection
Page 98 Epson Research and Development Vancouver Design Center Pixel Clock Configuration Register REG[05h] Read/Write PCLK Divide Select Bits 2-0 PCLK Source Select Bits 1-0 bits 6-4 PCLK Divide Select Bits [1:0] These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel Clock Source.
Page 105: Look-Up Table Registers
Vancouver Design Center 8.3.3 Look-Up Table Registers Note The S1D13706 has three 256-position, 6-bit wide LUTs, one for each of red, green, and blue (see Section 11, “Look-Up Table Architecture” on page 132). Look-Up Table Blue Write Data Register REG[08h]...
Page 106 Page 100 Epson Research and Development Vancouver Design Center Look-Up Table Write Address Register REG[0Bh] Write Only LUT Write Address Bits 7-0 bits 7-0 LUT Write Address Bits [7:0] This register forms a pointer into the Look-Up Table (LUT) which is used to write LUT blue, green, and red data stored in REG[08h], REG[09h], and REG[0Ah].
Page 107: Panel Configuration Registers
Epson Research and Development Page 101 Vancouver Design Center Look-Up Table Red Read Data Register REG[0Eh] Read Only LUT Red Read Data Bits 5-0 bits 7-2 LUT Red Read Data Bits [5:0] This register contains the data from the red component of the Look-Up Table. The LUT position is controlled by the LUT Read Address Register (REG[0Fh]).
Page 108: Table 8-5: Panel Data Width Selection
Page 102 Epson Research and Development Vancouver Design Center bits 5-4 Panel Data Width Bits [1:0] These bits select the data width size of the LCD panel. Table 8-5: Panel Data Width Selection Passive Panel Data Width Panel Data Width Bits [1:0]...
Page 109 Epson Research and Development Page 103 Vancouver Design Center MOD Rate Register REG[11h] Read/Write MOD Rate Bits 5-0 bits 5-0 MOD Rate Bits [5:0] These bits are for passive LCD panels only. When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME.
Page 110 Page 104 Epson Research and Development Vancouver Design Center Horizontal Display Period Start Position Register 0 REG[16h] Read/Write Horizontal Display Period Start Position Bits 7-0 Horizontal Display Period Start Position Register 1 REG[17h] Read/Write Horizontal Display Period Start Position Bits 9-8...
Page 111 Epson Research and Development Page 105 Vancouver Design Center Vertical Total Register 0 REG[18h] Read/Write Vertical Total Bits 7-0 Vertical Total Register 1 REG[19h] Read/Write Vertical Total Bits 9-8 bits 9-0 Vertical Total Bits [9:0] These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical Total is the sum of the Vertical Display Period and the Vertical Non-Display Period.
Page 112 Page 106 Epson Research and Development Vancouver Design Center Vertical Display Period Start Position Register 0 REG[1Eh] Read/Write Vertical Display Period Start Position Bits 7-0 Vertical Display Period Start Position Register 1 REG[1Fh] Read/Write Vertical Display Period Start Position Bits 9-8...
Page 113 Epson Research and Development Page 107 Vancouver Design Center FPLINE Pulse Start Position Register 0 REG[22h] Read/Write FPLINE Pulse Start Position Bits 7-0 FPLINE Pulse Start Position Register 1 REG[23h] Read/Write FPLINE Pulse Start Position Bits 9-8 bits 9-0 FPLINE Pulse Start Position Bits [9:0] These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
Page 114 For D-TFD panel only. This register stores the data to be written to the GCP data bits and is controlled by the D-TFD GCP Index register (REG[28h]). For further information on the use of this register, see Connecting to the Epson D-TFD Panels, document number X31B-G-012-xx.
Page 115: Display Mode Registers
Epson Research and Development Page 109 Vancouver Design Center 8.3.5 Display Mode Registers Display Mode Register REG[70h] Read/Write Hardware Dithering Software Display Blank Video Invert Bit-per-pixel Select Bits 2-0 Disable Video Invert Enable bit 7 Display Blank When this bit = 0, the LCD display pipeline is enabled.
Page 116: Table 8-8: Inverse Video Mode Select Options
When this bit = 0, GPIO0 has no effect on the video data. When this bit = 1, video data may be inverted via GPIO0. Note The S1D13706 requires some configuration before the hardware video invert feature can be enabled. • CNF3 must be set to 1 at RESET# •...
Page 117: Table 8-9: Lcd Bit-Per-Pixel Selection
Epson Research and Development Page 111 Vancouver Design Center bits 2-0 Bit-per-pixel Select Bits [2:0] These bits select the color depth (bit-per-pixel) for the displayed data for both the main window and the PIP window (if active). Note 1, 2, 4 and 8 bpp color depths use the 18-bit LUT, allowing a maximum number of 256K available colors on TFT panels.
Page 118: Table 8-10: Swivelview Tm Mode Select Options
Page 112 Epson Research and Development Vancouver Design Center bit 6 Display Data Byte Swap The display pipe fetches 32-bits of data from the display buffer. This bit enables byte 0 and byte 1 to be swapped, and byte 2 and byte 3 to be swapped, before sending them to the LCD display.
Page 119 Epson Research and Development Page 113 Vancouver Design Center Main Window Display Start Address Register 0 REG[74h] Read/Write Main window Display Start Address Bits 7-0 Main Window Display Start Address Register 1 REG[75h] Read/Write Main window Display Start Address Bits 15-8...
Page 120 Page 114 Epson Research and Development Vancouver Design Center Main Window Line Address Offset Register 0 REG[78h] Read/Write Main window Line Address Offset Bits 7-0 Main Window Line Address Offset Register 1 REG[79h] Read/Write Main window Line Address Offset Bits 9-8...
Page 121 Epson Research and Development Page 115 Vancouver Design Center 8.3.6 Picture-in-Picture Plus (PIP ) Registers Window Display Start Address Register 0 REG[7C] Read/Write Window Display Start Address Bits 7-0 Window Display Start Address Register 1 REG[7Dh] Read/Write Window Display Start Address Bits 15-8...
Page 122: Table 8-11: 32-Bit Address Increments For Color Depth
These bits determine the X start position of the PIP window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the X start position may not be a horizontal position value (only true in 0° and 180° SwivelView). For further information on defining the value of the X Start Position register, see Section 13, “Picture-in-Picture...
Page 123: Table 8-12: 32-Bit Address Increments For Color Depth
These bits determine the Y start position of the PIP window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the Y start position may not be a vertical position value (only true in 0° and 180° SwivelView). For further information on defining the value of the Y Start Position register, see Section 13, “Picture-in-Picture Plus (PIP+)”...
Page 124: Table 8-13: 32-Bit Address Increments For Color Depth
These bits determine the X end position of the PIP window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the X end position may not be a horizontal position value (only true in 0° and 180° SwivelView). For further information on defining the value of the X End Position register, see Section 13, “Picture-in-Picture...
Page 125: Table 8-14: 32-Bit Address Increments For Color Depth
These bits determine the Y end position of the PIP window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the Y end position may not be a vertical position value (only true in 0° and 180° SwivelView). For further information on defining the value of the Y End Position register, see Section 13, “Picture-in-Picture Plus (PIP+)”...
Page 126: Miscellaneous Registers
When this bit = 1, the memory controller is powered down and the MCLK source can be turned off. Note Memory writes are possible during power save mode because the S1D13706 dynamical- ly enables the memory controller for display buffer writes. bit 0 Power Save Mode Enable When this bit = 1, the software initiated power save mode is enabled.
Page 127 Epson Research and Development Page 121 Vancouver Design Center Reserved REG[A2h] Read/Write Reserved Reserved bit 7 Reserved. This bit must remain at 0. bit 0 Reserved. This bit must remain at 0. Reserved REG[A3h] Read/Write Reserved bit 7 Reserved. This bit must remain at 0.
Page 128: General Io Pins Registers
Page 122 Epson Research and Development Vancouver Design Center 8.3.8 General IO Pins Registers General Purpose IO Pins Configuration Register 0 REG[A8h] Read/Write GPIO6 Pin IO GPIO5 Pin IO GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO...
Page 129 Epson Research and Development Page 123 Vancouver Design Center General Purpose IO Pins Status/Control Register 0 REG[ACh] Read/Write GPIO6 Pin IO GPIO5 Pin IO GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIO0 Pin IO Status...
Page 130 Page 124 Epson Research and Development Vancouver Design Center bit 3 GPIO3 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit drives GPIO3 low.
Page 131 Epson Research and Development Page 125 Vancouver Design Center bit 0 GPIO0 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is configured as an output, writing a 1 to this bit drives GPIO0 high and writing a 0 to this bit drives GPIO0 low.
Page 132: Table 8-15: Pwm Clock Control
Page 126 Epson Research and Development Vancouver Design Center 8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers PWM Clock Enable Divided PWM Duty Cycle PWM Clock Clock Modulation Divider to PWMOUT PWMCLK Duty = n / 256...
Page 133: Table 8-16: Cv Pulse Control
Epson Research and Development Page 127 Vancouver Design Center bit 3 and bit 0 CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0) These bits control the CVOUT pin and CV Pulse circuitry as follows. Table 8-16: CV Pulse Control...
Page 134: Table 8-17: Pwm Clock Divide Select Options
Page 128 Epson Research and Development Vancouver Design Center PWM Clock / CV Pulse Configuration Register REG[B1h] Read/Write PWMCLK PWM Clock Divide Select Bits 3-0 CV Pulse Divide Select Bits 2-0 Source Select bits 7-4 PWM Clock Divide Select Bits [3:0] The value of these bits represents the power of 2 by which the selected PWM clock source is divided.
Page 135: Table 8-19: Pwmout Duty Cycle Select Options
Epson Research and Development Page 129 Vancouver Design Center CV Pulse Burst Length Register REG[B2h] Read/Write CV Pulse Burst Length Bits 7-0 bits 7-0 CV Pulse Burst Length Bits [7:0] The value of this register determines the number of pulses generated in a single CV Pulse...
Page 136: Frame Rate Calculation
Page 130 Epson Research and Development Vancouver Design Center 9 Frame Rate Calculation The following formula is used to calculate the display frame rate. PCLK FrameRate ------------------------------- - × Where: = PClk frequency (Hz) PCLK = Horizontal Total = ((REG[12h] bits 6-0) + 1) x 8 Pixels...
Page 137: Figure 10-1: 4/8/16 Bit-Per-Pixel Display Data Memory Organization
Epson Research and Development Page 131 Vancouver Design Center 10 Display Data Formats The following diagrams show the display mode data formats for a little-endian system. 1 bpp: bit 7 bit 0 Byte 0 Byte 1 = RGB value from LUT...
Page 138: Figure 11-1: 1 Bit-Per-Pixel Monochrome Mode Data Output Path
Page 132 Epson Research and Development Vancouver Design Center 11 Look-Up Table Architecture The following figures are intended to show the display data output path only. Note When Video Data Invert is enabled the video data is inverted after the Look-Up Table.
Page 139: Figure 11-3: 4 Bit-Per-Pixel Monochrome Mode Data Output Path
Epson Research and Development Page 133 Vancouver Design Center 4 Bit-per-pixel Monochrome Mode Green Look-Up Table 256x6 0000 0001 0010 0011 0100 0101 0110 6-bit Gray Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 bit-per-pixel data from Display Buffer...
Page 140: Figure 11-5: 1 Bit-Per-Pixel Color Mode Data Output Path
Page 134 Epson Research and Development Vancouver Design Center 16 Bit-Per-Pixel Monochrome Mode The LUT is bypassed and the green data is directly mapped for this color depth– See “Display Data Formats” on page 131.. 11.2 Color Modes 1 Bit-Per-Pixel Color...
Page 141: Figure 11-6: 2 Bit-Per-Pixel Color Mode Data Output Path
Epson Research and Development Page 135 Vancouver Design Center 2 Bit-Per-Pixel Color Red Look-Up Table 256x6 6-bit Red Data Green Look-Up Table 256x6 6-bit Green Data Blue Look-Up Table 256x6 6-bit Blue Data 2 bit-per-pixel data from Image Buffer = unused Look-Up Table entries...
Page 142: Figure 11-7: 4 Bit-Per-Pixel Color Mode Data Output Path
Page 136 Epson Research and Development Vancouver Design Center 4 Bit-Per-Pixel Color Red Look-Up Table 256x6 0000 0001 0010 0011 0100 0101 0110 6-bit Red Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 Green Look-Up Table 256x6 0000...
Page 143: Figure 11-8: 8 Bit-Per-Pixel Color Mode Data Output Path
Epson Research and Development Page 137 Vancouver Design Center 8 Bit-per-pixel Color Mode Red Look-Up Table 256x6 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 6-bit Red Data 1111 1000 1111 1001...
Page 144: Figure 12-1: Relationship Between The Screen Image And The Image Refreshed In 90° Swivelview
The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13706 in the following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following sense: B-D-A-C.
Page 145: Register Programming
Epson Research and Development Page 139 Vancouver Design Center 12.2.1 Register Programming Enable 90° SwivelView™ Mode Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 01. Display Start Address The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “B”.
Page 146: Register Programming
The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13706 in the following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following sense: D-C-B-A.
Page 147 The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13706 in the following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following sense: C-A-D-B.
Page 148: Register Programming
Page 142 Epson Research and Development Vancouver Design Center 12.4.1 Register Programming Enable 270° SwivelView™ Mode Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 11. The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “C”.
Page 149: Figure 13-1: Picture-In-Picture Plus With Swivelview Disabled
Epson Research and Development Page 143 Vancouver Design Center 13 Picture-in-Picture Plus (PIP 13.1 Concept Picture-in-Picture Plus enables a secondary window (or PIP window) within the main display window. The PIP window may be positioned anywhere within the virtual display...
Page 150: Figure 13-2: Picture-In-Picture Plus With Swivelview 90° Enabled
Page 144 Epson Research and Development Vancouver Design Center 13.2 With SwivelView Enabled 13.2.1 SwivelView 90° 90° SwivelView panel’s origin window x start position window x end position (REG[85h],REG[84h]) (REG[8Dh],REG[8Ch]) window window y start position (REG[89h],REG[88h]) window y end position...
Page 151: Figure 13-4: Picture-In-Picture Plus With Swivelview 270° Enabled
Epson Research and Development Page 145 Vancouver Design Center 13.2.3 SwivelView 270° 270° SwivelView main-window window y end position (REG[91h],REG[90h]) window y start position window (REG[89h],REG[88h]) window x start position window x end position (REG[85h],REG[84h]) (REG[8Dh],REG[8Ch]) panel’s origin Figure 13-4: Picture-in-Picture Plus with SwivelView 270° enabled...
Page 152: Big-Endian Bus Interface 14.1 Byte Swapping Bus Data
Bus data byte swapping translates all byte accesses correctly to the S1D13706 register and display buffer locations. To maintain the correct translation for 16-bit word access, even address bytes must be mapped to the MSB of the 16-bit word, and odd address bytes to the LSB of the 16-bit word.
Page 153: Figure 14-1: Byte-Swapping For 16 Bpp
LSB of the 16-bit pixel data is stored at the odd system memory address location. Bus data byte swapping (automatic when the S1D13706 is configured for Big-Endian) causes the 16-bit pixel data to be stored byte-swapped in the S1D13706 display buffer.
Page 154: Figure 14-2: Byte-Swapping For 1/2/4/8 Bpp
Page 148 Epson Research and Development Vancouver Design Center 14.1.2 1/2/4/8 Bpp Color Depth For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the display data. For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 0.
Page 155: Table 15-1: Power Save Mode Function Summary
GPIOs can be accessed and if configured as outputs can be changed. After reset, the S1D13706 is always in Power Save Mode. Software must initialize the chip (i.e. programs all registers) and then clear the Power Save Mode Enable bit.
Page 156: Figure 16-1: Mechanical Data 100Pin Tqfp15 (S1D13706F00A)
Page 150 Epson Research and Development Vancouver Design Center 16 Mechanical Data 100-pin TQFP15 surface mount package ± 0.4 16.0 ± 0.1 14.0 Index + 0.1 0.18 - 0.05 0~10° ± 0.2 All dimensions in mm Figure 16-1: Mechanical Data 100pin TQFP15 (S1D13706F00A)
Page 157: Figure 16-2: Mechanical Data 104Pin Cflga (S1D13706B00A)
Epson Research and Development Page 151 Vancouver Design Center 104-pin CFLGA package ± 0.15 8.00 1.00max ± 0.10 6.55 (0.725) 0.05max TOP VIEW SIDE VIEW ± 0.2 6.50 0.75 ± 0.10 0.40 0.15 0.65 10 11 4-( 1.05) 0.325 BOTTOM VIEW...
Page 158: References
Epson Research and Development Vancouver Design Center 17 References The following documents contain additional information related to the S1D13706. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com.
Page 159: Sales And Technical Support
Epson Research and Development Page 153 Vancouver Design Center 18 Sales and Technical Support Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd. 421-8, Hino, Hino-shi San Jose, CA 95134, USA 10F, No.
Page 160 Page 154 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Hardware Functional Specification X31B-A-001-08 Issue Date: 01/11/13...
Page 161 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 162 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Programming Notes and Examples X31B-G-003-03 Issue Date: 01/02/23...
Page 163 Epson Research and Development Page 3 Vancouver Design Center Table of Contents Introduction ........9 Initialization .
Page 164 Page 4 Epson Research and Development Vancouver Design Center 8.3.1 SwivelView 0° (Landscape Mode) ......48 8.3.2...
Page 165 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2-1: Example Register Values ....... . . 11 Table 4-1: Look-Up Table Configurations .
Page 166 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Programming Notes and Examples X31B-G-003-03 Issue Date: 01/02/23...
Page 167 Epson Research and Development Page 7 Vancouver Design Center List of Figures Figure 3-1: Pixel Storage for 1 Bpp in One Byte of Display Buffer ....14 Figure 3-2: Pixel Storage for 2 Bpp in One Byte of Display Buffer .
Page 168 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Programming Notes and Examples X31B-G-003-03 Issue Date: 01/02/23...
Page 169: Introduction
This guide discusses Power-on Initialization, Panning and Scrolling, LUT initialization, LCD Power Sequencing, SwivelView™, Picture-In-Picture Plus, etc. The example source code referenced in this guide is available on the web at www.eea.epson.com or www.erd.epson.com. This guide also introduces the Hardware Abstraction Layer (HAL), which is designed to simplify the programming of the S1D13706.
Page 170: Initialization
2 Initialization This section describes how to initialize the S1D13706. Sample code for performing initial- ization of the S1D13706 is provided in the file init13706.c which is available on the internet at www.eea.epson.com or www.erd.epson.com. S1D13706 initialization can be broken into the following steps.
Page 171 Epson Research and Development Page 11 Vancouver Design Center The following table represents the sequence and values written to the S1D13706 registers to control a configuration with these specifications. • 320x240 color single passive LCD @ 70Hz. • 8-bit data interface, format 2.
Page 172 Page 12 Epson Research and Development Vancouver Design Center Table 2-1: Example Register Values (Continued) Value Value Register Description Notes (Hex) (Binary) Display Mode Setting Configuration Selects the following: • display blank = screen is blanked • dithering = enabled 1000 0011 •...
Page 173 Epson Research and Development Page 13 Vancouver Design Center Table 2-1: Example Register Values (Continued) Value Value Register Description Notes (Hex) (Binary) 0000 0000 GPIO[6:0] pins are driven low Bit 7 controls the LCD bias 0000 0000 Set the GPO control bit to low power for the panel on the S5U13706B00C.
Page 174: Memory Models
Vancouver Design Center 3 Memory Models The S1D13706 contains a display buffer of 80K bytes and supports color depths of 1, 2, 4, 8, and 16 bit-per-pixel. For each color depth, the data format is packed pixel. Packed pixel data may be envisioned as a stream of pixels. In this stream, pixels are packed adjacent to each other.
Page 175: Memory Organization For Two Bit-Per-Pixel (4 Colors/Gray Shades)
Epson Research and Development Page 15 Vancouver Design Center 3.3 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2...
Page 176: Memory Organization For 8 Bpp (256 Colors/64 Gray Shades)
Figure 3-5: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer At a color depth of 16 bpp the S1D13706 is capable of displaying 64K (65536) colors. The 64K color pixel is divided into three parts: five bits for red, six bits for green, and five bits for blue.
Page 177: Look-Up Table (Lut)
For a discussion of the LUT architecture, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx. The S1D13706 is designed with a LUT consisting of 256 indexed red/green/blue entries. Each LUT entry is six bits wide. The color depth (bpp) determines how many indices are used to output the image to the display.
Page 178: Look-Up Table Read Registers
This is a write-only register and returns 00h if read. Note For further information on the S1D13706 LUT architecture, see the S1D13706 Hard- ware Functional Specification, document number X31B-A-001-xx. 4.1.2 Look-Up Table Read Registers...
Page 179: Look-Up Table Organization
This intensity can range in value between 0 and 0Fh. • The S1D13706 Look-Up Table is linear. This means increasing the LUT entry number results in a lighter color or gray shade. For example, a LUT entry of 0Fh in the red bank results in bright red output while a LUT entry of 05h results in dull red.
Page 180: Gray Shade Modes
Page 20 Epson Research and Development Vancouver Design Center 4.2.1 Gray Shade Modes Gray shade (monochrome) modes are defined by the Color/Mono Panel Select bit (REG[10h] bit 6). When this bit is set to 0, the value output to the panel is derived solely from the green component of the LUT.
Page 181 Epson Research and Development Page 21 Vancouver Design Center 4 bpp gray shade The 4 bpp gray shade mode uses the green component of the first 16 LUT entries. The remaining indices of the LUT are unused. Table 4-4: Suggested LUT Values for 4 Bpp Gray Shade...
Page 182: Color Modes
1 bpp color When the S1D13706 is configured for 1 bpp color mode the first 2 entries in the LUT are used. Each byte in the display buffer contains eight adjacent pixels. Table 4-5: Suggested LUT Values for 1 bpp Color...
Page 183 Vancouver Design Center 4 bpp color When the S1D13706 is configured for 4 bpp color mode the first 16 entries in the LUT are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT.
Page 184 Vancouver Design Center 8 bpp color When the S1D13706 is configured for 8 bpp color mode all 256 entries in the LUT are used. Each byte in the display buffer corresponds to one pixel and is used as an index value into the LUT.
Page 185 Epson Research and Development Page 25 Vancouver Design Center Table 4-8: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued) Index Index Index Index 16 bpp color The Look-Up Table is bypassed at this color depth, therefore programming the LUT is not required.
Page 186: Power Save Mode
Vancouver Design Center 5 Power Save Mode The S1D13706 is designed for very low-power applications. During normal operation, the internal clocks are dynamically disabled when not required. The S1D13706 design also includes a Power Save Mode to further save power. When Power Save Mode is initiated, LCD power sequencing is required to ensure the LCD bias power supply is disabled properly.
Page 187: Registers
The Memory Controller Power Save Status bit is a read-only status bit which indicates the power save state of the S1D13706 SRAM interface. When this bit returns a 1, the SRAM interface is powered down. When this bit returns a 0, the SRAM interface is active. This bit returns a 0 after a chip reset.
Page 188: Enabling Power Save Mode
Page 28 Epson Research and Development Vancouver Design Center 5.3 Enabling Power Save Mode Power Save Mode must be enabled using the following steps. 1. Disable the LCD bias power using GPO. Note The S5U13706B00C uses GPO to control the LCD bias power supplies. Your system design may vary.
Page 189: Lcd Power Sequencing
Evaluation board requires 0.5 seconds to fully discharge. Other power supply designs may vary. This section assumes the LCD bias power is controlled through GPO. The S1D13706 GPIO pins are multi-use pins and may not be available in all system designs. For further infor- mation on the availability of GPIO pins, see the S1D13706 Hardware Functional Specifi- cation, document number X31B-A-001-xx.
Page 190: Enabling The Lcd Panel
Page 30 Epson Research and Development Vancouver Design Center 6.1 Enabling the LCD Panel The HAL function seDisplayEnable(TRUE) can be used to enable the LCD panel. The function enables the LCD panel using the following steps. 1. Enable the LCD signals - Set Display Blank bit (REG[70h] bit 7) to 0.
Page 191: Swivelview
SwivelView 0° is selected, the panel will be in a “portrait” orientation. A selection of SwivelView 90° or SwivelView 270° rotates to a landscape orientation. The S1D13706 provides hardware support for SwivelView in all color depths (1, 2, 4, 8 and 16 bpp).
Page 192: Registers
Page 32 Epson Research and Development Vancouver Design Center 7.1 Registers These are the registers which control the SwivelView feature. REG[71h] Special Effects Register SwivelView SwivelView Display Data Display Data Sub-Window Mode Select Mode Select Word Swap Byte Swap Enable...
Page 193: Examples
Epson Research and Development Page 33 Vancouver Design Center In SwivelView 180°, program the start address = ((desired byte address + (panel width × panel height × bpp ÷ 8)) ÷ 4) - 1. In SwivelView 270°, program the start address = (desired byte address + ((panel width - 1) ×...
Page 194 Page 34 Epson Research and Development Vancouver Design Center 2. Determine the main window display start address. The main window is typically placed at the start of display memory which is at display address 0. main window display start address register = desired byte address ÷ 4 Program the Main Window Display Start Address registers.
Page 195 Epson Research and Development Page 35 Vancouver Design Center Program the Main Window Line Address Offset register. REG[78h] is set to 1Eh, and REG[79h] is set to 00h. ° Example 3: In SwivelView 180 mode, program the main window registers for a 320x240 panel at a color depth of 4 bpp.
Page 196: Limitations
Page 36 Epson Research and Development Vancouver Design Center 2. Determine the main window display start address. The main window is typically placed at the start of display memory, which is at dis- play address 0. main window display start address register = (desired byte address + ((panel width - 1) ×...
Page 197: Picture-In-Picture Plus
Epson Research and Development Page 37 Vancouver Design Center 8 Picture-In-Picture Plus 8.1 Concept Picture-in-Picture Plus enables a sub-window within the main display window. The sub- window may be positioned anywhere within the main window and is controlled through the Sub-Window control registers (see Section 8.2, “Registers”...
Page 198 Page 38 Epson Research and Development Vancouver Design Center REG[74h] Main Window Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[75h] Main Window Display Start Address Register 1...
Page 199 Epson Research and Development Page 39 Vancouver Design Center REG[78h] Main Window Line Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[79h] Main Window Line Address Offset Register 1...
Page 200 Page 40 Epson Research and Development Vancouver Design Center In SwivelView 180°, program the start address = ((desired byte address + (sub-window width × sub-window height × bpp ÷ 8)) ÷ 4) - 1 In SwivelView 270°, program the start address = (desired byte address + ((sub-window height - 1) ×...
Page 201 These bits determine the X start position of the sub-window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the X start position may not be a horizontal position value (only true in 0° and 180° SwivelView). For further information on defining the value of the X Start Position registers, see Section 8.3, “Picture-In-Picture-...
Page 202 These bits determine the Y start position of the sub-window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the Y start position may not be a vertical position value (only true in 0° and 180° SwivelView). For further information on defining the value of the Y Start Position registers, see Section 8.3, “Picture-In-Picture-Plus...
Page 203 Epson Research and Development Page 43 Vancouver Design Center In SwivelView 0°, these registers set the vertical coordinates (y) of the sub-windows’s top left corner. Increasing values of y move the top left corner downwards in steps of 1 line.
Page 204 These bits determine the X end position of the sub-window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the X end position may not be a horizontal position value (only true in 0° and 180° SwivelView). For further information on defining the value of the X End Position register, see Section 8.3, “Picture-In-Picture-...
Page 205 Epson Research and Development Page 45 Vancouver Design Center In SwivelView 180°, these registers set the horizontal coordinates (x) of the sub-window’s top left corner. Increasing values of x move the top left corner towards the right in steps of 32 ÷...
Page 206 These bits determine the Y end position of the sub-window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the Y end position may not be a vertical position value (only true in 0° and 180° SwivelView). For further information on defining the value of the Y End Position register, see Section 8.3, “Picture-In-Picture-Plus...
Page 207 Epson Research and Development Page 47 Vancouver Design Center Program the Sub-Window Y End Position registers so that sub-window Y end position registers = panel height - y - 1 In SwivelView 270°, these registers set the horizontal coordinates (x) of the sub-window’s top right corner.
Page 208: Picture-In-Picture-Plus Examples
Page 48 Epson Research and Development Vancouver Design Center 8.3 Picture-In-Picture-Plus Examples 8.3.1 SwivelView 0° (Landscape Mode) 0° SwivelView sub-window y start position (REG[89h],REG[88h]) panel’s origin sub-window y end position (REG[91h],REG[90h]) main-window sub-window sub-window x start position sub-window x end position...
Page 209 Epson Research and Development Page 49 Vancouver Design Center 160 ÷ (32 ÷ 4) = 20 Sub-window horizontal coordinates and horizontal width are valid. 3. Determine the main window display start address. The main window is typically placed at the start of display memory which is at display address 0.
Page 210 Page 50 Epson Research and Development Vancouver Design Center 7. Determine the value for the sub-window X and Y start and end position registers. Let the top left corner of the sub-window be (x1, y1), and let x2 = x1 + width, y2 = y1 + height.
Page 211: Swivelview 90
Epson Research and Development Page 51 Vancouver Design Center 8.3.2 SwivelView 90° 90° SwivelView panel’s origin sub-window x start position sub-window x end position (REG[85h],REG[84h]) (REG[8Dh],REG[8Ch]) sub-window sub-window y start position (REG[89h],REG[88h]) sub-window y end position (REG[91h],REG[90h]) main-window Figure 8-3: Picture-in-Picture Plus with SwivelView 90° enabled °...
Page 212 Page 52 Epson Research and Development Vancouver Design Center 2. Confirm the sub-window coordinates are valid. The horizontal coordinates and horizontal width must be a multiple of 32 ÷ bpp. 60 ÷ (32 ³ 4) = 7.5 (invalid) 120 ÷ (32 ÷ 4) = 15 The sub-window horizontal start coordinate is invalid.
Page 213 Epson Research and Development Page 53 Vancouver Design Center =120 ÷ (32 ÷ 4) = 15 = 0Fh Program the Sub-window Line Address Offset register. REG[80h] is set to 0Fh, and REG[81h] is set to 00h, 7. Determine the value for the sub-window X and Y start and end position registers.
Page 214: Swivelview 180
Page 54 Epson Research and Development Vancouver Design Center 8.3.3 SwivelView 180° 180° SwivelView sub-window x end position sub-window x start position (REG[8Dh],REG[8Ch]) (REG[85h],REG[84h]) sub-window main-window sub-window y end position sub-window y start position panel’s origin (REG[91h],REG[90h]) (REG[89h],REG[88h]) Figure 8-4: Picture-in-Picture Plus with SwivelView 180° enabled °...
Page 215 Epson Research and Development Page 55 Vancouver Design Center 2. Confirm the sub-window coordinates are valid. The horizontal coordinates and horizontal width must be a multiple of 32 ÷ bpp. 80 ÷ (32 ÷ 4) = 10 160 ÷ (32 ÷ 4) = 20 Sub-window horizontal coordinates and horizontal width are valid.
Page 216 Page 56 Epson Research and Development Vancouver Design Center 6. Determine the sub-window line address offset. = image width ÷ (32 ÷ bpp) number of dwords per line = 160 ÷ (32 ÷ 4) = 20 = 14h Program the Sub-window Line Address Offset registers. REG[80h] is set to 14h, and REG[81h] is set to 00h.
Page 217: Swivelview 270
Epson Research and Development Page 57 Vancouver Design Center 8.3.4 SwivelView 270° 270° SwivelView main-window sub-window y end position (REG[91h],REG[90h]) sub-window y start position sub-window (REG[89h],REG[88h]) sub-window x start position sub-window x end position (REG[85h],REG[84h]) (REG[8Dh],REG[8Ch]) panel’s origin Figure 8-5: Picture-in-Picture Plus with SwivelView 270° enabled °...
Page 218 Page 58 Epson Research and Development Vancouver Design Center 2. Confirm the sub-window coordinates are valid. The horizontal coordinates and horizontal width must be a multiple of 32 ÷ bpp. 60 ÷ (32 ÷ 4) = 7.5 (invalid) 120 ÷ (32 ÷ 4) = 15 The sub-window horizontal start coordinate is invalid.
Page 219 Epson Research and Development Page 59 Vancouver Design Center 6. Determine the sub-window line address offset. = image width ÷ (32 ÷ bpp) number of dwords per line = 120 ÷ (32 ÷ 4) = 15 = 0Fh Program the Sub-window Line Address Offset. REG[80h] is set to 0Fh, and REG[81h] is set to 00h.
Page 220: Limitations
Page 60 Epson Research and Development Vancouver Design Center 8.4 Limitations 8.4.1 SwivelView 0° and 180° In SwivelView 0° and 180°, the main window line address offset register requires the panel width to be a multiple of 32 ÷ bits-per-pixel. If this is not the case, then the main window line address offset register must be programmed to a longer line which is a multiple of 32 ÷...
Page 221: Identifying The S1D13706
Page 61 Vancouver Design Center 9 Identifying the S1D13706 The S1D13706 can be identified by reading the value contained in the Revision Code Register (REG[00h]). To identify the S1D13706 follow the steps below. 1. Read REG[00h]. 2. The production version of the S1D13706 returns a value of 28h (00101000b).
Page 222: Hardware Abstraction Layer (Hal)
Note As the SED13xx line of products changes, the HAL may change significantly or cease to be a useful tool. Seiko Epson reserves the right to change the functionality of the HAL or discontinue its use if no longer required.
Page 223 Epson Research and Development Page 63 Vancouver Design Center Table 10-1: HAL Functions (Continued) Function Description seSetSwivelViewMode Sets the SwivelView orientation of the LCD. seGetSwivelViewMode Returns the SwivelView orientation of the LCD. seCheckSwivelViewClocks Verifies the clocks are set correctly for the requested SwivelView orientation.
Page 224 Draws an ellipse centered on a given point with the specified horizontal and vertical seDrawMainWinEllipse radius. seDrawSubWinEllipse Register/Display Memory seGetLinearDisplayAddress Returns the linear address of the start of physical display memory. seGetLinearRegAddress Returns the linear address of the start of S1D13706 control registers. S1D13706 Programming Notes and Examples X31B-G-003-03 Issue Date: 01/02/23...
Page 225: Initialization
LPHAL_STRUC lpHalInfo) Description: This function registers the S1D13706 device parameters with the HAL library. The device parameters include such items as address range, register values, desired frame rate, etc. These parameters are stored in the HAL_STRUCT structure pointed to by lpHalInfo.
Page 226 Page 66 Epson Research and Development Vancouver Design Center int seInitReg(unsigned Flags) Description: This function initializes the S1D13706 registers, the LUT, assigns default surfaces and allocates memory accordingly. Parameters: Flags Provides additional information about how to perform the initialization. Valid values for Flags are: CLEAR_MEM Zero display memory as part of the initialization.
Page 227 ERR_FAILED Could not free memory. int seGetId(int * pId) Description: Reads the S1D13706 revision code register to determine the controller product and revi- sion. Parameters: A pointer to an integer to receive the controller ID. The value returned is the revision code.
Page 228: General Hal Support
Parameters: None Return Value: The return value is the size of the display buffer in bytes (1 4000h for the S1D13706). DWORD seGetAvailableMemorySize(void) Description: This function returns an offset to the last byte of memory accessible to an application.
Page 229 Epson Research and Development Page 69 Vancouver Design Center int seGetResolution(unsigned *Width, unsigned *Height) void seGetMainWinResolution(unsigned *Width, unsigned *Height) void seGetSubWinResolution(unsigned *Width, unsigned *Height) Description: seGetResolution() returns the width and height of the active surface (main window or sub- window).
Page 230 To work correctly these routines require the S1D13706 registers to be initialized prior to being called. Parameters: None.
Page 231 Epson Research and Development Page 71 Vancouver Design Center When powering up, the following steps are implemented: 1. Disable power save mode 2. Delay for LCD power up time interval [see seSetPowerUpDelay()] 3. Enable LCD power Note seSetPowerSaveMode() waits on vertical non-display (VNDP) cycles for delays. If there is no VNDP cycle, this function will freeze the system.
Page 232 Description: This function retrieves the SwivelView orientation of the LCD display. The SwivelView status is read directly from the S1D13706 registers. Calling this function when the LCD display is not initialized will result in an erroneous return value. Note seGetSwivelViewMode() was previously called seGetLcdOrientation().
Page 233 This implies two conditions for proper operation: a) The S1D13706 control registers must be configured to correct values. b) The display interface must be enabled (not in power save mode). For Intel platforms, seDelay() calls the C library time functions to delay the desired amount of time using the system clock.
Page 234 (for the S1D13706, the display blank feature is used to enable or disable the main window). seSubWinDisplayEnable() enables or disables the sub-window display.
Page 235: Advance Hal Functions
Description: Writing and debugging software under the Windows operating system greatly simplifies the development process for the S1D13706 evaluation system. One issue which impedes application programming is that of latency. Time critical operations (i.e. performance measurement) are not guaranteed any set amount of processor time.
Page 236: Surface Support
10.2.3 Surface Support The S1D13706 HAL library depends heavily on the concept of surfaces. Through surfaces the HAL tracks memory requirements of the main window and sub-window. Surfaces allow the HAL to permit or fail function calls which change the geometry of the S1D13706 display memory.
Page 237 Epson Research and Development Page 77 Vancouver Design Center The functions in this section allow the application programmer a little greater control over surfaces. int seGetSurfaceDisplayMode(void) This function determines the type of display associated with the current active surface. Description: None.
Page 238 Page 78 Epson Research and Development Vancouver Design Center DWORD seAllocMainWinSurface(DWORD Size) DWORD seAllocSubWinSurface(DWORD Size) Description: These functions allocate display buffer memory for a surface. If the surface previously had memory allocated then that memory is first released. Newly allocated memory is not cleared.
Page 239 Epson Research and Development Page 79 Vancouver Design Center void seSetMainWinAsActiveSurface(void) void seSetSubWinAsActiveSurface(void) Description: These functions set the active surface to the display indicated in the function name. Before calling one of these surface selection routines, that surface must have been allo- cated using any of the surface allocation functions.
Page 240: Register Access
Parameters: Index Offset to the first register to read. Return Value: The least significant word of the return value is the word read from the S1D13706 regis- ters. DWORD seReadRegDword(DWORD Index) Description: This routine reads four consecutive registers as a dword and returns the value.
Page 241 Epson Research and Development Page 81 Vancouver Design Center void seWriteRegWord(DWORD Index, unsigned Value) Description: This routine writes the word contained in Value to the specified index. Index Offset to the register pair to be written. Parameters: Value The value, in the least significant word, to write to the registers.
Page 242: Memory Access
10.2.5 Memory Access The Memory Access functions provide convenient method of accessing the display memory on an S1D13706 controller using byte, word or dword widths. To reduce the overhead of these function calls as much as possible, two steps were taken: •...
Page 243 Epson Research and Development Page 83 Vancouver Design Center void seWriteDisplayWords(DWORD Offset, unsigned Value, DWORD Count) Description: This routine writes one or more words to display memory starting at the specified offset. Offset Offset, in bytes, from the start of display memory to the first word to Parameters: write.
Page 244: Color Manipulation
Page 84 Epson Research and Development Vancouver Design Center 10.2.6 Color Manipulation The functions in the Color Manipulation section deal with altering the color values in the Look-Up Table directly through the accessor functions and indirectly through the color depth setting functions.
Page 245 Epson Research and Development Page 85 Vancouver Design Center void seReadLut(BYTE *pRGB, int Count) Description: seReadLut() reads one or more lookup table entries and returns the result in the array pointed to by pRGB. The read always begins at the first lookup table entry.
Page 246 Page 86 Epson Research and Development Vancouver Design Center Parameters: None. Return Value: None. unsigned seGetBitsPerPixel(void) Description: seGetBitsPerPixel() returns the current color depth for the associated display surface. Parameters: None. Return Value: The color depth of the surface. This value will be 1, 2, 4, 8, or 16.
Page 247: Virtual Display
DWORD height) Description: These functions prepare the S1D13706 to display a virtual image. “Virtual Image” describes the condition where the image contained in display memory is larger than the physical display. In this situation the physical display is used as a window into the larger display memory area (display surface).
Page 248 Page 88 Epson Research and Development Vancouver Design Center ERR_NOT_ENOUGH_MEMORY There is insufficient free display memory to set the requested virtual display size. void seVirtPanScroll(DWORD x, DWORD y) void seMainWinVirtPanScroll(DWORD x, DWORD y) void seSubWinVirtPanScroll(DWORD x, DWORD y) void seMainAndSubWinVirtPanScroll(DWORD x, DWORD y)
Page 249: Drawing
Epson Research and Development Page 89 Vancouver Design Center 10.2.8 Drawing Functions in this category perform primitive drawing on the specified display surface. Supported drawing primitive include pixels, lines, rectangles, ellipses and circles. All drawing functions are in relation to the given SwivelView mode. For example, co- ordinate (0, 0) is always the top left corner of the image, but this is physically in different corners of the panel depending on what SwivelView mode is selected.
Page 250 Page 90 Epson Research and Development Vancouver Design Center DWORD seGetPixel(long x, long y) DWORD seGetMainWinPixel(long x, long y) DWORD seGetSubWinPixel(long x, long y) Description: Returns the pixel color at the specified display location. Use seGetPixel() to read the pixel color at the specified (x,y) co-ordinates on the current active surface.
Page 251 Epson Research and Development Page 91 Vancouver Design Center void seDrawLine(long x1, long y1, long x2, long y2, DWORD Color) void seDrawMainWinLine(long x1, long y1, long x2, long y2, DWORD Color) void seDrawSubWinLine(long x1, long y1, long x2, long y2, DWORD Color) Description: These functions draw a line between two points in the specified color.
Page 252 Page 92 Epson Research and Development Vancouver Design Center void seDrawRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) void seDrawMainWinRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) void seDrawSubWinRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) Description: These routines draw a rectangle on the screen in the specified color.
Page 253 Epson Research and Development Page 93 Vancouver Design Center void seDrawCircle(long xCenter, long yCenter, long Radius, DWORD Color) void seDrawMainWinCircle(long xCenter, long yCenter, long Radius, DWORD Color) void seDrawSubWinCircle(long xCenter, long yCenter, long Radius, DWORD Color) Description: These routines draw a circle on the screen in the specified color. The circle is centered at the co-ordinate (x, y) and is drawn with the specified radius and Color.
Page 254 Page 94 Epson Research and Development Vancouver Design Center void seDrawEllipse(long xc, long yc, long xr, long yr, DWORD Color) void seDrawMainWinEllipse(long xc, long yc, long xr, long yr, DWORD Color) void seDrawSubWinEllipse(long xc, long yc, long xr, long yr, DWORD Color) Description: These routines draw an ellipse on the screen in the specified color.
Page 255: Register/Display Memory
This function returns the linear address of the start of S1D13706 control registers. Description: None. Parameters: Return Value: The return value is the linear address of the start of S1D13706 control registers. A linear address is a 32-bit offset, in CPU address space. Programming Notes and Examples S1D13706 Issue Date: 01/02/23...
Page 256: Porting Libse To A New Target Platform
The following examples assume that you have a copy of the complete source code for the S1D13706 utilities, including the makefiles, as well as a copy of the GNU Compiler v2.8.1 for Hitachi SH3.
Page 257: Building The Libse Library For Sh3 Target Example
Epson Research and Development Page 97 Vancouver Design Center 10.3.1 Building the LIBSE library for SH3 target example In the LIBSE files, there are two main types of files: • C and assembler files that contain the target specific code.
Page 258: Sample Code
Page 98 Epson Research and Development Vancouver Design Center 11 Sample Code Example source code demonstrating programming the S1D13706 using the HAL library is available on the internet at www.eea.epson.com. S1D13706 Programming Notes and Examples X31B-G-003-03 Issue Date: 01/02/23...
Page 259 S1D13706 Register Summary S1D13706 Register Summary X31B-R-001-02 X31B-R-001-02 REG[00h] R EVISION EGISTER REG[16h] H ORIZONTAL ISPLAY ERIOD TART OSITION EGISTER REG[70h] D ISPLAY EGISTER Product Code = 001010 Revision Code = 00 Horizontal Display Period Start Position Hardware Bit-per-pixel Select...
Page 260 Bit 2 Bit 1 Bit 0 Notes 10 REG[B1h] PWM Clock / CV Pulse Configuration Register 1 REG[00h] These bits are used to identify the S1D13706. For the S1D13706, the product code should be 10. REG[8Dh] S INDOW OSITION EGISTER...
Page 261 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 262 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 13706CFG Configuration Program X31B-B-001-03 Issue Date: 01/03/29...
Page 263 13706CFG ..........5 S1D13706 Supported Evaluation Platforms ..... . 5 Installation .
Page 264 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 13706CFG Configuration Program X31B-B-001-03 Issue Date: 01/03/29...
Page 265: 13706Cfg
13706CFG is an interactive Windows® 9x/ME/NT/2000 program that calculates register values for a user defined S1D13706 configuration. The configuration information can be used to directly alter the operating characteristics of the S1D13706 utilities or any program built with the Hardware Abstraction Layer (HAL) library. Alternatively, the configuration information can be saved in a variety of text file formats for use in other applications.
Page 266: Installation
Vancouver Design Center Installation Create a directory for 13706cfg.exe and the S1D13706 utilities. Copy the files 13706cfg.exe and panels.def to that directory. Panels.def contains configuration infor- mation for a number of panels and must reside in the same directory as 13706cfg.exe.
Page 267: 13706Cfg Configuration Tabs
13706CFG provides a series of tabs which can be selected at the top of the main window. Each tab allows the configuration of a specific aspect of S1D13706 operation. The tabs are labeled “General”, “Preference”, “Clocks”, “Panel”, “Panel Power”, and “Registers”.
Page 268 PCI interface and the decode addresses are determined by the system BIOS during boot-up. If using the S1D13706 Evaluation Board on a PCI based platform, both Windows and the S1D13XXX device driver must be installed. For further information on the S1D13xxx device driver, see the S1D13XXX 32-bit Windows Device Driver Installation Guide, document number X00A-E-003-xx.
Page 269: Preferences Tab
180°, or 270° in a counter-clockwise direction. This sets the initial orientation of the panel. Panel Invert The S1D13706 can invert the display data going to the LCD panel. The display data is inverted after the Look- Up Table. S/W Invert Enable The Video Invert feature can be controlled by software using REG[70h] bit 4.
Page 270: Clocks Tab
The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals. For further information regarding clocking and clock sources, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx. In automatic mode the values for CLKI and CLKI2 are calculated based on selections made for LCD timings from the Panel tab.
Page 271 Epson Research and Development Page 11 Vancouver Design Center The S1D13706 may use as many as two input clocks or as few as one. The more clocks used the greater the flexibility of choice in display type and memory speed. CLKI This setting determines the frequency of CLKI.
Page 272 Page 12 Epson Research and Development Vancouver Design Center BCLK These settings select the clock signal source and divisor for the bus interface clock (BCLK). Source The BCLK source is CLKI. Divide Specifies the divide ratio for the clock source signal.
Page 273 Epson Research and Development Page 13 Vancouver Design Center PWMCLK These controls configure various PWMCLK settings. The PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel. Enable When this box is checked, the PWMCLK circuitry is enabled.
Page 274: Panel Tab
TFT/FPLINE Predefined Panels TFT/FPFRAME Display Start The S1D13706 supports many panel types. This tab allows configuration of most panel settings such as panel dimensions, type and timings. Panel Type Selects between passive (STN) and active (TFT/D- TFD/HR-TFT) panel types. Several options may change or become unavailable when the STN/TFT setting is switched.
Page 275 Selects color STN panel format 2. This option is specif- ically for configuring 8-bit color STN panels. See the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx, for description of format 1 / format 2 data formats. Most new panels use the format 2 data format.
Page 276 TFT/FPLINE (pixels) These settings allow fine tuning of the TFT line pulse parameters and are only available when the selected panel type is TFT/D-TFD/HR-TFT. Refer to S1D13706 Hardware Functional Specification, document number X31B-A-001-xx for a complete description of the FPLINE pulse settings.
Page 277 TFT/FPFRAME (lines) These settings allow fine tuning of the TFT frame pulse parameters and are only available when the selected panel type is TFT/D-TFD/HR-TFT. Refer to S1D13706 Hardware Functional Specification, document number X31B-A-001-xx, for a complete description of the FPFRAME pulse settings.
Page 278: Panel Power Tab
S5U13706B00C evaluation board. Power Up Time Delay This setting controls the time delay between when the S1D13706 control signals are turned on and the LCD panel is powered-on. This setting must be configured according to the specification for the panel being used.
Page 279: Registers Tab
Vancouver Design Center Registers Tab The Registers tab allows viewing and direct editing the S1D13706 register values. Scroll up and down the list of registers and view their configured value based on the settings the previous tabs. Individual register settings may be changed by double-clicking on the register in the listing.
Page 280: 13706Cfg Menus
This may be used to quickly arrive at a starting point for register configuration. The only requirement is that the file being opened must contain a valid S1D13706 HAL library information block. 13706CFG supports a variety of executable file formats. Select the file type(s) 13706CFG should display in the Files of Type drop-down list and then select the filename from the list and click on the Open button.
Page 281: Save
Epson Research and Development Page 21 Vancouver Design Center Save From the Menu Bar, select “File”, then “Save” to initiate the save action. The Save menu option allows a fast save of the configuration information to a file that was opened with the Open menu option.
Page 282: Configure Multiple
Page 22 Epson Research and Development Vancouver Design Center Configure Multiple After determining the desired configuration, “Configure Multiple” allows the information to be saved into one or more executable files built with the HAL library. From the Menu Bar, select “File”, then “Configure Multiple” to display the Configure Multiple Dialog Box.This dialog box is also displayed when a file(s) is dragged onto the...
Page 283: Export
“Preview” button starts Notepad with a copy of the configuration file about to be saved. When the C Header File for S1D13706 WinCE Drivers option is selected as the export type, additional options are available and can be selected by clicking on the Options button.
Page 284: Enable Tooltips
Comments • On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13706 (i.e. Selecting TFT or STN on the Panel tab enables/disables options specific to the panel type). • The file panels.def is a text file containing operational specifications for several supported, and tested, panels.
Page 285 S1D13706 Embedded Memory LCD Controller 13706SHOW Demonstration Program Document Number: X31B-B-002-03...
Page 286 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 287 Vancouver Design Center 13706SHOW 13706SHOW is designed to demonstrate and test some of the S1D13706 display capabil- ities. The program can cycle through all color depths and display a pattern showing all available colors or shades of gray. Alternately, the user can specify a color depth and display configuration.
Page 288 Page 4 Epson Research and Development Vancouver Design Center Installation PC platform: Copy the file 13706show.exe to a directory specified in the path (e.g. PATH=C:\13706). Embedded platform: Download the program 13706show to the system. Usage PC Platform At the prompt, type:...
Page 289 Epson Research and Development Page 5 Vancouver Design Center Displays the help screen. Test Only Switches (The following switches were added for testing and validation. They are not supported at the customer level.) /bigmem Assumes memory size is 2M bytes instead of 80K bytes (for testing purposes only).
Page 290 Epson Research and Development Vancouver Design Center 13706SHOW Examples 13706SHOW is designed to demonstrate and test some of the features of the S1D13706. The following examples show how to use the program in both instances. Using 13706SHOW For Demonstration 1. To show color patterns which must be manually stepped through, type the following: 13706SHOW The program displays the default color depth as selected by 13706CFG.
Page 291 Epson Research and Development Page 7 Vancouver Design Center 5. To show solid vertical stripes, type the following: 13706SHOW /s The program displays the default color depth as selected by 13706CFG. Press any key to go to the next screen. Once all screens are shown the program exits. To exit the pro- gram immediately press the Esc key.
Page 292 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 13706SHOW Demonstration Program X31B-B-002-03 Issue Date: 01/02/23...
Page 293 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 294 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 13706PLAY Diagnostic Utility X31B-B-003-02 Issue Date: 01/02/23...
Page 295 Vancouver Design Center 13706PLAY 13706PLAY is a diagnostic utility allowing a user to read/write to all the S1D13706 registers, Look-Up Tables and display buffer. 13706PLAY is similar to the DOS DEBUG program; commands are received from the standard input device, and output is sent to the standard output device (console for Intel, terminal for embedded platforms).
Page 296 Page 4 Epson Research and Development Vancouver Design Center Installation PC platform Copy the file 13706play.exe to a directory in the path (e.g. PATH=C:\S1D13706). Embedded platform Download the program 13706play to the system. Usage PC platform At the prompt, type:...
Page 297 It may be necessary for the user to manually swap the bytes in order to perform the IO correctly. For further infor- mation on little/big endian and the S1D13706 byte/word swapping capabilities, see the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 298 Number of lines that are shown before halting the displayed data (decimal value). Initializes the S1D13706 registers with the default register settings as configured by the utility 13706CFG. To initialize the S1D13706 with different register values, reconfigure 13706PLAY using 13706CFG. For further information on 13706CFG, see the 13706PLAY User Manual, document number X31B-B-001-xx.
Page 299 Where: Color depth to be set (1/2/4/8/16 bpp). Quits the program. P [on | off] Controls the power on/off state of the S1D13706. Where: Powers on the chip. Powers off the chip. R addr [count] Reads a certain number of bytes from the specified address. If no value is provided for count, it defaults to 10h.
Page 300 Page 8 Epson Research and Development Vancouver Design Center RW addr [count] Reads a certain number of words from the specified address. If no value is provided for count, it defaults to 10h. Where: addr Address from which word(s) are read (hex).
Page 301 100 decimal). To use binary values attach a “‘b” suffix to the value (e.g. 0111‘b). Reads all the S1D13706 registers. XD index [data] Writes dword data to the register at index. If no data is specified, reads the 32-bit (dword) data from the register at index.
Page 302 Page 10 Epson Research and Development Vancouver Design Center 13706PLAY Example 1. Configure 13706PLAY using the utility 13706CFG. For further information on 13706CFG, see the 13706CFG User Manual, document number X31B-B-001-xx. 2. Type 13706PLAY to start the program. 3. Type ? for help.
Page 303 Example 1: Create a script file that reads all registers and then exits. ; This file initializes the S1D13706 and reads the registers. ; Note: after a semicolon (;), all characters on a line are ignored.
Page 304 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 13706PLAY Diagnostic Utility X31B-B-003-02 Issue Date: 01/02/23...
Page 305 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 306 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 13706BMP Demonstration Program X31B-B-004-02 Issue Date: 01/02/23...
Page 307 Vancouver Design Center 13706BMP 13706BMP is a demonstration utility used to show the S1D13706 display capabilities by rendering bitmap images on the display device. The program displays any bitmap stored in Windows BMP file format and then exits. 13706BMP supports SviwelView™ (90°, 180°, and 270°...
Page 308 Page 4 Epson Research and Development Vancouver Design Center Usage At the prompt, type: 13706bmp bmpfile1 [bmpfile2] [ds=n | ds=?] [move=n] [/noinit] [/r90 | /r180 | /r270] [/v] [/?] Where: bmpfile1 Specifies filename of the windows format bmp image used for the main window (display surface 0).
Page 309 Display Surfaces A display surface is a block of memory assigned to the main window and/or sub-window of the S1D13706. The sub-window is a feature of the S1D13706 “Picture-In-Picture Plus” feature. For further information on “Picture-In-Picture Plus”, see the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 310 Page 6 Epson Research and Development Vancouver Design Center 13706BMP Examples To display a bmp image in the main window on an LCD, type the following: 13706bmp bmpfile1.bmp ds=0 To display a bmp image in the main window with 90° SwivelView™ enabled, type the following: 13706bmp bmpfile1.bmp ds=0 /r90...
Page 311 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 312 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Windows® CE 2.x Display Drivers X31B-E-001-04 Issue Date: 01/05/25...
Page 313 Vancouver Design Center WINDOWS® CE 2.x DISPLAY DRIVERS The Windows CE display driver is designed to support the S1D13706 Embedded Memory LCD Controller running under the Microsoft Windows CE 2.x operating system. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 4, 8 and 16 bit- per-pixel SwivelView™...
Page 314 Click on “Shortcut” and replace the string “DEMO1” under the entry “Target” with “DEMO7”. Click on “OK” to finish. 5. Create a sub-directory named S1D13706 under x:\wince\platform\cepc\drivers\dis- play. 6. Copy the source code to the S1D13706 subdirectory. S1D13706 Windows® CE 2.x Display Drivers X31B-E-001-04 Issue Date: 01/05/25...
Page 315 8. Edit the file PLATFORM.BIB (located in x:\wince\platform\cepc\files) to set the de- fault display driver to the file EPSON.DLL (EPSON.DLL will be created during the build in step 13). Replace or comment out the following lines in PLATFORM.BIB: IF CEPC_DDI_VGA2BPP ddi.dll...
Page 316 2. Install Microsoft Visual C/C++ version 5.0 or 6.0. 3. Install Platform Builder 2.1x by running SETUP.EXE from compact disk #1. 4. Follow the steps below to create a “Build Epson for x86” shortcut which uses the current “Minshell” project icon/shortcut on the Windows desktop.
Page 317 Rename the icon “Build Minshell for x86” to “Build Epson for x86” by right clicking on the icon and choosing “rename”. g. Right click on the icon “Build Epson for x86” and click on “Properties” to bring up the “Build Epson for x86 Properties” window.
Page 318 13706CFG, refer to the 13706CFG Configuration Program User Manual, document number X31B-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13706 WinCE Drivers”. Save the new configuration as MODE0.H in x:\wince\platform\cepc\drivers\display\S1D13706, replacing the original configura- tion file.
Page 319 12. Generate the proper building environment by double-clicking on the Epson project icon --”Build Epson for x86”. 13. Type BLDDEMO <ENTER> at the command prompt of the “Build Epson for x86” window to generate a Windows CE image file (NK.BIN).
Page 320 Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below.
Page 321 Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13706 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.
Page 322 Page 12 Epson Research and Development Vancouver Design Center MonoPanel This option is intended for the support of monochrome panels only. The option causes palette colors to be grayscaled for correct display on a mono panel. For use with color panels this option should not be enabled.
Page 323 This means that the display driver will automatically locate the S1D13706 by scanning the PCI bus (currently only supported for the CEPC platform). If you select the address option “Other” and fill in your own custom addresses for the registers and video memory, then the display driver will not scan the PCI bus and will use the specific addresses you have chosen.
Page 324 Page 14 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Windows® CE 2.x Display Drivers X31B-E-001-04 Issue Date: 01/05/25...
Page 325 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 326 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Wind River WindML v2.0 Display Drivers X31B-E-002-03 Issue Date: 01/04/06...
Page 327 WindML v2.0. The driver package provides support for both 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13706. Source code modification is required to provide a smaller, more efficient driver for mass production.
Page 328 Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2.0 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo program. These instructions assume that Wind River’s Tornado platform is already installed.
Page 329 Mode0.h should be created using the configuration utility 13706CFG. For more infor- mation on 13706CFG, see the 13706CFG Configuration Program User Manual, docu- ment number X31B-B-001-xx available at www.erd.epson.com. 6. Build the WindML v2.0 library. From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin”...
Page 330 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Wind River WindML v2.0 Display Drivers X31B-E-002-03 Issue Date: 01/04/06...
Page 331 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 332 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Wind River UGL v1.2 Display Drivers X31B-E-003-02 Issue Date: 01/02/23...
Page 333 Vancouver Design Center Wind River UGL v1.2 Display Drivers The Wind River UGL v1.2 display drivers for the S1D13706 Embedded Memory LCD Controller are intended as “reference” source code for OEMs developing for Wind River’s UGL v1.2. The drivers provide support for both 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13706.
Page 334 Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1.2 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo software. These instructions assume that the Wind River Tornado platform is correctly installed.
Page 335 Mode0.h should be created using the configuration utility 13706CFG. For more infor- mation on 13706CFG, see the 13706CFG Configuration Program User Manual, docu- ment number X31B-B-001-xx available at www.erd.epson.com. 6. Open the S1D13706 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13706\8bpp\13706.wsp”...
Page 336 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Wind River UGL v1.2 Display Drivers X31B-E-003-02 Issue Date: 01/02/23...
Page 337 Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
Page 338 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Linux Console Driver X31B-E-004-02 Issue Date: 01/09/19...
Page 339 Page 3 Vancouver Design Center Linux Console Driver The Linux console driver for the S1D13706 Embedded Memory LCD Controller is intended as “reference” source code for OEMs developing for Linux, and supports 4, 8, and 16 bit-per-pixel color depths. A Graphical User Interface (GUI) such as Gnome can obtain the frame buffer address from this driver allowing the Linux GUI the ability to update the display.
Page 340 Before continuing with modifications for the S1D13706, you should ensure that you can build and start the Linux operating system. 2. Unzip the console driver files. Using a zip file utility, unzip the S1D13706 archive to a temporary directory. (e.g. /tmp) When completed the files: s1d13xxxfb.c...
Page 341 If your kernel version is not 2.2.17 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names.
Page 342 Note In order to use the S1D13706 console driver with X server, you need to configure the X server to use the FBDEV device. A good place to look for the necessary files and in- structions on this process is on the Internet at www.xfree86.org...
Page 343 Before continuing with modifications for the S1D13706, you should ensure that you can build and start the Linux operating system. 2. Unzip the console driver files. Using a zip file utility, unzip the S1D13706 archive to a temporary directory. (e.g. /tmp) When completed the files: Config.in...
Page 344 If your kernel version is not 2.4.5 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names.
Page 345 Note In order to use the S1D13706 console driver with X server, you need to configure the X server to use the FBDEV device. A good place to look for the necessary files and in- structions on this process is on the Internet at www.xfree86.org...
Page 346 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Linux Console Driver X31B-E-004-02 Issue Date: 01/09/19...
Page 347 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 348 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 QNX Photon v2.0 Display Driver X31B-E-005-02 Issue Date: 01/09/10...
Page 349 Vancouver Design Center QNX Photon v2.0 Display Driver The Photon v2.0 display drivers for the S1D13706 Embedded Memory LCD controller are intended as “reference” source code for OEMs developing for QNX platforms. The driver package provides support for 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13706.
Page 350 At the root of the Project source tree, type make. Note To build drivers for X86 NTO type ‘OSLIST=nto CPULIST=x86 make’. Further builds do not require all libraries to be re-built. To build only the S1D13706 display driver, change to the directory gddk_1.0/devg/S1D13706 and type make. S1D13706 QNX Photon v2.0 Display Driver...
Page 351 For the remaining steps the S5U13706B00C evaluation board must be installed on the test platform. It is recommended that the driver be verified before starting QNX with the S1D13706 as the primary display. To verify the driver, type the following command at the root of the Project source tree (gddk_1.0 directory).
Page 352 Page 6 Epson Research and Development Vancouver Design Center Comments • To restore the display driver to the default, comment out changes made to the trap file crt.$NODE. S1D13706 QNX Photon v2.0 Display Driver X31B-E-005-02 Issue Date: 01/09/10...
Page 353 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 354 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Windows® CE 3.x Display Drivers X31B-E-006-01 Issue Date: 01/05/25...
Page 355 Vancouver Design Center WINDOWS® CE 3.x DISPLAY DRIVERS The Windows CE 3.x display driver is designed to support the S1D13706 Embedded Memory LCD Controller running the Microsoft Windows CE operating system, version 3.0. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 8 and 16 bit-per-pixel SwivelView™...
Page 356 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for: 1. Windows CE Platform Builder 3.00 using the GUI interface. 2. Windows CE Platform Builder 3.00 using the command-line interface.
Page 357 Click the Set button. Click the OK button. 7. Create a new directory S1D13706, under x:\wince300\platform\cepc\drivers\display, and copy the S1D13706 driver source code into this new directory. 8. Add the S1D13706 driver component. a. From the Platform menu, select “Insert | User Component”.
Page 358 X31B-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13706 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 12. From the Platform window, click on ParameterView Tab. Show the tree for MY- PLATFORM Parameters by clicking on the ‘+’...
Page 359 CEPC_DDI_S1D13X0X=1 4. Generate the build environment by calling cepath.bat. 5. Create a new folder called S1D13706 under x:\wince300\platform\cepc\drivers\dis- play, and copy the S1D13706 driver source code into x:\wince300\platform\cepc\driv- ers\display\S1D13706. 6. Edit the file x:\wince300\platform\cepc\drivers\display\dirs and add S1D13706 into the list of directories.
Page 360 X31B-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13706 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 9. Edit the file PLATFORM.REG to match the screen resolution, color depth, and rota- tion information in MODE.H.
Page 361 Epson Research and Development Page 9 Vancouver Design Center 10. Delete all the files in the x:\wince300\release directory and delete the file x:\wince300\platform\cepc\*.bif 11. Type BLDDEMO <ENTER> at the command prompt to generate a Windows CE image file. The file generated will be x:\wince300\release\nk.bin.
Page 362 Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below.
Page 363 Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13706 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.
Page 364 Vancouver Design Center EpsonMessages This debugging option enables the display of EPSON-specific debug messages. These debug message are sent to the serial debugging port. This option should be disabled unless you are debugging the display driver, as they will significantly impact the performance of the display driver.
Page 365 Epson Research and Development Page 13 Vancouver Design Center “Rotation”=dword:0 “RefreshRate”=dword:3C “Flags”=dword:1 Note that all dword values are in hexadecimal, therefore 140h = 320, F0h = 240, and 3Ch = 60. The value for “Flags” should be 1 (LCD). When the display driver starts, it will read these values in the registry and attempt to match a mode table against them.
Page 366 To enable or disable the use of off-screen memory, edit the file: x:\wince300\platform\cepc\driv- ers\display\S1D13706\sources. In SOURCES, there is a line which, when uncom- mented, will instruct Windows CE to use off-screen display memory (if sufficient...
Page 367 Windows CE is shut down. If dis- play memory is kept powered up (set the S1D13706 in powersave mode), then the dis- play data will be maintained and this step can be skipped.
Page 368 This means that the display driver will automatically locate the S1D13706 by scanning the PCI bus (currently only supported for the CEPC platform). If you select the address option “Other” and fill in your own custom addresses for the registers and video memory, then the display driver will not scan the PCI bus and will use the specific addresses you have chosen.
Page 369: Installation Guide
The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners...
Page 370 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13XXX 32-Bit Windows Device Driver Installation Guide X00A-E-003-04 Issue Date: 01/04/17...
Page 371 This manual describes the installation of the Windows 9x/ME/NT 4.0/2000 device drivers for the S5U13xxxB00x series of Epson Evaluation Boards. The file S1D13XXX.VXD is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows 9x/ME.
Page 372 Type the driver location or select BROWSE to find it. 7. Click NEXT. 8. Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card. Select this file and click OPEN. 9. Windows then shows the path to the file. Click OK.
Page 373 Type the driver location or select BROWSE to find it. 5. Click NEXT. 6. Windows will open the installation file and show the option EPSON PCI Bridge Card. 7. Click FINISH. All ISA Bus Evaluation Cards 1.
Page 374 8. Select OTHER DEVICES from HARDWARE TYPE and Click NEXT. 9. Click HAVE DISK. 10. Specify the location of the driver and click OK. 11. Click OK. 12. EPSON PCI Bridge Card will appear in the list. 13. Click NEXT. 14. Windows will install the driver. 15. Click FINISH.
Page 375 Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Cards 1. Install the evaluation board in the computer and boot the computer. 2. Go to the CONTROL PANEL and select ADD NEW HARDWARE. 3. Click NEXT.
Page 376 7. Specify the location of the driver files and click OK. 8. Select the file S1D13XXX.INF and click OK. 9. Click OK. 10. The EPSON PCI Bridge Card should be selected in the list window. 11. Click NEXT. 12. Click NEXT.
Page 377 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 378 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 379 ..... . 20 S1D13706 Embedded Memory ......20 Manual/Software Adjustable LCD Panel Positive Power Supply (VDDH) .
Page 380 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 381: List Of Figures
Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3-1: Configuration DIP Switch Settings ......10 Table 3-2: Jumper Summary .
Page 382 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 383: Introduction
1 Introduction This manual describes the setup and operation of the S5U13706B00C Rev. 1.0 Evaluation Board. The board is designed as an evaluation platform for the S1D13706 Embedded Memory LCD Controller. This user manual is updated as appropriate. Please check the Epson Electronics America Website at www.eea.epson.com or the Epson Research and Development Website at...
Page 384: Features
• 4/8/16-bit 3.3V or 5V single color passive LCD panel support. • 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support. • Direct interface for 18-bit Epson D-TFD LCD panel support. • Direct interface for 18-bit Sharp HR-TFT LCD panel support.
Page 385: Installation And Configuration
S1D13706 LCD controller to be configured for a specified evaluation platform. 3.1 Configuration DIP Switches The S1D13706 has configuration inputs (CNF[7:0]) which are read on the rising edge of RESET#. In order to configure the S1D13706 for multiple Host Bus Interfaces a ten- position DIP switch (S1) is required.
Page 386 Page 10 Epson Research and Development Vancouver Design Center The S1D13706 has 8 configuration inputs (CONF[7:0]) which are read on the rising edge of RESET#. All S1D13706 configuration inputs are fully configurable using a ten position DIP switch as described below.
Page 387: Configuration Jumpers
Refer to the S1D13706 Hardware Functional Specification, document number X28B-A-001-xx for details. Note When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no jumper and JP6 must be set to position 2-3. GPIO0 connected GPIO0 disconnected...
Page 388 Page 12 Epson Research and Development Vancouver Design Center JP2 - CLKI2 Source JP2 selects the source for the CLKI2. Position 1-2 sets the CLKI2 source to MCLKOUT from the Cypress clock synthesizer (default setting). Position 2-3 sets the CLKI2 source to the external oscillator at U5.
Page 389 Epson Research and Development Page 13 Vancouver Design Center JP4 - GPO Polarity on H1 JP4 selects the polarity of the GPO signal available on the LCD Connector H1. Position 1-2 sends the GPO signal directly to H1 (default setting).
Page 390 Position 1-2 sets the voltage level to 5.0V (default setting). Position 2-3 sets the voltage level to 3.3V. Note When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no jumper and JP6 must be set to position 2-3. 5.0V 3.3V...
Page 391: Cpu Interface
RESET# Note A0 for these busses is not used internally by the S1D13706. If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. These pins are not used in their corresponding Host Bus Interface mode. Systems are responsible for externally connecting them to the host interface IO V S5U13706B00C Rev.
Page 392: Cpu Bus Connector Pin Mapping
CPU Bus Connector Pin Mapping Table 4-2: CPU Bus Connector (H3) Pinout Connector Comments Pin No. Connected to DB0 of the S1D13706 Connected to DB1 of the S1D13706 Connected to DB2 of the S1D13706 Connected to DB3 of the S1D13706 Ground...
Page 393 Table 4-3: CPU Bus Connector (H4) Pinout Connector Comments Pin No. Connected to A0 of the S1D13706 Connected to A1 of the S1D13706 Connected to A2 of the S1D13706 Connected to A3 of the S1D13706 Connected to A4 of the S1D13706...
Page 394: Lcd Interface Pin Mapping
FPDATxx signals at the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see S1D13706 Hardware Functional Specification, document number X31B-A-001-xx. GPO on H1 can be inverted by setting JP4 to 2-3.
Page 395 Epson Research and Development Page 19 Vancouver Design Center Table 5-2: Extended LCD Signal Connector (H2) Monochrome Color Passive Panel Color TFT Panel Passive Panel Connector Single Name Pin No. Single Others D-TFD Format 1 Format 2 4-bit 8-bit 4-bit...
Page 396: Technical Description
When JP5 is set to position 1-2, VDDH can be controlled through software to provide an output voltage from +20V to +40V. CVOUT and GPO of the S1D13706 are connected to LADJ and LON of MAX754. The output voltage (VDDH) can be adjusted from +20V to +40V in 64 steps by sending pulses to CVOUT.
Page 397: Manual/Software Adjustable Lcd Panel Negative Power Supply (Vlcd)
When JP7 is set to position 1-2, VLCD can be controlled through software to provide an output voltage from -8V to -24V. CVOUT and GPO of the S1D13706 are connected to ADJ and CTRL of MAX749. The output voltage (VLCD) can be adjusted from -8V to -24V in 64 steps by sending pulses to CVOUT.
Page 398: Software Adjustable Lcd Backlight Intensity Support Using Pwm
The buffered LCD connector (H1) provides the same LCD panel signals as those directly from S1D13706, but with voltage-adapting buffers selectable to 3.3V or 5.0V. Pin 32 on this connector provides a voltage level of 3.3V or 5.0V to the LCD panel logic (see “JP6 - LCD Panel Voltage”...
Page 399: Clock Synthesizer And Clock Options
7.1 Clock Programming The S1D13706 utilities automatically program the clock generator. If manual programming of the clock generator is required, refer to the source code for the S1D13706 utilities available on the internet at www.eea.epson.com. For further information on programming the clock generator, refer to the Cypress ICD2061A specification.
Page 400: References
Epson Research and Development Vancouver Design Center 8 References 8.1 Documents • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, document number X31B-A-001-xx. • Epson Research and Development, Inc., S1D13806 Programming Notes and Examples, document number X31B-G-003-xx. • Cypress Semiconductor Corporation, ICD2061A Data Sheet.
Page 401: Parts List
Epson Research and Development Page 25 Vancouver Design Center 9 Parts List Table 9-1: Parts List Manufacturer / Part No. / Item Designation Part Value Description Assembly Instructions "C1-C11,C13,C16- 0.1u "50V X7R +/-5%, 1206 pckg." C21,C25,C27,C29" "C26,C12" 10u 10V 10u 10V "Tantalum C-Size, 10V +/-10%"...
Page 402 Page 26 Epson Research and Development Vancouver Design Center Table 9-1: Parts List Manufacturer / Part No. / Item Designation Part Value Description Assembly Instructions 402 1% "1206 / 1%, E-96 series" 301 1% "1206 / 1%, E-96 series" 200 POT...
Page 403 Epson Research and Development Page 27 Vancouver Design Center Table 9-1: Parts List Manufacturer / Part No. / Item Designation Part Value Description Assembly Instructions "Fundamental Mode, Parallel 14.31818MHz Resonant Crystal, HC49 Low FOXS/143-20 or equivalent Profile pckg." (JP1-JP7) Micro Shunt "Computer Bracket, Blank -...
Page 404: Schematics
Page 28 Epson Research and Development Vancouver Design Center 10 Schematics Figure 10-1: S1D13706B00C Schematics (1 of 6) S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 405 Epson Research and Development Page 29 Vancouver Design Center Figure 10-2: S1D13706B00C Schematics (2 of 6) S5U13706B00C Rev. 1.0 Evaluation Board User Manual S1D13706 Issue Date: 01/02/23 X31B-G-004-04...
Page 406 Page 30 Epson Research and Development Vancouver Design Center Figure 10-3: S1D13706B00C Schematics (3 of 6) S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 407 Epson Research and Development Page 31 Vancouver Design Center Figure 10-4: S1D13706B00C Schematics (4 of 6) S5U13706B00C Rev. 1.0 Evaluation Board User Manual S1D13706 Issue Date: 01/02/23 X31B-G-004-04...
Page 408 Page 32 Epson Research and Development Vancouver Design Center Figure 10-5: S1D13706B00C Schematics (5 of 6) S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 409 Epson Research and Development Page 33 Vancouver Design Center Figure 10-6: S1D13706B00C Schematics (6 of 6) S5U13706B00C Rev. 1.0 Evaluation Board User Manual S1D13706 Issue Date: 01/02/23 X31B-G-004-04...
Page 410: Board Layout
Page 34 Epson Research and Development Vancouver Design Center 11 Board Layout Figure 11-1: S5U13706B00C Board Layout S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 411: Technical Support
Epson Research and Development Page 35 Vancouver Design Center 12 Technical Support 12.1 EPSON LCD Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 412 Page 36 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 S5U13706B00C Rev. 1.0 Evaluation Board User Manual X31B-G-004-04 Issue Date: 01/02/23...
Page 413 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 414 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors X31B-G-002-02 Issue Date: 01/02/23...
Page 415 Card Access Cycles ........8 S1D13706 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 416 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors X31B-G-002-02 Issue Date: 01/02/23...
Page 417 Figure 2-2: Toshiba 3905/12 PC Card IO Cycle ......9 Figure 4-1: S1D13706 to TMPR3905/12 Direct Connection ..... . 12...
Page 418 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors X31B-G-002-02 Issue Date: 01/02/23...
Page 419: Introduction
1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13706 Embedded Memory LCD Controller and the Toshiba MIPS TMPR3905/3912 processors. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 420: Interfacing To The Tmpr3905/12
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the TMPR3905/12 2.1 The Toshiba TMPR3905/12 System Bus The TMPR39XX family of processors features a high-speed system bus typical of modern MIPS RISC microprocessors. This section provides an overview of the operation of the CPU bus in order to establish interface requirements.
Page 421 Epson Research and Development Page 9 Vancouver Design Center Figure 2-1: “Toshiba 3905/12 PC Card Memory/Attribute Cycle,” illustrates a typical memory/attribute cycle on the Toshiba 3905/12 PC Card bus. A[25:0] CARDREG* D[31:16] CARD1CSL* CARD1CSH* CARD1WAIT* Figure 2-1: Toshiba 3905/12 PC Card Memory/Attribute Cycle Figure 2-2: “Toshiba 3905/12 PC Card IO Cycle,”...
Page 422: S1D13706 Host Bus Interface
Generic #2 Host Bus Interface which is most suitable for connection to the Toshiba TMPR3905/12 microprocessor. The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Page 423: Host Bus Interface Signals
The Host Bus Interface requires the following signals. • CLKI is a clock input required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 424: Toshiba Tmpr3905/12 To S1D13706 Interface
Oscillator Clock divider Note: When connecting the S1D13706 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: S1D13706 to TMPR3905/12 Direct Connection...
Page 425 The Generic #2 Host Bus Interface control signals of the S1D13706 are asynchronous with respect to the S1D13706 bus clock. This gives the system designer full flexibility to choose the appropriate source (or sources) for CLKI and CLKI2. The choice of whether both...
Page 426: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 latches CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 427: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 428: References
• Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X31B-G-004-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, Document Number X31B-G-003-xx.
Page 429: Technical Support
Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13706) Taiwan North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.
Page 430 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors X31B-G-002-02 Issue Date: 01/02/23...
Page 431 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 432 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the PC Card Bus X31B-G-005-02 Issue Date: 01/02/23...
Page 433 Memory Access Cycles ....... . . 8 S1D13706 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 434 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the PC Card Bus X31B-G-005-02 Issue Date: 01/02/23...
Page 435 Figure 2-2: PC Card Write Cycle ........9 Figure 4-1: Typical Implementation of PC Card to S1D13706 Interface ....12...
Page 436 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the PC Card Bus X31B-G-005-02 Issue Date: 01/02/23...
Page 437: Introduction
1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 438: Interfacing To The Pc Card Bus
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2.1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness. This section is an overview of the operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1...
Page 439 Epson Research and Development Page 9 Vancouver Design Center During a read cycle, -OE (output enable) is driven low. A write cycle is specified by driving -OE high and driving the write enable signal (-WE) low. The cycle can be lengthened by driving -WAIT low for the time needed to complete the cycle.
Page 440: S1D13706 Host Bus Interface
Generic #2 supports an external Chip Select, shared Read/Write Enable for high byte, and individual Read/Write Enable for low byte. The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 441: Host Bus Interface Signals
The S1D13706 Generic #2 Host Bus Interface requires the following signals from the PC Card bus. • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 442: Pc Card To S1D13706 Interface
4 PC Card to S1D13706 Interface 4.1 Hardware Connections The S1D13706 is interfaced to the PC Card bus with a minimal amount of glue logic. In this implementation, the address inputs (AB[16:0]) and data bus (DB[15:0] connect directly to the CPU address (A[16:0]) and data bus (D[15:0]).
Page 443: S1D13706 Hardware Configuration
The S1D13706 is a memory mapped device. The S1D13706 uses two 128K byte blocks which are selected using A17 from the PC Card bus (A17 is connected to the S1D13706 M/R# pin). The internal registers occupy the first 128K byte block and the 80K byte display buffer occupies the second 128K byte block.
Page 444: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 445: References
X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, document number X31B-G-004-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, Document Number X31B-G-003-xx. 6.2 Document Sources • PC Card website: http://www.pc-card.com.
Page 446: Technical Support
Page 16 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 447: Power Consumption
The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 448 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Power Consumption X31B-G-006-02 Issue Date: 01/02/23...
Page 449 • Internal CLK divide: internal registers allow the input clock to be divided before going to the internal logic blocks – the higher the divide, the lower the power consumption. There is a power save mode in the S1D13706. The power consumption is affected by various system design variables.
Page 450 Epson Research and Development Vancouver Design Center 1.1 Conditions The following table gives an example of a specific environment and its effects on power consumption. Table 1-1: S1D13706 Total Power Consumption in mW Power Save Mode MCLK/ S1D13706 Test Condition...
Page 451 CPU performance and LCD frame-rate, whereas power save mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13706 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility.
Page 452 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Power Consumption X31B-G-006-02 Issue Date: 01/02/23...
Page 453 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 454 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4102 / VR4111 Microprocessors X31B-G-007-02 Issue Date: 01/02/23...
Page 455 LCD Memory Access Cycles ......9 S1D13706 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 456 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4102 / VR4111 Microprocessors X31B-G-007-02 Issue Date: 01/02/23...
Page 457 Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles ......9 Figure 4-1: Typical Implementation of VR4102/VR4111 to S1D13706 Interface ... 12...
Page 458 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4102 / VR4111 Microprocessors X31B-G-007-02 Issue Date: 01/02/23...
Page 459: Introduction
1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the NEC VR4102/4111 microprocessor. The NEC VR4102 and VR4111 microprocessors are specifically designed to support an external LCD controller.
Page 460: Interfacing To The Nec Vr4102/Vr4111
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102/VR4111 2.1 The NEC VR41XX System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows®...
Page 461: Lcd Memory Access Cycles
(WR#) signals are driven low for the appropriate cycle. LCDRDY is driven low by the S1D13706 to insert wait states into the cycle. The system high byte enable is driven low for 16-bit transfers and high for 8-bit transfers.
Page 462: S1D13706 Host Bus Interface
Read/Write Enable for high byte, and individual Read/Write Enable for low byte. The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 463: Host Bus Interface Signals
The Host Bus Interface requires the following signals: • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 464: Vr4102/Vr4111 To S1D13706 Interface
HIO V RD/WR# Note: When connecting the S1D13706 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of VR4102/VR4111 to S1D13706 Interface...
Page 465: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 466: Nec Vr4102/Vr4111 Configuration
LCD controller. Physical address 0A00_0000h to 0AFF_FFFFh (16M bytes) is reserved for an external LCD controller by the NEC VR4102/4111. The S1D13706 is a memory mapped device. The S1D13706 uses two 128K byte blocks which are selected using ADD17 from the NEC VR4102/4111 (ADD17 is connected to the S1D13706 M/R# pin).The internal registers occupy the first 128K bytes block and the 80K...
Page 467: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 468: References
X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, document number X31B-G-004-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, document number X31B-G-003-xx. 6.2 Document Sources • NEC Electronics Inc. website: http://www.necel.com.
Page 469: Technical Support
Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 Epson LCD Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 470 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4102 / VR4111 Microprocessors X31B-G-007-02 Issue Date: 01/02/23...
Page 471 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 472 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4181A™ Microprocessor X31B-G-008-02 Issue Date: 01/02/23...
Page 473 LCD Memory Access Signals ......9 S1D13706 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 474 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4181A™ Microprocessor X31B-G-008-02 Issue Date: 01/02/23...
Page 475 Table 4-2: CLKI to BCLK Divide Selection ......13 List of Figures Figure 4-1: Typical Implementation of VR4181A to S1D13706 Interface ....12 Interfacing to the NEC VR4181A™ Microprocessor...
Page 476 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4181A™ Microprocessor X31B-G-008-02 Issue Date: 01/02/23...
Page 477: Introduction
Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the NEC VR4181A microprocessor. The NEC VR4181A microprocessor is specifically designed to support an external LCD controller.
Page 478: Interfacing To The Nec Vr4181A
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4181A 2.1 The NEC VR4181A System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows®...
Page 479: Lcd Memory Access Signals
The read or write enable signals (#MEMRD or #MEMWR) are driven low for the appropriate cycle and IORDY is driven low by the S1D13706 to insert wait states into the cycle. The high byte enable (UBE#) is driven low for 16-bit transfers and high for 8-bit transfers.
Page 480: S1D13706 Host Bus Interface
Enable for high byte, and individual Read/Write Enable for low byte. The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 481: Host Bus Interface Signals
The interface requires the following signals. • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 482: Vr4181A To S1D13706 Interface
S1D13706 to the NEC VR4181A. A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle. #MEMCS16 of the NEC VR4181A is connected to #LCDCS to signal that the S1D13706 is capable of 16-bit transfers.
Page 483: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 484: Nec Vr4181A Configuration
The S1D13706 is a memory mapped device. The S1D13706 uses two 128K byte blocks which are selected using A17 from the NEC VR181A (A17 is connected to the S1D13706 M/R# pin).The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block.
Page 485: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11.2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 486: References
X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, document number X31B-G-004-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, document number X31B-G-003-xx. 6.2 Document Sources • NEC Electronics Inc.website: http://www.necel.com.
Page 487: Technical Support
Epson Research and Development Page 17 Vancouver Design Center 7 Technical Support 7.1 Epson LCD Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 488 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the NEC VR4181A™ Microprocessor X31B-G-008-02 Issue Date: 01/02/23...
Page 489 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 490 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B-G-009-02 Issue Date: 01/02/23...
Page 491 User-Programmable Machine (UPM) ......12 S1D13706 Host Bus Interface ......13 Host Bus Interface Pin Mapping .
Page 492 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B-G-009-02 Issue Date: 01/02/23...
Page 493 Table 3-1: Host Bus Interface Pin Mapping ......13 Table 4-1: List of Connections from MPC821ADS to S1D13706 ....16 Table 4-3: CLKI to BCLK Divide Selection .
Page 494 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B-G-009-02 Issue Date: 01/02/23...
Page 495: Introduction
Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MPC821 microprocessor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 496: Interfacing To The Mpc821
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2.1 The MPC8XX System Bus The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern RISC microprocessors. This section provides an overview of the operation of the CPU bus in order to establish interface requirements.
Page 497: Normal (Non-Burst) Bus Transactions
Epson Research and Development Page 9 Vancouver Design Center 2.2.1 Normal (Non-Burst) Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: •...
Page 498: Burst Cycles
Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: “Power PC Memory Write Cycle” illustrates a typical memory write cycle on the Power PC system bus. SYSCLK A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Valid Transfer Start Wait States Transfer...
Page 499: Memory Controller Module
Burst cycles are mainly intended to facilitate cache line fills from program or data memory. They are normally not used for transfers to/from IO peripheral devices such as the S1D13706, therefore the interfaces described in this document do not attempt to support burst cycles.
Page 500: User-Programmable Machine (Upm)
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough flexibility to accommodate the S1D13706 and it is desirable to leave the UPM free to handle other interfacing duties, such as EDO DRAM.
Page 501: S1D13706 Host Bus Interface
MPC821 microprocessor. Generic #1 supports a Chip Select and an individual Read Enable/Write Enable for each byte. The Generic #1 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 502: Host Bus Interface Signals
The Host Bus Interface requires the following signals. • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 503: Mpc821 To S1D13706 Interface
4 MPC821 to S1D13706 Interface 4.1 Hardware Description The interface between the S1D13706 and the MPC821 requires no external glue logic. The polarity of the WAIT# signal must be selected as active high by connecting CNF5 to NIO (see Table 4-2:, “Summary of Power-On/Reset Configuration Options,” on page 18).
Page 504: Mpc821Ads Evaluation Board Hardware Connections
System (ADS). The ADS board has 5 volt logic connected to the data bus, so the interface included two 74F245 octal buffers on D[0:15] between the ADS and the S1D13706. In a true 3 volt system, no buffering is necessary. 4.2 MPC821ADS Evaluation Board Hardware Connections The following table details the connections between the pins and signals of the MPC821 and the S1D13706.
Page 505 Epson Research and Development Page 17 Vancouver Design Center Table 4-1: List of Connections from MPC821ADS to S1D13706 (Continued) MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13706 Signal Name P12-A14 P12-B14 P12-D14 P12-B13 P12-C13 SRESET P9-D15 RESET# SYSCLK P9-C2...
Page 506: S1D13706 Hardware Configuration
Vancouver Design Center 4.3 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 507: Mpc821 Chip Select Configuration
Chip select 4 is used to control the S1D13706. The following options are selected in the base address register (BR4). • BA (0:16) = 0000 0000 0100 0000 0 – set starting address of S1D13706 to 40 0000h • AT (0:2) = 0 – ignore address type bits.
Page 508: Test Software
The test software to exercise this interface is very simple. It configures chip select 4 (CS4) on the MPC821 to map the S1D13706 to an unused 256K byte block of address space and loads the appropriate values into the option register for CS4. Then the software runs a tight loop reading the 13706 Revision Code Register REG[00h].
Page 509: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 510: References
• Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User’s Manual, Motorola Publication no. MPC821UM/; available on the Internet at http://www.mot.com/SPS/ADC/pps/_subpgs/_documentation/821/821UM.html. • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, Document Number X31B-G-004-xx.
Page 511: Technical Support
Epson Research and Development Page 23 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 512 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B-G-009-02 Issue Date: 01/02/23...
Page 513 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 514 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor X31B-G-010-02 Issue Date: 01/02/23...
Page 515 Chip-Select Module ......10 S1D13706 Host Bus Interface ......11 Host Bus Interface Pin Mapping .
Page 516 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor X31B-G-010-02 Issue Date: 01/02/23...
Page 517 Figure 2-3: Chip Select Module Outputs Timing ......10 Figure 4-1: Typical Implementation of MCF5307 to S1D13706 Interface ....13 Interfacing to the Motorola MCF5307 "ColdFire"...
Page 518 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor X31B-G-010-02 Issue Date: 01/02/23...
Page 519: Introduction
Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MCF5307 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 520: Interfacing To The Mcf5307
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2.1 The MCF5307 System Bus The MCF5200/5300 family of processors feature a high-speed synchronous system bus typical of modern microprocessors. This section is an overview of the operation of the CPU bus in order to establish interface requirements.
Page 521: Burst Cycles
Epson Research and Development Page 9 Vancouver Design Center Figure 2-1: “MCF5307 Memory Read Cycle,” illustrates a typical memory read cycle on the MCF5307 system bus. BCLK0 A[31:0] SIZ[1:0], TT[1:0] D[31:0] Sampled when TA low Transfer Start Wait States Transfer...
Page 522: Chip-Select Module
They are typically not used for transfers to or from IO peripheral devices such as the S1D13706. The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not burst capable.
Page 523: S1D13706 Host Bus Interface
MFC5307 microprocessor. Generic #1 supports a Chip Select and an individual Read Enable/Write Enable for each byte. The Generic #1 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 524: Host Bus Interface Signals
The Host Bus Interface requires the following signals. • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 525: Mcf5307 To S1D13706 Interface
RESET# System RESET Note: When connecting the S1D13706 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of MCF5307 to S1D13706 Interface Interfacing to the Motorola MCF5307 "ColdFire"...
Page 526: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 527: Register/Memory Mapping
Therefore, one of the IO chip selects CS2 through CS7 is required to address the entire address space of the S1D13706. These IO chip selects have a fixed, 2M byte block size. In the example interface, chip select 4 is used to control the S1D13706. The CSBAR register should be set to the upper 8 bits of the desired base address.
Page 528: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 529: References
X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, document number X31B-G-004-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, document number X31B-G-003-xx. 6.2 Document Sources • Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447.
Page 530: Technical Support
Page 18 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 531 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 532 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Connecting to the Sharp HR-TFT Panels X31B-G-011-04 Issue Date: 01/02/23...
Page 533 Technical Support ........20 EPSON LCD Controllers (S1D13706) ..... 20 Sharp HR-TFT Panel .
Page 534 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Connecting to the Sharp HR-TFT Panels X31B-G-011-04 Issue Date: 01/02/23...
Page 535 Table 2-1: HR-TFT Power-On/Off Sequence Timing ......11 Table 2-2: S1D13706 to LQ039Q2DS01 Pin Mapping ......12 Table 3-1: S1D13706 to LQ031B1DDxx Pin Mapping .
Page 536 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Connecting to the Sharp HR-TFT Panels X31B-G-011-04 Issue Date: 01/02/23...
Page 537: Introduction
1 Introduction This application note describes the hardware and software environment required to connect to the Sharp HR-TFT panels directly supported by the S1D13706. These panels are: • Sharp LQ031B1DDXX 160 x 160 HR-TFT panel. • Sharp LQ039Q2DS01 320 x 240 HR-TFT panel.
Page 538: Connecting To The Sharp Lq039Q2Ds01 Hr-Tft
2 Connecting to the Sharp LQ039Q2DS01 HR-TFT 2.1 External Power Supplies The S1D13706 provides all necessary data and control signals to connect to the Sharp LQ039Q2DS01 320 x 240 HR-TFT panel. However, it does not provide any of the voltages required for gray scaling, gate driving, or for the digital and analog supplies.
Page 539: Digital/Analog Power Supplies
Epson Research and Development Page 9 Vancouver Design Center 2.1.2 Digital/Analog Power Supplies The digital power supply (VSHD) must be connected to a 3.3V supply. The analog power supply (VSHA) must be connected to a 5.0V supply. 2.1.3 DC Gate Driver Power Supplies...
Page 540: Ac Gate Driver Power Supplies
(offset typically -9.0V). The AC component is the common electrode driving signal ) which has a voltage of ±2.5V. V must be alternated every horizontal period and every vertical period. The S1D13706 output signal REV accomplishes this function and generates the alternating V signal which is superimposed onto V .
Page 541: Hr-Tft Mod Signal
** It is recommended to use one of the general purpose IO pins GPIO[6:4] to control the other power supplies required by the HR-TFT panel. ***The S1D13706 LCD power-on/off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0 ****LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and GPIO[3:0].
Page 542: S1D13706 To Lq039Q2Ds01 Pin Mapping
Page 12 Epson Research and Development Vancouver Design Center 2.3 S1D13706 to LQ039Q2DS01 Pin Mapping Table 2-2: S1D13706 to LQ039Q2DS01 Pin Mapping LCD Pin LCD Pin S1D13706 Description Remarks Name Pin Name See Section 2.1, “External Power Power supply of gate driver (high level) Supplies”...
Page 543 Epson Research and Development Page 13 Vancouver Design Center Table 2-2: S1D13706 to LQ039Q2DS01 Pin Mapping (Continued) LCD Pin LCD Pin S1D13706 Description Remarks Name Pin Name FPDAT17 Blue data signal (LSB) FPDAT16 Blue data signal FPDAT15 Blue data signal...
Page 544: Connecting To The Sharp Lq031B1Ddxx Hr-Tft
10 gray scale voltages and combines their function into a single IC. The S1D13706 output signal REV is used to alternate the gray scale voltages and connects to the SW input of the IR3E203 IC. The COM signal is used in generating the gate driver panel AC voltage, V and is explained in Section 3.1.4, “AC Gate Driver Power...
Page 545: Digital/Analog Power Supplies
Epson Research and Development Page 15 Vancouver Design Center 3.1.2 Digital/Analog Power Supplies The digital power supply (VSHD) must be connected to a 3.3V supply. The analog power supply (VSHA) must be connected to a 5.0V supply. 3.1.3 DC Gate Driver Power Supplies See Section 2.1.3, “DC Gate Driver Power Supplies”...
Page 546: S1D13706 To Lq031B1Ddxx Pin Mapping
Page 16 Epson Research and Development Vancouver Design Center 3.3 S1D13706 to LQ031B1DDxx Pin Mapping Table 3-1: S1D13706 to LQ031B1DDxx Pin Mapping LCD Pin LCD Pin S1D13706 Description Remarks Name Pin Name See Section 3.1, “External Power Power supply of gate driver (high level) Supplies”...
Page 547 Epson Research and Development Page 17 Vancouver Design Center Table 3-1: S1D13706 to LQ031B1DDxx Pin Mapping (Continued) LCD Pin LCD Pin S1D13706 Description Remarks Name Pin Name FPDAT17 Blue data signal (LSB) FPDAT16 Blue data signal FPDAT15 Blue data signal...
Page 548: Test Software
Vancouver Design Center 4 Test Software Test utilities and Windows CE display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 549: References
• Sharp Electronics Corporation, LQ031B1DDxx Specification. • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, Document Number X31B-G-003-xx. 5.2 Document Sources • Sharp Electronics Corporation Website: http://www.sharpsma.com.
Page 550: Technical Support
Page 20 Epson Research and Development Vancouver Design Center 6 Technical Support 6.1 EPSON LCD Controllers (S1D13706) Taiwan North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.
Page 551 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 552 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B-G-013-02 Issue Date: 01/02/23...
Page 553 Asynchronous / Synchronous Bus Operation ....8 S1D13706 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 554 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B-G-013-02 Issue Date: 01/02/23...
Page 555 Table 4-2: CLKI to BCLK Divide Selection ......13 List of Figures Figure 4-1: Typical Implementation of MC68030 to S1D13706 Interface ....12 Interfacing to the Motorola MC68030 Microprocessor...
Page 556 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B-G-013-02 Issue Date: 01/02/23...
Page 557: Introduction
Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MC68030 microprocessor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 558: Motorola Mc68030 Bus Interface
Page 8 Epson Research and Development Vancouver Design Center 2 Motorola MC68030 Bus Interface 2.1 Overview The MC68030 is a second generation enhanced microprocessor from the Motorola M68000 family of devices. The MC68030 is a 32-bit microprocessor with a 32-bit address bus and a 32-bit data bus.
Page 559 Epson Research and Development Page 9 Vancouver Design Center signals the start of a bus cycle by indicating a valid address has been placed on the bus. DS (the data strobe) is used as a condition for valid data on the data bus. SIZ selects the active portions of the data bus.
Page 560: S1D13706 Host Bus Interface
MC68K #2 Host Bus Interface which directly supports the Motorola MC68030 micropro- cessor. The MC68K #2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 561: Host Bus Interface Signals
The Host Bus Interface requires the following signals. • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 562: Mc68030 To S1D13706 Interface
Address decoding logic is required to provide the chip select (CS#) and memory/register (M/R#) signals to the S1D13706 since the MC68030 does not have a chip select module. SIZ1 is modified to signal the S1D13706 that 24-bit and 32-bit accesses are to converted into word-byte and word-word accesses, respectively.
Page 563: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 564: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 565: References
• Motorola Inc., MC68030 32-bit Enhanced Microprocessor User’s Manual, Motorola Publication no. MC68030UM/; available on the Internet at http://www.mot.com/SPS/ADC/pps/_subpgs/_documentation/ • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, Document Number X31B-G-004-xx.
Page 566: Technical Support
Page 16 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 567 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 568 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 569 Level Shift and Clamp Circuit for Vertical Logic Control Signals ..13 S1D13706 to D-TFD Panel Pin Mapping ......14 LCD Pin Mapping for Horizontal Connector (LF37SQT and LF26SCT) .
Page 570 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 571 Figure 5-1: GCP Data ......... . 19 Connecting to the Epson D-TFD Panels...
Page 572 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 573: Introduction
1 Introduction This application note describes the hardware and software required to connect the S1D13706 to two Epson D-TFD (Digital Thin Film Diode) panels, the 320 x 240 LF37SQT and the 160 x 240 LF26SCT. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 574: External Power Supplies
Vancouver Design Center 2 External Power Supplies The S1D13706 provides all necessary data and control signals to connect to the Epson LF37SQT and LF26SCT D-TFD panels. However, it does not provide any of the vertical and horizontal logic voltages, contrast or brightness voltages, or the horizontal and vertical liquid crystal driving voltages.
Page 575: Veey - Lcd Panel Drive Voltage For Vertical Power Supplies - Brightness Reference
The circuit in Figure 2-2: “VEE Switching Power Supply” uses GPIO5 (DD_P1), a S1D13706 output that has a 200KHz - 96% duty cycle signal, as the switching control of the switching power supply. The duty cycle of the input to the gate of Q1 is varied by the feedback of VEE through D1.
Page 576 R1 and R2, determine the current flowing into resistor R7. The current flowing into R7 sets the output voltage VEEY. Therefore, any change in temperature results in a corresponding change in the output of VEEY. S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 577: Vcc - Horizontal Logic Power Supply
A general purpose output pin may be used to control VCC (GPO on the S1D13706). Figure 2-4: “VCC Power Supply” shows an example of this power supply. The control signal (GPO) in this implementation activates VCC when it is low.
Page 578: Swing Power Supply For The Vertical Drive (V0Y) And Logic (Vccy / V5Y) Voltages
VEEY Figure 2-5: Swing Power Supply for Vertical System Voltages The swing power supply is controlled by the S1D13706 output signal GPIO3 (FRS). When GPIO3 is low, transistor Q1B turns on and Q1A turns off. V5Y (vertical logic low potential) goes to GND. Transistor U1 also turns on and VCCY (vertical logic high potential) = VCC = 3.3V.
Page 579: Level Shift And Clamp Circuit For Vertical Logic Control Signals
Figure 2-6: “Logic for Vertical Control Signals” shows the circuitry required for the vertical control signals. The control signals on the left are outputs from the S1D13706 and the derived control signals on the right are connected to the LCD panel.
Page 580: S1D13706 To D-Tfd Panel Pin Mapping
Vancouver Design Center 3 S1D13706 to D-TFD Panel Pin Mapping The S1D13706 outputs and the external signals are sent to the D-TFD panels through two flat cable connectors. A 30-pin connector is used for the horizontal drivers and a 12-pin connector for the vertical drivers.
Page 581: Lcd Pin Mapping For Horizontal Connector (Lf37Sqt And Lf26Sct)
VSS (GND) crystal drive Common power supply logic low and liquid X-29 VSS (GND) crystal drive Forward Scanning: Open X030 EIO1 VSS (GND) I/O enable signal Reverse Scanning: Low Connecting to the Epson D-TFD Panels S1D13706 Issue Date: 01/02/23 X31B-G-012-03...
Page 582: Lcd Pin Mapping For Y Connector (Lf37Sqt)
Forward scanning: Open Reverse scanning: Active low pulse Y-12 DYIO1 FPFRAME Start pulse signal See Section 2.5, “Level Shift and Clamp Circuit for Vertical Logic Control Signals” on page 13. S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 583: Lcd Pin Mapping For Y Connector (Lf26Sct)
13. Forward scanning: V5Y Y-11 Shift direction selection for shift registers Reverse scanning: VCCY Connect to V5Y. Ground and power supply for liquid crystal Y-12 VSS (GND) drive Connecting to the Epson D-TFD Panels S1D13706 Issue Date: 01/02/23 X31B-G-012-03...
Page 584: Power-On/Off Sequence
GPIO5 Pin IO Status low to GPIO5 inactive FRAME GPIO5 inactive to LCD signals low 1. t1 and t 4 are controlled by software and must be determined from the timing requirements of the panel connected. S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 585: Gcp Data Signal
GPIO4 (RES) signal. A one in each bit indicates the presence of a GCP pulse at that pixel/XSCL position. A zero indicates the absence of a GCP pulse. For D-TFD AC Timing required by the S1D13706, see the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 586: Programming Gcp Data
The following values must be programmed into the GCP data bit chain for the LF37SQT and LF26SCT D-TFD panels. Table 5-1: GCP Data Bit Chain Values for LF37SQT and LF26SCT Index Value Index Value Index Value Index Value S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 587: Test Software
Vancouver Design Center 6 Test Software Test utilities and display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 588: References
7 References 7.1 Documents • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, Document Number X31B-G-003-xx. 7.2 Document Sources • Epson Electronics America Website: http://www.eea.epson.com.
Page 589: Technical Support
Epson Research and Development Page 23 Vancouver Design Center 8 Technical Support 8.1 EPSON LCD Controllers (S1D13706) Taiwan North America Japan Epson Taiwan Technology Epson Electronics America, Inc. Seiko Epson Corporation & Trading Ltd. 150 River Oaks Parkway Electronic Devices Marketing Division 10F, No.
Page 590 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Connecting to the Epson D-TFD Panels X31B-G-012-03 Issue Date: 01/02/23...
Page 591 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. All other trademarks are the property of their respective owners.
Page 592 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B-G-014-02 Issue Date: 01/02/23...
Page 593 Bus Transactions ......8 S1D13706 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 594 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B-G-014-02 Issue Date: 01/02/23...
Page 595 Figure 2-2: REDCAP2 Memory Write Cycle ......9 Figure 4-1: Typical Implementation of REDCAP2 to S1D13706 Interface ....12...
Page 596 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B-G-014-02 Issue Date: 01/02/23...
Page 597: Introduction
1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13706 Embedded Memory LCD Controller and the Motorola REDCAP2 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 598: Interfacing To The Redcap2
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the REDCAP2 2.1 The REDCAP2 System Bus REDCAP2 integrates a RISC microprocessor (MCU) and a general purpose digital signal processor (DSP) on a single chip. The External Interface Module (EIM) handles the interface to external devices.
Page 599 Epson Research and Development Page 9 Vancouver Design Center Figure 2-1: “REDCAP2 Memory Read Cycle” on page 9 illustrates a typical memory read cycle on the REDCAP2 bus. A[21:0] D[15:0] OE, EB0-1 Figure 2-1: REDCAP2 Memory Read Cycle Figure 2-2: “REDCAP2 Memory Write Cycle” on page 9 illustrates a typical memory write cycle on the REDCAP2 bus.
Page 600: S1D13706 Host Bus Interface
The S1D13706 implements a 16-bit native REDCAP2 host bus interface which is used to interface to the REDCAP2 processor. The REDCAP2 host bus interface is selected by the S1D13706 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configu- ration.
Page 601: Host Bus Interface Signals
3.2 Host Bus Interface Signals The Host Bus Interface requires the following signals: • CLKI is a clock input which is required by the S1D13706 host bus interface and connects to CKO of the REDCAP2. • The address inputs AB[16:0], and the data bus DB[15:0], connect directly to the REDCAP2 bus address (A[16:0]) and data bus (D[15:0]), respectively.
Page 602: Redcap2 To S1D13706 Interface
*Note: This example uses CS1. CSn can be any of CS0-CS4. **Note: When connecting the S1D13706 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Page 603: Hardware Connections
Epson Research and Development Page 13 Vancouver Design Center 4.2 Hardware Connections The following table details the connections between the pins and signals of the REDCAP2 and the S1D13706. Table 4-1: List of Connections from REDCAP2 ADM to S5U13706B00C REDCAP2 Signal Name REDCAP2ADS Connector and Pin Name...
Page 604 Page 14 Epson Research and Development Vancouver Design Center Table 4-1: List of Connections from REDCAP2 ADM to S5U13706B00C (Continued) REDCAP2 Signal Name REDCAP2ADS Connector and Pin Name S1D13706 Signal Name CLK0 P24-3 BUSCLK P9-40 P9-47 RD/WR# P9-48 P9-46 WE0#...
Page 605: S1D13706 Hardware Configuration
Vancouver Design Center 4.3 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 606: Redcap2 Chip Select Configuration
Epson Research and Development Vancouver Design Center 4.5 REDCAP2 Chip Select Configuration In this example, Chip Select 1 controls the S1D13706. The following options are selected in the CS1 Control Register. • CSEN = 1 — Chip Select function enabled.
Page 607: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 608: References
Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, Document Number X31B-G-004-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, Document Number X31B-G-003-xx. 6.2 Document Sources • Motorola Literature Distribution Center: (800) 441-2447.
Page 609: Technical Support
Epson Research and Development Page 19 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 610 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B-G-014-02 Issue Date: 01/02/23...
Page 611 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 612 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to 8-bit Processors X31B-G-015-02 Issue Date: 01/02/23...
Page 613 The Generic 8-bit Processor System Bus ..... 8 S1D13706 Host Bus Interface ......9 Host Bus Interface Pin Mapping .
Page 614 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to 8-bit Processors X31B-G-015-02 Issue Date: 01/02/23...
Page 615 Table 4-1: Summary of Power-On/Reset Configuration Options ....12 List of Figures Figure 4-1: Typical Implementation of 8-bit Processor to S1D13706 Interface ... . 11 Interfacing to 8-bit Processors...
Page 616 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to 8-bit Processors X31B-G-015-02 Issue Date: 01/02/23...
Page 617: Introduction
1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and 8-bit processors. This document is not intended to cover all possible implementation, but provides a generic example of how such an interface can be accomplished.
Page 618: Interfacing To An 8-Bit Processor
2 Interfacing to an 8-bit Processor 2.1 The Generic 8-bit Processor System Bus Although the S1D13706 does not directly support an 8-bit CPU, an 8-bit interface can be achieved with minimal external logic. Typically, the bus of an 8-bit microprocessor is straight forward with minimal CPU and system control signals.
Page 619: S1D13706 Host Bus Interface
Generic #2 Host Bus Interface which can be adapted for use with an 8-bit processor. The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 620: Host Bus Interface Signals
The S1D13706 Generic #2 Host Bus Interface requires the following signals from an 8-bit processor. • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 621: 8-Bit Processor To S1D13706 Interface
The interface between the S1D13706 and an 8-bit processor requires minimal glue logic. A decoder is used to generate the chip select for the S1D13706 based on where the S1D13706 is mapped into memory. Alternatively, if the processor supports a chip select module, it can be programmed to generate a chip select for the S1D13706 without the need of an address decoder.
Page 622: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 623: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.11/2.12 display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 624: References
X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, document number X31B-G-004-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, Document Number X31B-G-003-xx. 6.2 Document Sources • Epson Electronics America website: http://www.eea.epson.com...
Page 625: Technical Support
Epson Research and Development Page 15 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway & Trading Ltd.
Page 626 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to 8-bit Processors X31B-G-015-02 Issue Date: 01/02/23...
Page 627 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 628 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B-G-016-02 Issue Date: 01/02/26...
Page 629 Chip-Select Module ......8 S1D13706 Host Bus Interface ......9 Host Bus Interface Pin Mapping .
Page 630 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B-G-016-02 Issue Date: 01/02/26...
Page 631 Table 4-3: WS Bit Programming ........13 List of Figures Figure 4-1: Typical Implementation of MC68VZ328 to S1D13706 Interface ... . . 11 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor...
Page 632 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B-G-016-02 Issue Date: 01/02/26...
Page 633: Introduction
1 Introduction This application note describes the hardware and software environment required to interface the S1D13706 Embedded Memory LCD Controller and the Motorola MC68VZ328 Dragonball VZ microprocessor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 634: Interfacing To The Mc68Vz328
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68VZ328 2.1 The MC68VZ328 System Bus The Motorola MC68VZ328 "Dragonball VZ" is the third generation in the Dragonball microprocessor family. The Dragonball VZ is an integrated controller designed for handheld products.
Page 635: S1D13706 Host Bus Interface
Dragonball Host Bus Interface which directly supports the Motorola MC68VZ328 micro- processor. The Dragonball Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After RESET# is released, the bus interface signals assume their selected config- uration.
Page 636: Host Bus Interface Signals
The Host Bus Interface requires the following signals. • CLKI is a clock input required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 637: Mc68Vz328 To S1D13706 Interface
The interface between the S1D13706 and the MC68VZ328 does not requires any external glue logic. Chip select module B is used to provide the S1D13706 with a chip select and A17 is used to select between memory and register accesses.
Page 638: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 639: Register/Memory Mapping
4.2.2 MC68VZ328 Chip Select and Pin Configuration The chip select used to map the S1D13706 (in this example CSB1) must have its RO (Read Only) bit set to 0, its BSW (Bus Data Width) set to 1 for a 16-bit bus, and the WS (Wait states) bits should be set to 111b to allow the S1D13706 to terminate bus cycles externally with DTACK.
Page 640: Software
OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13706 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com. S1D13706...
Page 641: References
• Motorola Inc., MC68VZ328 DragonBall-VZ® Integrated Processor User’s Manual, Motorola Publication no. MC683VZ28UM; available on the Internet at http://www.mot.com/SPS/WIRELESS/products/MC68VZ328.html. • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 Evaluation Board User Manual, Document Number X31B-G-004-xx.
Page 642: Technical Support
Page 16 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13706) Japan Taiwan North America Seiko Epson Corporation Epson Taiwan Technology & Trading Ltd. Epson Electronics America, Inc. Electronic Devices Marketing Division 10F, No. 287...
Page 643 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 644 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Integrating the CFLGA 104-pin Chip Scale Package X31B-G-018-02 Issue Date: 01/02/26...
Page 645 Technical Support ........10 EPSON LCD Controllers (S1D13706) ..... 10 List of Figures Figure 3-1: Example Perimeter Pad Routing .
Page 646 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Integrating the CFLGA 104-pin Chip Scale Package X31B-G-018-02 Issue Date: 01/02/26...
Page 647: Introduction
1 Introduction This manual provides an example for integrating the CFLGA 104-pin chip scale package (CSP) available for the S1D13706. It includes an overview of the package and provides an example of how to route the pads. This application note is updated as appropriate. Please check the Epson Electronics America website at www.eea.epson.com or the Epson Research and Development website...
Page 648: Package Description
Vancouver Design Center 2 Package Description Designing a Chip Scale Package part (i.e. S1D13706) into a printed circuit board requires the use of microvia technology. Before starting development of a PCB, consult with the board manufacturer for information about the particular microvia technology they use.
Page 649: Routing
3 Routing 3.1 Perimeter Pads Perimeter pads of the S1D13706 CSP are usually fanned out on the top layer using 0.004" traces with 0.0045" spaces at the passage between pads. The traces are terminated using standard via technology (i.e. 0.025" via with 0.012" hole).
Page 650: Inner Pads
Page 8 Epson Research and Development Vancouver Design Center 3.2 Inner Pads The inner pads on top layer require microvias connecting them with the microvia specific layer located just below the top layer. The pads on the microvia specific layer have a land size of 0.254mm (0.010") in diameter and are fanned out with 0.005"...
Page 651: References
Epson Research and Development Page 9 Vancouver Design Center 4 References 4.1 Documents • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. 4.2 Document Sources • Epson Electronics America website: http://www.eea.epson.com. • Epson Research and Development website: http://www.erd.epson.com.
Page 652: Technical Support
Page 10 Epson Research and Development Vancouver Design Center 5 Technical Support 5.1 EPSON LCD Controllers (S1D13706) Japan Taiwan North America Seiko Epson Corporation Epson Taiwan Technology & Trading Ltd. Epson Electronics America, Inc. Electronic Devices Marketing Division 10F, No. 287...
Page 653 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 654 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor X31B-G-019-02 Issue Date: 02/06/26...
Page 655 Variable-Latency IO Access Cycles ......9 S1D13706 Host Bus Interface ......11 Host Bus Interface Pin Mapping .
Page 656 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor X31B-G-019-02 Issue Date: 02/06/26...
Page 657 Figure 2-2: SA-1110 Variable-Latency IO Write Cycle ......10 Figure 4-1: Typical Implementation of SA-1110 to S1D13706 Interface ....13...
Page 658 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor X31B-G-019-02 Issue Date: 02/06/26...
Page 659: Introduction
1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13706 Embedded Memory LCD Controller and the Intel StrongARM SA-1110 Microprocessor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 660: Interfacing To The Strongarm Sa-1110 Bus
The StrongARM SA-1110 microprocessor is a highly integrated communications micro- controller that incorporates a 32-bit StrongARM RISC processor core. The SA-1110 is ideally suited to interface to the S1D13706 LCD controller and provides a high perfor- mance, power efficient solution for embedded systems.
Page 661: Variable-Latency Io Access Cycles
Epson Research and Development Page 9 Vancouver Design Center 2.1.3 Variable-Latency IO Access Cycles The first nOE assertion occurs two memory cycles after the assertion of chip select (nCS3, nCS4, or nCS5). Two memory cycles prior to the end of minimum nOE or nWE assertion (RDF+1 memory cycles), the SA-1110 starts sampling the data ready input (RDY).
Page 662 Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: illustrates a typical variable-latency IO access write cycle on the SA-1110 bus. A[25:0] ADDRESS VALID nCS4 D[31:0] DATA VALID nCAS[3:0] Figure 2-2: SA-1110 Variable-Latency IO Write Cycle S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor...
Page 663: S1D13706 Host Bus Interface
Generic #2 Host Bus Interface which is most suitable for direct connection to the SA-1110. The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Page 664: Host Bus Interface Signal Descriptions
The S1D13706 Generic #2 Host Bus Interface requires the following signals. • CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source for its internal bus and memory clocks. This clock is typically driven by the host CPU system clock.
Page 665: Strongarm Sa-1110 To S1D13706 Interface
System RESET RESET# Note: When connecting the S1D13706 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of SA-1110 to S1D13706 Interface...
Page 666: S1D13706 Hardware Configuration
Vancouver Design Center 4.2 S1D13706 Hardware Configuration The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
Page 667: Strongarm Sa-1110 Register Configuration
7 of the control register (register 1) to 0. • The CLKI signal input to the S1D13706 from one of the SDCLK[2:1] pins is a deriva- tive of the SA-1110 internal processor speed (either divide by 2 or 4). The S1D13706 Generic #2 Host Bus Interface has a maximum BCLK of 50MHz.
Page 668: Register/Memory Mapping
Each variable-latency IO chip select is assigned 128M Bytes of address space. Therefore; if nCS4 is used the S1D13706 registers will be located at 4000 0000h and the display buffer will be located at 4002 0000h. These blocks are aliased over the entire 128M byte address space.
Page 669: Software
Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13706. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13706CFG, or by directly modifying the source.
Page 670: References
Manual, Order Number 278240-001. • Epson Research and Development, Inc., S1D13706 Hardware Functional Specification, Document Number X31B-A-001-xx. • Epson Research and Development, Inc., S1D13706 Programming Notes and Examples, Document Number X31B-G-003-xx. • Epson Research and Development, Inc., S5U13706B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X31B-G-004-xx.
Page 671: Technical Support
Epson Research and Development Page 19 Vancouver Design Center 7 Technical Support 7.1 EPSON LCD Controllers (S1D13706) Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology & Trading Ltd. Electronic Devices Marketing Division 150 River Oaks Parkway 10F, No.
Page 672 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor X31B-G-019-02 Issue Date: 02/06/26...

Epson S1D13706 Technical Manual

Table of Contents

Typical System Implementation Diagrams

D.C. Characteristics

A.C. Characteristics

Clocks

Frame Rate Calculation

Display Data Formats

Look-Up Table Architecture

Sales and Technical Support

Table of Contents

1 Introduction

2 Initialization

3 Memory Models

4 Look-Up Table (LUT)

5 Power Save Mode

6 LCD Power Sequencing

7 Swivelview

8 Picture-In-Picture Plus

9 Identifying the S1D13706

10 Hardware Abstraction Layer (HAL)

11 Sample Code

Table of Contents

Manual/Software Adjustable LCD Panel Negative Power Supply (Vlcd)

1 Introduction

2 Features

3 Installation and Configuration

4 CPU Interface

5 LCD Interface Pin Mapping

6 Technical Description

7 Clock Synthesizer and Clock Options

8 References

9 Parts List

10 Schematics

11 Board Layout

12 Technical Support

Quick Links

Chapters

Related Manuals for Epson S1D13706

Summary of Contents for Epson S1D13706