Sony STR-DA7100ES Service Manual page 45

Pin No. Pin Name
60 RESET_ARM
61 LINK_ON
62 HPS
63 LOW_PWR_RDY
64 DISABLE_IF
65 GPIO0
66 GPIO1
67 SDA
68 SCL
69 GPIO6
70 GPIO7
71 GPIO8
72 GPIO9
73 REG_EN
74 REG_OUT
75 VDD
76 VSS
77 TMS
78 TDI
79 TDO
80 TCK
81 TRST
82 ARM_TMS
83 ARM_TDI
84 ARM_TDO
85 UART_TXD
86 UART_RXD
87 GPIO10
88 TMR WTCHDOG
89 MCIF_INT
90 MCIF_CS_IO
91 MCIF_CS_MEM
92 MCIF_R_NW
93 MCIF_STRB
94 MCIF_WAIT
95 MCIF_ACK
96 MCIF_OE
97 MCIF_WE
98 MCIF_BUSCLK
MCIF_DATA0,
99, 100
MCIF_DATA1
101 VDD
102 VSS
MCIF_DATA2 to
103 to 114
MCIF_DATA13
115 REG_OUT
116 VDD
117 VSS
I/O
I System reset signal input from the i. link system controller "L": reset
- Not used
- Not used
- Not used
- Not used
O Reload timer output to the main system controller
O Clock mode switch signal output terminal
- Not used
- Not used
O FSSEL signal output to the i. link DSP
O Data receive start signal and reset signal output to the i. link DSP
O SA-CD channel select signal output to the i. link DSP
I FSTATE signal input from the i. link DSP
- Not used
- Not used
- Power supply terminal (+3.3V)
- Ground terminal
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
I FSTATE signal input from the i. link DSP
- Not used
O Interrupt request signal output to the i. link system controller
I Chip select signal input from the i. link system controller
I Chip select signal input from the i. link system controller
- Not used
- Not used
O Bus wait request signal output to the i. link system controller
- Not used
I Read data input from the i. link system controller
I Read/write enable signal input from the i. link system controller
I Serial data transfer clock signal input from the i. link system controller
I/O Two-way data bus with the i. link system controller and flash memory
- Power supply terminal (+3.3V)
- Ground terminal
I/O Two-way data bus with the i. link system controller and flash memory
- Not used
- Power supply terminal (+3.3V)
- Ground terminal
STR-DA7100ES
Description
45