Fujitsu F2MC-8L F202RA Hardware Manual page 271

Figure 11.6-2 Operation of External Interrupt 2 (INT20)
Pulse waveform input
to INT20/AN4 pin
(Detection of the "L" level)
EIE2:IE20
EIF2:IF20
(IRQA state also
changes accordingly.)
Operation of interrupt
processing routine for
IRQA
PDR0:bit0
Note:
Even when the pin is used as an external interrupt input pin, the pin state can be read directly from the
port 0 data register (PDR0).
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
External interrupt input enabled state
Clear the bit within interrupt
processing routine.
Interrupt processing
RETI
Can be read at any time.
Interrupt processing
RETI
255