Sign In
Upload
Manuals
Brands
NEC Manuals
Microcontrollers
UPD70F3116(A1)
NEC UPD70F3116(A1) Manuals
Manuals and User Guides for NEC UPD70F3116(A1). We have
1
NEC UPD70F3116(A1) manual available for free PDF download: User Manual
NEC UPD70F3116(A1) User Manual (826 pages)
32-Bit Single-Chip Microcontrollers
Brand:
NEC
| Category:
Microcontrollers
| Size: 4.59 MB
Table of Contents
Table of Contents
9
Chapter 1 Introduction
18
Outline
18
Features
21
Applications
23
Ordering Information
23
Pin Configuration (Top View)
24
Configuration of Function Block
26
Internal Block Diagram
26
Internal Units
27
Differences between Products
29
Chapter 2 Pin Functions
30
List of Pin Functions
30
Pin Status
36
Description of Pin Functions
37
Types of Pin I/O Circuit and Connection of Unused Pins
45
Pin I/O Circuits
47
Chapter 3 Cpu Function
48
Features
48
CPU Register Set
49
Program Register Set
50
System Register Set
51
Operation Modes
57
Operation Mode Specification
58
Address Space
59
CPU Address Space
59
Image
60
Wrap-Around of CPU Address Space
61
Memory Map
62
Area
63
External Memory Expansion
67
Recommended Use of Address Space
68
On-Chip Peripheral I/O Registers
70
Programmable Peripheral I/O Registers
81
Specific Registers
98
System Wait Control Register (VSWC)
98
Cautions
98
Chapter 4 Bus Control Function
100
Features
100
Bus Control Pins
100
Pin Status During Internal ROM, Internal RAM, and On-Chip Peripheral I/O Access
100
Memory Block Function
101
Chip Select Control Function
102
Bus Cycle Type Control Function
105
Bus Access
106
Number of Access Clocks
106
Bus Sizing Function
107
Word Data Processing Format
107
Bus Width
108
Wait Function
114
Programmable Wait Function
114
External Wait Function
116
Relationship between Programmable Wait and External Wait
116
Idle State Insertion Function
117
Bus Hold Function
118
Function Outline
118
Bus Hold Procedure
118
Operation in Power Save Mode
119
Bus Hold Timing
119
Bus Priority Order
120
Boundary Operation Conditions
120
Program Space
120
Data Space
120
Chapter 5 Memory Access Control Function
121
SRAM, External ROM, External I/O Interface
121
Features
121
SRAM, External ROM, External I/O Access
122
Chapter 6 Dma Functions (Dma Controller)
127
Features
127
Configuration
128
Control Registers
129
DMA Source Address Registers 0 to 3 (DSA0 to DSA3)
129
DMA Destination Address Registers 0 to 3 (DDA0 to DDA3)
131
DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)
133
DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3)
134
DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)
136
DMA Disable Status Register (DDIS)
138
DMA Restart Register (DRST)
138
DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3)
139
Transfer Mode
142
Single Transfer Mode
142
Single-Step Transfer Mode
144
Block Transfer Mode
145
Transfer Types
145
Two-Cycle Transfer
145
Transfer Target
146
Transfer Type and Transfer Target
146
External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
147
DMA Channel Priorities
147
Next Address Setting Function
147
DMA Transfer Start Factors
149
Forcible Interruption
150
DMA Transfer End
150
Forcible Termination
151
Restriction Related to DMA Transfer Forcible Termination
152
Times Related to DMA Transfer
153
Precautions
154
Interrupt Factors
155
Chapter 7 Interrupt/Exception Processing Function
156
Features
156
Non-Maskable Interrupt
160
Operation
161
Restore
163
Non-Maskable Interrupt Status Flag (NP)
164
Edge Detection Function
164
Maskable Interrupts
165
Operation
165
Restore
167
Priorities of Maskable Interrupts
168
Interrupt Control Register (Xxicn)
172
Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
175
In-Service Priority Register (ISPR)
176
Maskable Interrupt Status Flag (ID)
177
Interrupt Trigger Mode Selection
177
Software Exception
186
Operation
186
Restore
187
Exception Status Flag (EP)
188
Exception Trap
189
Illegal Opcode Definition
189
Debug Trap
191
Multiple Interrupt Servicing Control
193
Interrupt Response Time
194
Periods in Which CPU Does Not Acknowledge Interrupts
196
Chapter 8 Clock Generation Function
197
Features
197
Configuration
197
Input Clock Selection
198
Direct Mode
198
PLL Mode
198
Peripheral Command Register (PHCMD)
199
Clock Control Register (CKC)
200
Peripheral Status Register (PHS)
202
PLL Lockup
203
Power Save Control
204
Overview
204
Control Registers
207
HALT Mode
210
IDLE Mode
212
Software STOP Mode
214
Securing Oscillation Stabilization Time
216
Oscillation Stabilization Time Security Specification
216
Time Base Counter (TBC)
217
Chapter 9 Timer/Counter Function
218
Timer 0
218
Features (Timer 0)
218
Function Overview (Timer 0)
219
Basic Configuration
220
Control Registers
226
Operation
250
Operation Timing
284
Timer 1
293
Features (Timer 1)
293
Function Overview (Timer 1)
293
Basic Configuration
295
Control Registers
299
Operation
313
Supplementary Description of Internal Operation
323
Timer 2
326
Features (Timer 2)
326
Function Overview (Timer 2)
326
Basic Configuration
328
Control Registers
335
Operation
352
PWM Output Operation When Timer 2 Operates in Compare Mode
370
Timer 3
373
Features (Timer 3)
373
Function Overview (Timer 3)
373
Basic Configuration
374
Control Registers
379
Operation
385
Application Examples
392
Precautions
398
Timer 4
399
Features (Timer 4)
399
Function Overview (Timer 4)
399
Basic Configuration
400
Control Register
404
Operation
405
Application Example
407
Precautions
407
Timer Connection Function
408
Overview
408
Control Register
409
Chapter 10 Serial Interface Function
410
Features
410
Asynchronous Serial Interface 0 (UART0)
411
Features
411
Configuration
412
Control Registers
414
Interrupt Requests
421
Operation
422
Dedicated Baud Rate Generator 0 (BRG0)
434
Precautions
441
Asynchronous Serial Interfaces 1, 2 (UART1, UART2)
442
Features
442
Configuration
443
Control Registers
445
Interrupt Requests
454
Operation
455
Synchronous Mode
464
Dedicated Baud Rate Generators 1, 2 (BRG1, BRG2)
469
Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
477
Features
477
Configuration
477
Control Registers
479
Operation
493
Output Pins
508
Dedicated Baud Rate Generator 3 (BRG3)
509
Chapter 11 Fcan Controller
513
Function Overview
513
Configuration
514
Configuration of Messages and Buffers
516
Time Stamp Function
517
Message Processing
520
Message Transmission
520
Message Reception
522
Mask Function
523
Protocol
525
Protocol Mode Function
525
Message Formats
526
Functions
535
Determination of Bus Priority
535
Bit Stuffing
535
Multi-Master
535
Multi-Cast
535
CAN Sleep Mode/Can Stop Mode Function
536
Error Control Function
536
Baud Rate Control Function
539
Cautions on Bit Set/Clear Function
542
Control Registers
544
Operations
596
Initialization Processing
596
Transmit Setting
609
Receive Setting
610
CAN Sleep Mode
612
CAN Stop Mode
613
Rules for Correct Setting of Baud Rate
615
Ensuring Data Consistency
619
Sequential Data Read
619
Burst Read Mode
620
Interrupt Conditions
621
Interrupts that Are Generated for FCAN Controller
621
Interrupts that Are Generated for Global CAN Interface
621
How to Shut down FCAN Controller
622
Cautions on Use
623
Chapter 12 Nbd Function
625
Pd70F3116)
625
Overview
625
NBD Function Register Map
626
NBD Function Protocol
627
NBD Function
630
RAM Monitoring, Accessing NBD Space
630
Event Detection Function
632
Chip ID Registers (TID0 to TID2)
633
Control Registers
634
Restrictions on NBD
637
General Restrictions
637
Restrictions Related to Read or Write of RAM by NBD
637
Restrictions Related to NBD Event Trigger Function
637
How to Detect Termination of DMA Initialization Via NBD Tool
637
Initialization Required for DMA (2 Channels)
638
Chapter 13 A/D Converter
642
Features
642
Configuration
642
Control Registers
646
Interrupt Requests
655
A/D Converter Operation
656
A/D Converter Basic Operation
656
Operation Modes and Trigger Modes
657
Operation in A/D Trigger Mode
660
Operation in Select Mode
660
Operation in Scan Mode
661
Operation in A/D Trigger Polling Mode
662
Operation in Select Mode
662
Operation in Scan Mode
663
Operation in Timer Trigger Mode
664
Operation in Select Mode
664
Operation in Scan Mode
665
Operation in External Trigger Mode
666
Operation in Select Mode
666
Operation in Scan Mode
667
Precautions on Operation
668
Stopping A/D Conversion Operation
668
Trigger Input During A/D Conversion Operation
668
External or Timer Trigger Interval
668
Operation in Standby Modes
668
Compare Match Interrupt in Timer Trigger Mode
669
Timing that Makes the A/D Conversion Result Undefined
669
How to Read A/D Converter Characteristics Table
670
Chapter 14 Port Functions
674
Features
674
Basic Configuration of Ports
674
Pin Functions of each Port
689
Port 0
689
Port 1
690
Port 2
693
Port 3
696
Port 4
698
Port DH
700
Port DL
702
Port CS
704
Port CT
706
Port CM
708
Operation of Port Function
710
Writing to I/O Port
710
Reading from I/O Port
710
Output Status of Alternate Function in Control Mode
710
Noise Eliminator
711
Interrupt Pins
711
Timer 10, Timer 11, Timer 3 Input Pins
712
Timer 2 Input Pins
716
Chapter 15 Reset Function
719
Features
719
Pin Functions
719
Initialization
721
Chapter 16 Flash Memory
727
Pd70F3116)
727
Features
727
Writing by Flash Programmer
727
Programming Environment
729
Communication Mode
729
Pin Connection
731
VPP Pin
731
Serial Interface Pin
731
RESET Pin
733
NMI Pin
733
MODE0 to MODE2 Pins
733
Port Pins
733
Other Signal Pins
733
Power Supply
734
Programming Method
734
Flash Memory Control
734
Flash Memory Programming Mode
735
Selection of Communication Mode
735
Communication Commands
736
Flash Memory Programming by Self-Programming
737
Outline of Self-Programming
737
Self-Programming Function
738
Outline of Self-Programming Interface
738
Hardware Environment
739
Software Environment
741
Self-Programming Function Number
742
Calling Parameters
743
Contents of RAM Parameters
744
Errors During Self-Programming
745
Flash Information
745
Area Number
746
Flash Programming Mode Control Register (FLPMC)
747
Calling Device Internal Processing
749
Erasing Flash Memory Flow
752
Continuous Writing Flow
753
Internal Verify Flow
754
Acquiring Flash Information Flow
755
Self-Programming Library
756
How to Distinguish Flash Memory and Mask ROM Versions
758
Chapter 17 Turning On/Off Power
759
Chapter 18 Electrical Specifications
761
Normal Operation Mode
761
Flash Memory Programming Mode ( PD70F3116 Only)
787
Chapter 19 Package Drawing
789
Chapter 20 Recommended Soldering Conditions
790
Appendix A Notes on Target System Design
791
Appendix B Register Index
792
Appendix C Instruction Set List
803
Functions
803
Instruction Set (Alphabetical Order)
806
Appendix D Revision History
812
Major Revisions in this Edition
812
Revision History up to Previous Edition
814
Advertisement
Advertisement
Related Products
NEC V850E/MS1 UPD70F3102
NEC V850E/MS1 UPD70F3102A
NEC UPD70F3116
NEC UPD70F3116(A)
NEC uPD70F3610
NEC uPD70F3611
NEC uPD70F3617
NEC uPD70F3743
NEC uPD70F3744
NEC uPD70F3745
NEC Categories
Monitor
Projector
Server
Telephone
Computer Hardware
More NEC Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL