Hitachi F-ZTAT H8/3036 Manuals

Manuals and User Guides for Hitachi F-ZTAT H8/3036. We have 1 Hitachi F-ZTAT H8/3036 manual available for free PDF download: Hardware Manual

Hitachi F-ZTAT H8/3036 Hardware Manual (689 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2.45 MB

Table of Contents
3
Overview
14
Block Diagram
18
Pin Description
19
Pin Arrangement
19
Pin Functions
20
Pin Functions
24
Cpu
28
Overview
28
Features
28
Differences from H8/300 CPU
29
CPU Operating Modes
30
Address Space
31
Register Configuration
32
Overview
32
General Registers
33
Control Registers
34
Initial CPU Register Values
35
Data Formats
36
General Register Data Formats
36
Memory Data Formats
37
Instruction Set
39
Instruction Set Overview
39
Instructions and Addressing Modes
40
Tables of Instructions Classified by Function
42
Basic Instruction Formats
52
Notes on Use of Bit Manipulation Instructions
53
Addressing Modes and Effective Address Calculation
53
Addressing Modes
53
Effective Address Calculation
56
Processing States
60
Overview
60
Program Execution State
61
Exception-Handling State
61
Exception-Handling Sequences
63
Reset State
64
Power-Down State
64
Basic Operational Timing
65
On-Chip Memory Access Timing
65
On-Chip Supporting Module Access Timing
66
Access to External Address Space
67
MCU Operating Modes
68
Overview
68
Operating Mode Selection
68
Register Configuration
69
Mode Control Register (MDCR)
70
System Control Register (SYSCR)
71
Operating Mode Descriptions
73
Mode 1
73
Mode 3
73
Pin Functions in each Operating Mode
74
Memory Map in each Operating Mode
74
Restrictions on Use of Mode 6
83
Exception Handling
85
Overview
85
Exception Handling Types and Priority
85
Exception Handling Operation
85
Exception Vector Table
86
Reset
88
Overview
88
Reset Sequence
88
Interrupts after Reset
90
Interrupts
90
Trap Instruction
91
Stack Status after Exception Handling
91
Notes on Stack Usage
92
Interrupt Controller
93
Overview
93
Features
93
Block Diagram
94
Pin Configuration
95
Register Configuration
95
System Control Register (SYSCR)
95
IRQ Status Register (ISR)
95
IRQ Enable Register (IER)
95
IRQ Sense Control Register (ISCR)
105
Interrupt Sources
106
External Interrupts
106
Internal Interrupts
107
Interrupt Vector Table
107
Interrupt Operation
110
Interrupt Handling Process
110
Interrupt Sequence
115
Interrupt Response Time
116
Usage Notes
117
Contention between Interrupt and Interrupt-Disabling Instruction
117
Instructions that Inhibit Interrupts
118
Interrupts During EEPMOV Instruction Execution
118
Usage Notes
118
Bus Controller
121
Overview
121
Features
121
Block Diagram
122
Input/Output Pins
123
Register Configuration
123
Register Descriptions
124
Access State Control Register (ASTCR)
124
Wait Control Register (WCR)
125
Wait State Controller Enable Register (WCER)
126
Address Control Register (ADRCR)
127
Operation
129
Area Division
129
Bus Control Signal Timing
131
Wait Modes
133
Interconnections with Memory (Example)
139
Usage Notes
141
Register Write Timing
141
Precautions on Setting ASTCR and ABWCR
141
I/O Ports
142
Overview
142
Port 1
146
Overview
146
Register Descriptions
146
Pin Functions in each Mode
148
Overview
150
Register Descriptions
151
Pin Functions in each Mode
153
Port 3
156
Overview
156
Register Descriptions
156
Port 5
159
Overview
159
Port 6
164
Overview
164
Register Descriptions
164
Pin Functions in each Mode
166
Port 7
166
Overview
169
Overview
170
Overview
173
Register Descriptions
173
Port a
177
Overview
177
Register Descriptions
178
Pin Functions
180
Port B
187
Overview
187
Register Descriptions
187
Pin Functions
189
16-Bit Integrated Timer Unit (ITU)
195
Overview
195
Features
195
Block Diagrams
198
Register Configuration
205
Register Descriptions
208
Timer Start Register (TSTR)
208
Timer Synchro Register (TSNC)
209
Timer Mode Register (TMDR)
211
Timer Function Control Register (TFCR)
214
Timer Output Master Enable Register (TOER)
216
Timer Output Control Register (TOCR)
219
Timer Counters (TCNT)
220
General Registers (GRA, GRB)
221
Buffer Registers (BRA, BRB)
222
Timer Control Registers (TCR)
223
Timer I/O Control Register (TIOR)
226
Timer Status Register (TSR)
228
Timer Interrupt Enable Register (TIER)
230
CPU Interface
232
16-Bit Accessible Registers
232
8-Bit Accessible Registers
234
Operation
235
Overview
235
Basic Functions
236
Synchronization
246
PWM Mode
248
Reset-Synchronized PWM Mode
252
Complementary PWM Mode
255
Phase Counting Mode
265
Buffering
267
ITU Output Timing
274
Interrupts
276
Setting of Status Flags
276
Clearing of Status Flags
278
Interrupt Sources
279
Usage Notes
280
Programmable Timing Pattern Controller
295
Overview
295
Features
295
Block Diagram
296
TPC Pins
297
Registers
298
Register Descriptions
299
Port a Data Direction Register (PADDR)
299
Port a Data Register (PADR)
299
Port B Data Direction Register (PBDDR)
300
Port B Data Register (PBDR)
300
Next Data Register a (NDRA)
301
Next Data Register B (NDRB)
303
Next Data Enable Register a (NDERA)
305
Next Data Enable Register B (NDERB)
306
TPC Output Control Register (TPCR)
307
TPC Output Mode Register (TPMR)
310
Operation
312
Overview
312
Output Timing
313
Normal TPC Output
314
Non-Overlapping TPC Output
316
TPC Output Triggering by Input Capture
318
Usage Notes
319
Operation of TPC Output Pins
319
Note on Non-Overlapping Output
319
Section 10 Watchdog Timer
321
Overview
321
Features
321
Block Diagram
322
Pin Configuration
322
Register Configuration
323
Register Descriptions
324
Timer Counter (TCNT)
324
Timer Control/Status Register (TCSR)
325
Reset Control/Status Register (RSTCSR)
327
Notes on Register Access
329
Operation
331
Watchdog Timer Operation
331
Interval Timer Operation
332
Timing of Setting of Overflow Flag (OVF)
333
Timing of Setting of Watchdog Timer Reset Bit (WRST)
334
Interrupts
335
Usage Notes
335
Section 11 Serial Communication Interface
336
Overview
336
Features
336
Block Diagram
338
Input/Output Pins
339
Register Configuration
339
Register Descriptions
340
Receive Shift Register (RSR)
340
Receive Data Register (RDR)
340
Transmit Shift Register (TSR)
341
Transmit Data Register (TDR)
341
Serial Mode Register (SMR)
342
Serial Control Register (SCR)
346
Serial Status Register (SSR)
350
Bit Rate Register (BRR)
354
Operation
363
Overview
363
Operation in Asynchronous Mode
365
Multiprocessor Communication
374
Synchronous Operation
381
SCI Interrupts
390
Usage Notes
391
Section 12 Smart Card Interface
396
Overview
396
Features
396
Block Diagram
397
Pin Configuration
398
Register Configuration
398
Register Descriptions
399
Smart Card Mode Register (SCMR)
399
Serial Status Register (SSR)
401
Operation
403
Overview
403
Pin Connections
403
Data Format
405
Register Settings
407
Clock
409
Data Transfer Operations
411
Usage Note
417
Section 13 A/D Converter
420
Overview
420
Features
420
Block Diagram
421
Input Pins
422
Register Configuration
423
Register Descriptions
424
A/D Data Registers a to D (ADDRA to ADDRD)
424
A/D Control/Status Register (ADCSR)
425
A/D Control Register (ADCR)
428
CPU Interface
429
Operation
430
Single Mode (SCAN = 0)
430
Scan Mode (SCAN = 1)
432
Input Sampling and A/D Conversion Time
434
External Trigger Input Timing
435
Interrupts
436
Usage Notes
436
Section 14 RAM
442
Overview
442
Block Diagram
443
Register Configuration
443
System Control Register (SYSCR)
444
Operation
445
Section 15 ROM
446
Overview
446
Overview of Flash Memory
447
Features
447
Block Diagram
448
Pin Configuration
449
Register Configuration
449
Register Descriptions
450
Flash Memory Control Register (FLMCR)
450
Erase Block Register (EBR)
454
RAM Control Register (RAMCR)
455
Flash Memory Status Register (FLMSR)
457
On-Board Programming Modes
458
Boot Mode
459
User Program Mode
466
Programming/Erasing Flash Memory
468
Program Mode
469
Program-Verify Mode
470
Erase Mode
472
Erase-Verify Mode
472
Flash Memory Protection
474
Hardware Protection
474
Software Protection
476
Error Protection
476
NMI Input Disable Conditions
478
Flash Memory Emulation by RAM
479
Flash Memory PROM Mode
480
PROM Mode Setting
480
Memory Map
480
PROM Mode Operation
481
Memory Read Mode
481
Auto-Program Mode
481
Auto-Erase Mode
481
Status Read Mode
481
PROM Mode Transition Time
491
Notes on Memory Programming
492
Notes on Flash Memory Programming/Erasing
493
Mask ROM Overview
498
Block Diagram
498
Notes on Ordering Mask ROM Version Chip
499
Section 16 Clock Pulse Generator
500
Overview
500
Block Diagram
501
Oscillator Circuit
502
Connecting a Crystal Resonator
502
External Clock Input
504
Duty Adjustment Circuit
507
Prescalers
507
Frequency Divider
507
Register Configuration
507
Division Control Register (DIVCR)
508
Usage Notes
508
Section 17 Power-Down State
509
Overview
509
Register Configuration
511
System Control Register (SYSCR)
511
Module Standby Control Register (MSTCR)
513
Sleep Mode
515
Transition to Sleep Mode
515
Exit from Sleep Mode
515
Software Standby Mode
516
Transition to Software Standby Mode
516
Exit from Software Standby Mode
516
Selection of Oscillator Waiting Time after Exit from Software Standby Mode
517
Sample Application of Software Standby Mode
518
Usage Note
518
Transition to Hardware Standby Mode
519
Exit from Hardware Standby Mode
519
Timing for Hardware Standby Mode
519
Module Standby Function
520
Module Standby Timing
520
Read/Write in Module Standby
520
Usage Notes
520
System Clock Output Disabling Function
521
Section 18 Electrical Characteristics
522
Electrical Characteristics of Masked ROM Version
522
Absolute Maximum Ratings
522
DC Characteristics
523
AC Characteristics
534
A/D Conversion Characteristics
540
Electrical Characteristics of Flash Memory Version
541
Absolute Maximum Ratings
541
DC Characteristics
542
AC Characteristics
549
A/D Conversion Characteristics
555
Flash Memory Characteristics
556
Operational Timing
558
Bus Timing
558
Control Signal Timing
562
Clock Timing
564
TPC and I/O Port Timing
564
ITU Timing
565
SCI Input/Output Timing
566
Appendix A Instruction Set
567
Instruction List
567
Operation Code Maps
582
Number of States Required for Execution
585
Appendix B Internal I/O Register Field
595
Addresses
595
Function
603
Appendix C I/O Block Diagrams
661
Port 1 Block Diagram
661
Port 2 Block Diagram
662
Port 3 Block Diagram
663
Port 5 Block Diagram
664
Port 6 Block Diagram
665
Port 7 Block Diagram
667
Port 8 Block Diagram
668
Port 9 Block Diagram
670
Port a Block Diagram
674
Port B Block Diagram
677
Appendix Dpin States
680
Port States in each Mode
680
Pin States at Reset
682
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
685
Appendix F Product Code Lineup
686
Appendix G Package Dimensions
687

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