Timing Of Watchdog Timer Overflow Flag (Wovf) Setting; Interrupts; Usage Notes; Contention Between Timer Counter (Tcnt) Write And Increment - Hitachi H8S/2338 Series Hardware Manual

10.3.4

Timing of Watchdog Timer Overflow Flag (WOVF) Setting

The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time,
the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an
internal reset signal is generated for the entire H8S/2338 Series, H8S/2328 Series, or H8S/2318
Series chip. Figure 10-7 shows the timing in this case.
ø
TCNT
Overflow signal
(internal signal)
WOVF
WDTOVF signal*
Internal reset
signal
Note: * The WDTOVF output function is not available in all models; please check the reference manual
for the relevant model for confirmation.
10.4

Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
10.5

Usage Notes

10.5.1

Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T
takes priority and the timer counter is not incremented. Figure 10-8 shows this operation.
382
H'FF
Figure 10-7 Timing of WOVF Setting
H'00
132 states
518 states
state of a TCNT write cycle, the write
2